AbiralArch commited on
Commit
2ac7363
·
verified ·
1 Parent(s): 1314969

Upload README.md with huggingface_hub

Browse files
Files changed (1) hide show
  1. README.md +52 -0
README.md ADDED
@@ -0,0 +1,52 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ ---
2
+ dataset_info:
3
+ features:
4
+ - name: instruction
5
+ dtype: string
6
+ - name: input
7
+ dtype: string
8
+ - name: output
9
+ dtype: string
10
+ - name: metadata
11
+ dtype: string
12
+ task_categories:
13
+ - text-generation
14
+ language:
15
+ - en
16
+ tags:
17
+ - verilog
18
+ - hardware-design
19
+ - hdl
20
+ - fpga
21
+ - asic
22
+ size_categories:
23
+ - 1K<n<10K
24
+ ---
25
+
26
+ # Verilog and hardware design training data collection
27
+
28
+ ## Contents
29
+
30
+ - **cvdp_expert_problems.json**: CVDP expert-level problems
31
+ - **cvdp_memory_problems.json**: CVDP memory-focused problems
32
+ - **cvdp_processor_problems.json**: CVDP processor design problems
33
+
34
+ ## Usage
35
+
36
+ ```python
37
+ from datasets import load_dataset
38
+
39
+ dataset = load_dataset('AbiralArch/verilog-training-data')
40
+ ```
41
+
42
+ ## Statistics
43
+
44
+ - **Files**: 3
45
+ - **Total Size**: 10.1 MB
46
+ - **Uploaded**: 2025-07-31 20:40:12
47
+
48
+ ## Files Available
49
+
50
+ - `cvdp_expert_problems.json`
51
+ - `cvdp_memory_problems.json`
52
+ - `cvdp_processor_problems.json`