Datasets:
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README.md
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---
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dataset_info:
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features:
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- name: instruction
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dtype: string
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- name: input
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dtype: string
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- name: output
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dtype: string
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- name: metadata
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dtype: string
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task_categories:
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- text-generation
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language:
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- en
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tags:
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- verilog
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- hardware-design
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- hdl
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- fpga
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- asic
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size_categories:
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- 1K<n<10K
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---
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# Verilog and hardware design training data collection
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## Contents
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- **cvdp_expert_problems.json**: CVDP expert-level problems
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- **cvdp_memory_problems.json**: CVDP memory-focused problems
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- **cvdp_processor_problems.json**: CVDP processor design problems
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## Usage
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```python
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from datasets import load_dataset
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dataset = load_dataset('AbiralArch/verilog-training-data')
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```
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## Statistics
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- **Files**: 3
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- **Total Size**: 10.1 MB
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- **Uploaded**: 2025-07-31 20:40:12
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## Files Available
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- `cvdp_expert_problems.json`
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- `cvdp_memory_problems.json`
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- `cvdp_processor_problems.json`
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