text: abstract: an accelerator is a specialized integrated circuit designed to
  perform specific computations faster than if those computations were
  performed by general purpose processor, cpu or gpu. state-of-the-art
  deep neural networks (dnns) are becoming progressive larger and
  different applications require different number of layers, types of layer,
  number of nodes per layer and different interconnect between consecutive
  layers. a dnn learning and inference accelerator thus need to be
  reconfigurable against those many requirements for a dnn. it needs to
  reconfigure to maximum use its on die resources, and if necessary, need to
  be able to connect with other similar dies or packages for larger and higher
  performing dnns. a field-programmable dnn learning & inference
  accelerator (fprog-dnn) using hybrid systolic/non-systolic techniques,
  distributed information/control and deep pipelined structure is proposed
  and its microarchitecture and operation presented here. 400mm2 die sizes
  are planned for 100 thousand workers (fp64) that can extend to multipledie packages. reconfigurability allows for different number of workers to
  be assigned to different layers as a function of the relative difference in
  computational load among layers. the computational delay per layer is
  made roughly the same along pipelined accelerator structure. vgg-16 and
  recently proposed inception modules are used for showing the flexibility
  of the fprog-dnn’s reconfigurability. special structures were also added
  for a combination of convolution layer, map coincidence and feedback for
  state of the art learning with small set of examples, which is the focus of a
  companion paper by the author (franca-neto, 2018). the flexibility of the
  accelerator described can be appreciated by the fact that it is able to
  reconfigure from (1) allocating all a dnn computations to a single worker
  in one extreme of sub-optimal performance to (2) optimally allocating
  workers per layer according to computational load in each dnn layer to
  be realized. due the pipelined nature of the dnn realized in the fprogdnn, the speed-up provided by fprog-dnn varies from 2x to 50x to
  gpus or tpus at equivalent number of workers. this speed-up is
  consequence of hiding the delay in transporting activation outputs from
  one layer to the next in a dnn behind the computations in the receiving
  layer. this fprog-dnn concept has been simulated and validated at
  behavioral/functional level.