# On Approximate 8-bit Floating-Point Operations Using Integer Operations
††thanks: This work was financed by the ELLIIT strategic research environment
through the project D3 ACRE – Approximate Computing Reducing Energy.

1st Theodor Lindberg  Dept. of Electrical Engineering
Linköping University
SE-581 83 Linköping, Sweden
<EMAIL_ADDRESS>2nd Oscar Gustafsson  Dept. of Electrical Engineering
Linköping University
SE-581 83 Linköping, Sweden
<EMAIL_ADDRESS>
###### Abstract

In this work, approximate eight-bit floating-point operations performed using
simple integer operations is discussed. For two-bit mantissa formats, faithful
rounding can always be obtained for the considered operations. For all
operations, correctly rounded results can be obtained for different rounding
modes, either directly or by adding a conditional carry in. For three-bit
mantissa formats, faithful rounding can be sometimes be obtained directly,
while for other operations a conditional carry in must be added. Correctly
rounded results can be obtained for most operations and rounding modes using
slightly more complicated expressions for the carry in. Hardware
implementation results for multiplication using both standard cell and FPGA
technology are presented illustrating the potential benefit of integer
computation. Especially for FPGA, significant resource savings are obtained.

###### Index Terms:

floating-point arithmetic, 8-bit floating-point, FP8

##  1 Introduction

Eight-bit floating-point (FP8) formats is an emerging topic in error resilient
applications [1, 2, 3]. It has recently even been adapted by some of the
leading edge architectures specializing in machine learning – such as the H100
Tensor Core from NVIDIA[4] and the Gaudi 2 AI accelerator from Intel[5]. Other
short floating-point formats, such as FP16, has also seen fit in Internet of
Things (IoT) devices, where low energy consumption is key[6, 7]. Together with
the increase of IoT devices, an incentive for edge computing has also emerged.
Edge computing solutions are needed in applications with low latency, such as
6G, to cope with the strict requirements. Ideas about deploying CNN networks
on IoT devices are also becoming reality, and something that will play an
eminent role in 6G networks[8].

Floating-point operations are however still expensive. While using FP8 has
many advantages in lower precision applications, such as shorter latency,
smaller memory footprint, and reduced energy consumption, very few platforms
support FP8 operations as of today. Let alone, it is not rare for smaller
microcontrollers to not include a floating-point unit (FPU) at all. Some have
for example implemented pseudo FP16 operations on eight-bit
microcontrollers[9].

Additionally, research points towards multiple FP8 formats are needed within
the same application[1, 2]. The two most prominent FP8 formats being E5M2 and
E4M3, where the numbers indicates how many exponent and mantissa bits they use
respectively. Both being supported on the H100 Tensor Core and Gaudi 2[4, 5].

In this work, the implementation of approximate FP8 operations using integer
arithmetic operations is considered. This allows implementation of approximate
FP8-operations using integer vector/SIMD instruction, something that can be
efficient when there is no hardware support for FP8. It is shown that for
certain rounding modes, correctly rounded results can be obtained. Also, it is
shown that by forming a carry-in term, most operations and rounding-modes can
be supported. Expressions for these carry-in terms are provided.
Implementation results for FP8 multiplication show that the integer operation
approach is attractive, especially for FPGA implementation.

##  2 Approximate Floating-Point Operations in the Logarithmic Domain

A normal floating-point number $x$ can be expressed using the triplet
$(s_{x},e_{x},m_{x})$ such that

$x=(-1)^{s_{x}}(1+m_{x})2^{e_{x}},$ (1)

where $s_{x}\in\\{0,1\\}$, $0\leq m_{x}<1$, and $e_{\min}\leq e_{x}\leq
e_{\max}$.

The binary interchange formats usually follow the IEEE 754-2019 Standard[10]
where the aforementioned triplet is stored as three fields; a sign bit
$S_{x}$, follow by a $W_{E}$-bit biased exponent ${E_{x}=e_{x}+b}$, and a
$(p-1)$-bit trailing integral significand $M_{x}$, where the bias $b$ is equal
to $2^{W_{E}-1}-1$ and $M_{x}$ equals $m_{x}\cdot 2^{p-1}$[11]. Figures 1a and
1b illustrates the E5M2 and E4M3 binary interchange formats as defined in [3].

(a) The E5M2 format. (b) The E4M3 format.

Figure 1: Binary representation of the considered FP8 formats.

A floating-point number of such form can be converted to a sign-magnitude
fixed-point number $\hat{X}$ in the LNS domain using Mitchell’s
approximation[12], as explained in [13], by

$(-1)^{s_{x}}\log_{2}|x|\approx X-B=\hat{X},$ (2)

where $X$ is the binary representation of $x$ and $B$ equals $b\ll(p-1)$. The
operation is thus very cheap and the conversion back from LNS is simply
interpreting

$\hat{X}+B$ (3)

as a floating-point number. The fixed-point number $\hat{X}$ consists of a
sign bit $S_{x}$, an integer part $E_{x}$, and a fractional part $M_{x}$.
Similarly, the constant $B$ can be interpreted as the fixed-point
representation of the bias $b$.

Table I shows a collection of approximate operations presented in [13], which
serve as a starting point in this work. The constant $B$ depends on the format
and equals ${(15\ll 2)=60=\mathtt{0x3c}}$ for E5M2, and ${(7\ll
3)=56=\mathtt{0x38}}$ for E4M3. Negative constants are written as eight-bit
signed numbers using two’s complement.

TABLE I: Approximate Operations in LNS Operation | Mathematical notation | Expression in LNS
---|---|---
Multiplication | $x\times y$ | $X+Y-B$
Square | $x^{2}$ | $X\ll 1-B$
Division | $x/y$ | $X-Y+B$
Reciprocal | $1/x$ | $-X+2B$
Square-root | $\sqrt{x}$ | $X\gg 1+B/2$
Reciprocal square-root | $1/\sqrt{x}$ | $-X\gg 1+3B/2$

##  3 Error Analysis and Compensations

As the operations are performed in the LNS domain and the aim is to achieve
different rounding modes, it makes sense to reason in terms of number of units
in the last place (ulp). While there exists several definitions of the ulp
function[14], this work uses a slight modification of the definition from
Goldberg [15]. The definition from Goldberg states if the floating-point
$d_{0}.d_{1}\dots d_{p-1}\beta^{e}$ is used to represent a number $z$, then
its error is by

$|d_{0}.d_{1}\dots d_{p-1}\ -z/\beta^{e}|\beta^{p-1}$ (4)

ulps, where $\beta$ is the radix. However, to differentiate over and under
approximations the absolute error is not used. While $z$ may be any real
number, to achieve a particular rounding mode the reference is the quantized
value of $z$ after using the rounding mode of interest. The result from an
operation before quantization is referred to as the mathematically exact
result.

Seven different rounding modes are taken into consideration in this work:

  1. 1.

RNe: round to closest, ties to even,

  2. 2.

RNa: round to closest, ties to away,

  3. 3.

RNz: round to closest, ties to zero,

  4. 4.

RU: round towards positive infinity,

  5. 5.

RD: round towards negative infinity,

  6. 6.

RZ: round towards zero,

  7. 7.

faithful rounding.

The six first rounding modes are defined by the IEEE 754-2019 Standard[10],
where RNe is the default mode. RNz was introduced in the revision of the 2008
Standard, and was added specifically for augmented operations[10, 16].

A result is considered faithful if $\operatorname{RD}(x)$ or
$\operatorname{RU}(x)$ is always returned[11], faithful rounding is therefore
defined in this work as a mode, $\circ$, that fulfills

$\operatorname{RD}(x)\leq\circ(x)\leq\operatorname{RU}(x).$ (5)

Due to the similarities between the modes, many expressions for the error
compensations are likely to be shared. Remember, the only difference between
the modes with correct rounding is the handling of tie breaks, and the
difference between the modes with direct rounding is the handling of sign.

###  3.1 E5M2

This section studies the considered operations for the E5M2 format.

####  3.1.1 Multiplication

The multiplication is approximated as

$X+Y-B=X+Y+\mathtt{0xc4}.$ (6)

Figure 2 shows the error compared to the mathematically exact result. As the
error is always positive and at most $1/2$ ulp, both RNz and RZ are obtained
without any error correction.

Figure 2: Error in ulp for approximate E5M2 multiplication using (6) compared
to the mathematically exact result.

To study the other rounding modes further, the quantized error for each mode
is calculated. Figure 3 shows the error with regards to RNe. From here it can
be seen that one ulp must be added when $m_{x}$ equals $0.25$ and $m_{y}$
equals $0.5$, or vice versa. The ulp can be added via a conditional carry in,
$c_{\mathrm{in}}$, as

$c_{\mathrm{in}}=x_{0}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}.$ (7)

Figure 3: Error in ulp for approximate E5M2 multiplication using (6) compared
to RNe.

The carry-in expression for RNa only differs from (7) at the other tie break,
i.e., when both $m_{x}$ and $m_{y}$ equal $0.5$, leading to

$c_{\mathrm{in}}=x_{0}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}.$ (8)

The directed modes RU and RD are correct when one of the operands are zero.
For the remaining cases, a carry in should be added depending on the sign or
the result, $S_{r}=S_{x}\oplus S_{y}$, as

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0muS\mkern-1.0mu}\mkern
1.0mu_{r}\left(x_{0}+x_{1}\right)\left(y_{0}+y_{1}\right)$ (9)

for RU and

$c_{\mathrm{in}}=S_{r}\left(x_{0}+x_{1}\right)\left(y_{0}+y_{1}\right)$ (10)

for RD.

####  3.1.2 Square

The square is approximated as

$X\ll 1-B=X\ll 1+\mathtt{0xc4},$ (11)

and can be deducted from multiplication with $m_{y}=m_{x}$. Hence, the
rounding modes RNe, RNz, RD, and RZ are all achieved without any carry in,
i.e. $c_{\mathrm{in}}=0$.

The edge case for RNa is when $m_{x}$ equals $0.5$, which gives the boolean
expression

$c_{\mathrm{in}}=x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}$ (12)

for the carry in.

RU is only correct when $m_{x}=0$, so the carry in therefore becomes

$c_{\mathrm{in}}=x_{0}+x_{1}.$ (13)

####  3.1.3 Division

Unlike for the previous cases, the division approximation

$X-Y+B=X-Y+\mathtt{0x3c},$ (14)

gives an over-approximation, as shown in Fig. 4. However, as the error is in
$[0,1\,\mathrm{ulp}]$ it is possible to decrease the constant such that an
under-approximation is obtained, see Fig. 5, and a conditional carry in can
compensate the error.

Figure 4: Error in ulp for approximate E5M2 division using (14), compared to
the mathematically exact result. Figure 5: Error in ulp for approximate E5M2
division using (15), compared to the mathematically exact result.

The new expression with a conditional carry in thus becomes

$X-Y+B-1+c_{\mathrm{in}}=X-Y+\mathtt{0x3b}+c_{\mathrm{in}}.$ (15)

The modes with correct rounding, RNe, RNa, and RNz, can all share the same
carry in expression

$c_{\mathrm{in}}=x_{0}+x_{1}+y_{0}y_{1}+\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1},$ (16)

while the other modes have some variations. RZ, RU, and RD all share the term

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}+x_{0}x_{1}y_{0}y_{1},$ (17)

but RU and RD also consider the resulting sign $S_{r}=S_{x}\oplus S_{y}$ as

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0muS\mkern-1.0mu}\mkern
1.0mu_{r}+\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}+x_{0}x_{1}y_{0}y_{1}$ (18)

and

$c_{\mathrm{in}}=S_{r}+\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}+x_{0}x_{1}y_{0}y_{1},$ (19)

respectively.

####  3.1.4 Reciprocal

Reciprocal is the same as division with numerator equal to 1, so the
expression

$-X+2B=-X+\mathtt{0x88}$ (20)

results in an over approximation, and the constant must therefore be decreased
to $\mathtt{0x87}$ leading to

$-X+2B-1+c_{\mathrm{in}}=-X+\mathtt{0x87}+c_{\mathrm{in}}$ (21)

RNe, RNa, RNz must be compensated for $m_{x}=0$ and $m_{x}=0.75$, so the carry
in expression thus becomes

$c_{\mathrm{in}}=x_{0}x_{1}+\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}.$ (22)

For RZ, the edge case is only when $m_{x}=0$, which gives the carry in
expression

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}.$
(23)

RU and RD again only differ at the sign, $S_{r}=0\oplus S_{x}=x_{7}$, as shown
in (24) and (25) respectively.

$c_{\mathrm{in}}=x_{7}+\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1},$
(24) $c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{7}+\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}$
(25)

####  3.1.5 Square-Root

The square-root approximate is determined as

$X\gg 1+\frac{B}{2}=X\gg 1+\mathtt{0x1e}.$ (26)

This gives correct rounding for RNe, RNa, and RNz. However, (26) will under-
approximate RU, and over-approximate the other directed modes. It is therefore
not possible to select a constant such that all rounding modes can be achieved
by solely selecting the carry in. RU can be compensated by forwarding the last
bit to the carry in,

$c_{\mathrm{in}}=x_{0}.$ (27)

The error of (26) repeats itself every other exponent for other formats, as
the last bit of the exponent field will shift down to the mantissa. However
since there are so few mantissa bits, this property does not appear here.

####  3.1.6 Reciprocal Square-Root

The approximate reciprocal square-root,

$-X\ll 1+\frac{3B}{2}=-X\ll 1+\mathtt{0x5a},$ (28)

yields a slight over-approximation, however due to quantization the error
compensation is identical to that of the square-root (26).

###  3.2 E4M3

The method for deciding error compensation for E4M3 is similar to that of
E5M2, and is therefore kept more brief.

It is here important to note that even though the boolean expressions for the
carry ins for E4M3 will be large, they will in fact map very well to FPGA
architectures. This is because the expression only depends on six variables at
most, i.e. the two mantissas, and can therefore fit inside a single LUT on
many architectures. Furthermore, the synthesis tool may even combine the first
full adder and the carry in as they both solely depend on $m_{x}$ and $m_{y}$.

####  3.2.1 Multiplication

For multiplication, the approximation

$X+Y-B=X+Y+\mathtt{0xc8},$ (29)

is used. Figure 6 shows the error compared to the mathematically correct
result, and as the error is at most $-1.5$ ulp, none of the rounding modes are
obtained directly. Consequently, RU and RD are not achievable.

Figure 6: Error in ulp for the approximate E4M3 multiplication in (29)
compared to the mathematically exact result.

The carry in expression for RNe however becomes

$c_{\mathrm{in}}=x_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{1}y_{0}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2},$ (30)

while RNa must correct a couple of additional tie break:

$c_{\mathrm{in}}=x_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{2}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}.$ (31)

As the approximation gives a slightly smaller result, the tie breaks for RNz
will be correct and the carry in expression becomes

$c_{\mathrm{in}}=x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}+x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}x_{1}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{0}x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{0}y_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}y_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}+x_{1}x_{2}y_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{1}y_{0}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}.$ (32)

Lastly, the boolean expression for obtaining RZ is

$c_{\mathrm{in}}=x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{1}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{0}x_{1}y_{0}y_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}.$ (33)

Faithful rounding can be obtained in several ways, one is to check if $m_{x}$
and $m_{y}$ are greater than $0$ which gives the carry expression

$c_{\mathrm{in}}=(x_{2}+x_{1}+x_{0})(y_{2}+y_{1}+y_{0}).$ (34)

####  3.2.2 Square

From using the approximation

$X\ll 1-B=X\ll 1+\mathtt{0xc8},$ (35)

the carry in compensation for RNe and RNz becomes

$c_{\mathrm{in}}=x_{2}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}+x_{0}x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2},$ (36)

while RNa has a slightly smaller expression of

$c_{\mathrm{in}}=x_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2}+x_{2}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}$ (37)

as more cases must be compensated for. RU will not work since the error will
be $-1.5$ ulp at most (as noted in Section 3.2.1), but the same expression for
RN and RZ can be share:

$c_{\mathrm{in}}=x_{0}x_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}+x_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}.$ (38)

Faithful rounding can be achieved by adding an extra ulp when $m_{x}$ equals
$0.375$ or $0.5$ by

$c_{\mathrm{in}}=x_{2}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{0}+\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2}x_{1}x_{0}.$ (39)

####  3.2.3 Division

Similar to the case for E5M2, the constant must be decremented such that the
carry in can compensate the error. The division for E4M3 will thus be
performed as

$X-Y+B-1+c_{\mathrm{in}}=X-Y+\mathtt{0x37}+c_{\mathrm{in}}.$ (40)

The three correctly rounded modes, RNe, RNa, and RNz, share the same
expression

$c_{\mathrm{in}}=x_{0}x_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}+x_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{2}y_{1}y_{2}+x_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}+x_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}+y_{0}y_{1}y_{2}+\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{2}+x_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}+x_{2}y_{0}y_{2}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}$ (41)

for the carry in. No error compensation can be found for the directed modes
however, as the error is $\pm 1$ ulp.

The error plot for division in E4M3 looks similar to that of E5M2, Fig. 5, and
from there it is possible to see that faithful rounding can be achieved by
adding the carry in when $m_{y}=0$ and when $m_{x}=m_{y}$. This can be
realized by the boolean expression

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{2}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0muy\mkern-1.0mu}\mkern
1.0mu_{0}+\overline{(x_{2}\oplus y_{2})}\,\overline{(x_{1}\oplus
y_{1})}\,\overline{(x_{0}\oplus y_{0})}.$ (42)

####  3.2.4 Reciprocal

Also here must the constant be decremented as

$-X+2B-1+c_{\mathrm{in}}=-X+\mathtt{0x6f}+c_{\mathrm{in}}.$ (43)

The directed rounding modes cannot be obtained here either, since the error
has two different signs, just as before. The carry in expression for the
correctly rounded modes on the other hand is

$c_{\mathrm{in}}=x_{0}x_{1}x_{2}+\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}.$ (44)

As the reciprocal is just a sub case of division, faithful rounding can be
obtained by simply adding a carry in when $m_{x}=0$ by

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{0}.$
(45)

####  3.2.5 Square-Root

The approximation

$X\gg 1+\frac{B}{2}-1+c_{\mathrm{in}}=X\gg 1+\mathtt{0x1b}+c_{\mathrm{in}}.$
(46)

is used. It will however under-approximate RNe, RNa, and RNz when the least
significant bit of the exponent is $1$, the expression thus becomes

$c_{\mathrm{in}}=\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{3}+x_{0}+x_{1}+x_{2}.$ (47)

The fact that the error depends on $x_{3}$ is due to the right shift mentioned
in Section 3.1.5.

A maximum error of $-2$ ulps is obtained when comparing with RU, so
compensating with a carry in is thus not possible. However the rounding modes
RD and RZ are possible to obtain by using

$c_{\mathrm{in}}=x_{3}x_{0}+\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{3}\left(x_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}+x_{0}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}+\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{1}\mkern
1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern 1.0mu_{2}\right)$ (48)

as the expression for the carry in. RD and RZ are naturally the same as the
square-root will by definition produce a positive number.

####  3.2.6 Reciprocal Square-Root

Performing the reciprocal square-root approximation as

$-X\ll 1+\frac{3B}{2}=-X\ll+\mathtt{0x54},$ (49)

will over-approximate all rounding modes except RU. Hence, the expression used
is

$-X\ll 1+\frac{3B}{2}-1+c_{\mathrm{in}}=-X\ll
1+\mathtt{0x53}+c_{\mathrm{in}}.$ (50)

The carry in expression for RNe, RNa, and RNz becomes

$c_{\mathrm{in}}=x_{3}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2}+\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{3}x_{1}x_{2}+x_{0},$ (51)

and, again, notice that the error depends on the least significant bit of the
exponent, $x_{3}$.

For RN and RZ the expression becomes

$c_{\mathrm{in}}=x_{3}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{1}\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{2}+\mkern 1.0mu\overline{\mkern-1.0mux\mkern-1.0mu}\mkern
1.0mu_{3}x_{0}x_{1}x_{2}.$ (52)

###  3.3 Summary of Obtained Expressions

Tables II and III summarizes the obtained expressions for E5M2 and E4M3
respectively. Where the carry in expressions are too long to fit inside the
table the equation is instead referenced. For rounding modes where correcting
the error with just the carry in was not possible a dash is written. Note that
in some cases all possible rounding modes was possible to obtain, but the same
constant can not be used.

TABLE II: Summary of Suggested Expressions for E5M2.

|  | Boolean expressions for carry in, $c_{\mathit{in}}$a
---|---|---
Operation | Integer arithmetic expression | RNe | RNa | RNz | RU | RD | RZ | Faithful
$x\times y$ | $X+Y+\mathtt{0xc4}+c_{\mathit{in}}$ | (7) | (8) | $0$ | (9) | (10) | $0$ | $0$
$x^{2}$ | $X\ll 1+\mathtt{0xc4}+c_{\mathit{in}}$ | $0$ | (12) | $0$ | (13) | $0$ | $0$ | $0$
$x/y$ | $X-Y+\mathtt{0x3b}+c_{\mathit{in}}$ | (16) | (16) | (16) | (18) | (19) | (17) | $0$
$1/x$ | $-X+\mathtt{0x87}+c_{\mathit{in}}$ | (22) | (22) | (22) | (24) | (25) | (23) |  $1$b
$\sqrt{x}$ | $X\gg 1+\mathtt{0x1e}+c_{\mathit{in}}$ | $0$ | $0$ | $0$ | (27) | — | — | $0$
$1/\sqrt{x}$ | $-X\gg 1+\mathtt{0x5a}+c_{\mathit{in}}$ | $0$ | $0$ | $0$ | (27) | — | — | $0$

  * a

Where — indicates that the rounding mode cannot be obtained using the integer
expressions

  * b

Instead of having an unconditional $1$ on the carry in, the constant can be
increased

TABLE III: Summary of Suggested Expressions for E4M3.

|  | Boolean expressions for carry in, $c_{\mathit{in}}$a
---|---|---
Operation | Integer arithmetic expression | RNe | RNa | RNz | RU | RD | RZ | Faithful
$x\times y$ | $X+Y+\mathtt{0xc8}+c_{\mathit{in}}$ | (30) | (31) | (32) | — | — | (33) | (34)
$x^{2}$ | $X\ll 1+\mathtt{0xc8}+c_{\mathit{in}}$ | (36) | (37) | (36) | — | (38) | (38) | (39)
$x/y$ | $X-Y+\mathtt{0x37}+c_{\mathit{in}}$ | (41) | (41) | (41) | — | — | — | (42)
$1/x$ | $-X+\mathtt{0x6f}+c_{\mathit{in}}$ | (44) | (44) | (44) | — | — | — | (45)
$\sqrt{x}$ | $X\gg 1+\mathtt{0x1b}+c_{\mathit{in}}$ | (47) | (47) | (47) | — | (48) | (48) | $0$
$1/\sqrt{x}$ | $-X\gg 1+\mathtt{0x53}+c_{\mathit{in}}$ | (51) | (51) | (51) | — | (52) | (52) | 1b

  * a

Where — indicates that the rounding mode cannot be obtained using the integer
expressions

  * b

Instead of having an unconditional $1$ on the carry in, the constant can be
increased

##  4 Hardware Implementation of Multiplication

To demonstrate the potential savings of these schemes, a minimal example for
floating-point multiplication is implemented and synthesized for both ASIC and
FPGA. Two different rounding are considered, the first one being RNe as it
most commonly used, and the second one being RZ since it can be considered one
of the cheapest rounding modes.

Note, as multiplication is the simplest circuits of the considered operations
to implement for floating-point, next to square, greater improvements can
likely be obtained for the other operations.

As a reference, a multiplier based on the one presented in[11] is used, but
with the difference that the calculation of ${E_{x}+E_{y}-b}$ and
${E_{x}+E_{y}-b+1}$ is not done in parallel in order to save area. Also, the
reference multiplier only supports normalized operands and no handling of NaN
or inf to have a fair comparison.

There is also a combined reference multiplier, which can be seen as a E5M3
multiplier, but with configurable rounding and bias. However, as the results
are worse for this than by simply multiplex the outputs of the two dedicated
variants, there is also a version which does exactly that. Additional efforts
will be spent on trying to optimized the combined multiplier for the final
version.

For the final version, energy figures based on switching-activity simulations
will be provided for the standard cell implementations.

###  4.1 ASIC Results

The synthesis was made using Synopsys Design Compiler with a $28$ nm FD-SOI
standard cell library at $1.0$ V power supply voltage. A slow-slow process
corner at an ambient temperature of $125~{}^{\circ}$C was considered to keep
the results on the pessimistic side. Registers are added on the input and
output to obtain a more correct critical path, but the registers are not
included in the results.

Figures 7, 8, and 9 show the area consumption of the designs with respect to
clock frequency. For E5M2, the proposed designs are slightly larger compared
to the reference111However, using other commercial synthesis tools,
improvements are present for the proposed over the reference.. Clear
improvements are seen for E4M3, both in terms of area and maximum speed.
Notably, the reference circuit using RNe reached $3.75$ GHz with an area of
$160$ µm2, while the proposed designed reached $5.75$ GHz using only and area
of $85$ µm2.

Figure 7: Area consumption for E5M2 multipliers. Figure 8: Area consumption
for E4M3 multipliers. Figure 9: Area consumption for combined E4M3/E5M2
multipliers.

Finally, for the combined multiplier, significant savings are again present
for the proposed approach. Somewhat surprisingly, it is more efficient to
simply multiplex the outputs of two dedicated multipliers rather than using an
approach with a E5M3 multiplier. As mentioned earlier, these results will be
further investigated to find a more efficient implementation for the final
version.

###  4.2 FPGA Results

The design was synthesized for an AMD Artix-$7$, xc7a12tcpg238-3. Registers
are again to the input and out, hence $24$ flip-flops were used in all designs
($25$ for the combined as there is an additional register for the control
signal). The synthesis results can be found in Table IV.

TABLE IV: FPGA Synthesis Results for Multipliers. Format | Implementation | Delay, ns | LUTs
---|---|---|---
E5M2 | Prop. RNe | $1.775$ | $8$
Prop. RZ | $1.607$ | $8$
Ref. RNe | $2.581$ | $10$
Ref. RZ | $2.342$ | $10$
E4M3 | Prop. RNe | $2.575$ | $8$
Prop. RZ | $2.297$ | $8$
Ref. RNe | $4.318$ | $18$
Ref. RZ | $3.458$ | $17$
Combined | Prop. RNe | $3.155$ | $9$
Prop. RZ | $2.308$ | $9$
Ref. RNe | $5.024$ | $44$
Ref. RZ | $4.143$ | $36$
| Mux. RNe | $4.300$ | $30$
| Mux. RZ | $4.153$ | $27$

For the E5M2 case, fewer LUTs are used and the critical path is reduced. The
proposed design of the E4M3 multiplier is again significantly better than its
reference counterpart. For both rounding modes, the LUT count is more than
halved. The delay is decreased by about $40\%$ for RNe and about $33\%$ for
RZ.

Hence, the rather long expressions in (30) and (33) can be mapped to the same
6-input LUT required for the addition of the least significant bits. As many
FPGAs support ternary addition of three general numbers using a single LUT per
bit [17, 18], it is not surprising that they also support addition of two
general numbers and a constant. Hence, one may expect that all other
computations also will fit within eight 6-input LUTs.

For the combined multiplier, again, significant savings are obtained using the
proposed approach. The carry-in generation now cannot fit within a 6-input LUT
as the mode select signal is also required. On the other hand, the complexity
of reference multiplier increases significantly. For FPGA, it is clearly more
efficient to simply multiplex the outputs of the two reference multipliers.

##  5 Conclusions

In this work, eight-bit floating-point operations using simple integer
operations is discussed. It is shown that correct rounding can be obtained in
most cases for the considered operations when using a two-bit mantissa format,
and faithful rounding can always be obtained. Faithful rounding can sometimes
be obtained directly when using a three-bit mantissa format. However, by using
a conditional carry in, correct rounding, and several other rounding modes,
can be obtained for all considered operations and formats. Boolean expressions
for the carry in are presented for all cases where it can be used. Results for
hardware implementation of multipliers are presented, synthesized to both
standard cells and FPGA. For E5M2 on FPGA and for E4M3 on both platforms,
significant complexity savings are obtained. In addition, combined multipliers
supporting both formats are implemented and, again, significant savings are
obtained using the proposed approach.

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