Further author information: (Peter Orel)
P.O.: E-mail<EMAIL_ADDRESS>Telephone: +1 737 230 2800

# X-ray speed reading with the MCRC: prototype success and next generation
upgrades

Peter Orel  Kavli Institute for Particle Astrophysics and Cosmology, Stanford
University, 452 Lomita Mall, Stanford, CA 94305, USA  Abigail Y. Pan  Kavli
Institute for Particle Astrophysics and Cosmology, Stanford University, 452
Lomita Mall, Stanford, CA 94305, USA  Department of Physics, Stanford
University, 382 Via Pueblo Mall, Stanford, CA 94305, USA  Sven Herrmann  Kavli
Institute for Particle Astrophysics and Cosmology, Stanford University, 452
Lomita Mall, Stanford, CA 94305, USA  Tanmoy Chattopadhyay  Kavli Institute
for Particle Astrophysics and Cosmology, Stanford University, 452 Lomita Mall,
Stanford, CA 94305, USA  Glenn Morris  Kavli Institute for Particle
Astrophysics and Cosmology, Stanford University, 452 Lomita Mall, Stanford, CA
94305, USA  Haley Stueber  Kavli Institute for Particle Astrophysics and
Cosmology, Stanford University, 452 Lomita Mall, Stanford, CA 94305, USA
Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, CA
94305, USA  Steven W. Allen  Kavli Institute for Particle Astrophysics and
Cosmology, Stanford University, 452 Lomita Mall, Stanford, CA 94305, USA
Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, CA
94305, USA  SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo
Park, CA 94025, USA  Daniel Wilkins  Kavli Institute for Particle Astrophysics
and Cosmology, Stanford University, 452 Lomita Mall, Stanford, CA 94305, USA
Gregory Prigozhin  MIT Kavli Institute for Astrophysics and Space Research
Beverly LaMarr  MIT Kavli Institute for Astrophysics and Space Research
Richard Foster  MIT Kavli Institute for Astrophysics and Space Research
Andrew Malonis  MIT Kavli Institute for Astrophysics and Space Research
Marshall W. Bautz  MIT Kavli Institute for Astrophysics and Space Research
Michael J. Cooper  MIT Lincoln Laboratory  Kevan Donlon  MIT Lincoln
Laboratory

###### Abstract

The Advanced X-ray Imaging Satellite (AXIS) is a NASA probe class mission
concept designed to deliver arcsecond resolution with an effective area ten
times that of Chandra (at launch). The AXIS focal plane features an MIT
Lincoln Laboratory (MIT-LL) X-ray charge-coupled device (CCD) detector working
in conjunction with an application specific integrated circuit (ASIC), denoted
the Multi-Channel Readout Chip (MCRC). While this readout ASIC targets the
AXIS mission, it is applicable to a range of potential X-ray missions with
comparable readout requirements. Designed by the X-ray astronomy and
Observational Cosmology (XOC) group at Stanford University, the MCRC ASIC
prototype (MCRC-V1.0) uses a 350 nm technology node and provides 8 channels of
high speed, low noise, low power consumption readout electronics. Each channel
implements a current source to bias the detector output driver, a preamplifier
to provide gain, and an output buffer to interface directly to an analog-to-
digital (ADC) converter. The MCRC-V1 ASIC exhibits comparable performance to
our best discrete electronics implementations, but with ten times less power
consumption and a fraction of the footprint area. In a total ionizing dose
(TID) test, the chip demonstrated a radiation hardness equal or greater to 25
krad, confirming the suitability of the process technology and layout
techniques used in its design. The next iteration of the ASIC (MCRC-V2) will
expand the channel count and extend the interfaces to external circuits,
advancing its readiness as a readout-on-a-chip solution for next generation
X-ray CCD-like detectors. This paper summarizes our most recent
characterization efforts, including the TID radiation campaign and results
from the first operation of the MCRC ASIC in combination with a representative
MIT-LL CCD.

###### keywords:

MCRC, CCD, AXIS, ASIC, TID, readout-on-a-chip, low noise, high speed

##  1 Introduction

Charged-coupled device (CCD) X-ray imaging detectors transformed the field of
X-ray astronomy, offering simultaneous imaging and moderate spectroscopic
capabilities over the $\sim$ 0.3 - 10 keV energy range. These detectors served
to unlock a vast array of scientific discoveries, from precise measurements of
the thermodynamic properties of the hot, X-ray emitting plasma in groups and
clusters of galaxies to detailed measurements of matter in its final moments
before plunging into supermassive black holes. To enable future, strategic
X-ray missions, the 2020 Physics of the Cosmos Program Annual Technology
Report (PATR) identified “fast, low-noise, megapixel X-ray imaging arrays” as
a top-priority technology development need for future strategic astrophysics
missions. One such X-ray mission is the proposed Advanced X-ray Imaging
Satellite (AXIS). AXIS, a response to NASA’s Astrophysics Probe Explorer
(APEX) Announcement of Opportunity, will be a critical part of the 2030s
astrophysics landscape. With 1-2 arcsecond quality imaging across a 24
arcminute diameter field-of-view and a sensitivity greater then 10$\times$
that of the Chandra X-ray observatory at launch (Chandra’s soft X-ray
sensitivity has decreased notably over time), AXIS offers X-ray capabilities
that are well-matched in depth to the James Web space telescope and other
near-term and future ground- and space-based facilities that will dominate the
next 15 years of astronomical research [1].

The high-speed AXIS X-ray camera incorporates a focal plane array with CCDs
designed and fabricated by MIT Lincoln Laboratory (MIT/LL). The CCDs have
multiple outputs to increase the data rate from the 1440 $\times$ 1440 pixel
imaging area, and are coupled with an application-specific integrated circuit
(ASIC) specifically designed for compact, low-power consumption, high-speed,
and low-noise readout. Conceived by the XOC group at Stanford University, the
ASIC is called the Multi-Channel Readout Chip (MCRC). Figure 1 shows the AXIS
focal plane array, which consists of four fast-readout frame-store CCDs
arranged in a 2$\times$2 pattern, each with a dedicated MCRC readout chip co-
mounted on the interposer. In addition, an aluminum cover shields the frame
store regions from the focused celestial X-rays during readout, and provides
the ASICs with additional particle damage protection. The entire array is
maintained at 183 K using a cold finger connection and active trim heaters.
AXIS will be placed in a low-inclination ($<$ 8 ), low-Earth orbit (LEO). The
primary drivers for this choice are the need to maintain rapid, on-demand (low
data-rate) communications for time-domain science, and to obtain a low
radiation environment, providing a low detector background and slowing
detector degradation [2].

Notwithstanding shielding and LEO orbit placement, the readout electronics
still needs to be radiation tolerant. As such, the MCRC prototype (MCRC-V1)
has been exposed to gamma radiation and its total ionizing dose (TID) response
has been measured and is reported in section 3. Further test results for the
MCRC-V1 prototype in both a stand alone configuration and paired with
prototype AXIS CCD detectors are presented in section 4, demonstrating the
technology readiness. Future improvements and updates that will be
incorporated in the second generation of the MCRC chip are discussed in
section 5.

---
Figure 1: Concept of the AXIS X-ray imager focal plane array. The focal plane
is composed of four sub-modules, each consisting of a frame-transfer CCD with
1440 x 1440 pixels of 24 m size, resulting in a X-ray imager with a total of 8
Mega-pixels. The field of view is $27\times 27$ arcmin2, with each pixel
corresponds spanning $0.5\times 0.5$ arcsec2 on the sky. The nominal operation
temperature is 183 K (-90 C).

##  2 Architecture and design

The MCRC-V1 features 8 analog channels. Each channel has two inputs: a source
follower voltage input (SF) and an experimental drain current (DR) input.
Figure 2(a) shows a simplified schematic of a single analog channel. Both
inputs have adjustable current sources to set the operating point (OP) of the
corresponding detector, and are AC coupled to internal programmable switches,
making it easy to shift between the two input circuits. Only one readout mode
can be selected at a given time for the entire chip. The readout mode switches
are followed by a fully differential preamplifier (PRE), which performs
single-ended-to-differential conversion and provides gain. There are two user-
selectable gain settings of 8 V/V (G8) and 16 V/V (G16), respectively. The
output of the PRE is buffered to the chip output pins by a unity gain fully
differential output buffer (OB) that can drive a 100 impedance line with an
almost rail-to-rail output swing, making it simple to interface to a
commercial analog-to-digital (ADC) converter [3, 4].

(a)

(b)

Figure 2: The MCRC-V1 single analog channel schematic (a) [4], and (b) a
photograph of the fabricated MCRC-V1 die with labels showing sub-circuit
locations. Each of the analog channels starts with an input stage, which
allows the user to select between the voltage and the current inputs,
respectively. This input stage is followed by a preamplifier and a fully
differential buffer driver. Eight channels plus a digital control section
constitute the full chip.

Apart from the analog core, the MCRC-V1 also features the following:

  * •

A digital core with eight 16-bit data registers that form the chip’s volatile
memory. The registers can be programmed and/or read back through a serial
peripheral interface (SPI) bus. The SPI interface is fully duplex and makes
use of low-voltage differential signaling (LVDS) transceivers.

  * •

Four programmable 7-bit digital-to-analog (DAC)s to independently set each of
the operating points of the active cascode (ACAS), current-to-coltage (I2V),
PRE, and OB. All nodes are externally accessible to provide the option of
precise calibration, monitoring or bypassing, if necessary.

  * •

Test circuitry to access and monitor the most important nodes in the ASIC.
This is used for debugging and characterization purposes, and is not intended
to be used during normal operation.

Figure 2(b) shows a photograph of the fabricated MCRC-V1 die with dimensions
of 4160 by 2900 . The chip has been designed and manufactured in the X-FAB
ultra-low-noise CMOS XH035 3.3 V 350 m process technology with isolated
p-wells [5]. This makes it possible to keep the chip substrate isolated from
the bulk of the n-type transistors, i.e. switching currents are not flowing
through the substrate, preventing transistor transient disturbances from
coupling to sensitive nodes of the ASIC and corrupting the signal of interest.
Furthermore, all analog circuitry is surrounded by deep p-well guard rings
that ensure good isolation and keep the bulk substrate potential stable to
avoid return current ground loops. The input and output signal carrying wires
are surrounded by metal connected to the substrate potential to prevent
electromagnetic fields, created by the rapidly switching signals, from
coupling between neighbouring channels. To avoid further noise contamination
from the digital circuitry, the analog and digital voltage rails are kept
separate [3].

##  3 Radiation tolerance

Radiation testing has been conducted at Brookhaven National Laboratory (BNL).
Our measurement setup consisted of a Cobalt-60 source, an ASIC test
motherboard, four printed circuit boards (PCB)s with MCRC-V1 ASICs installed,
a power supply, and several blocks of lead for shielding.

The Cobalt-60 source emits gamma photons at energies of 1.19 MeV and 1.31 MeV,
respectively. Dosimetry performed by facility staff at a distance of 4.25
inches from the source, estimated a dose rate of 9114 rad/h for the day of
July 24th, 2023. To leverage the same dose, the ASIC has been carefully
positioned in the same spot. Figures 3(a) and 3(b) show the setup and the
alignment of the chip to the source. Lead blocks were placed around the ASIC
to shield the motherboard electronics. For safety purposes, the Cobalt-60
source is stored underground when people are working inside the hatch. The
setup was operated by a computer sitting outside the hatch. The two were
connected by a 50 feet long Ethernet cable. After the setup passed the safety
and operational check-list, the hatch was sealed with an interlock system.
Upon interlock system activation, the source was raised and the tests were
executed sequentially for each of the four ASIC boards. Each MCRC-V1 chip was
randomly selected from the original lot and directly wirebonded to its board.
The exposure periods for each board were approximately 5.5 hours long,
corresponding to a total ionizing dose of roughly 50 krad. The chips were
powered on and fully configured for the duration of the tests.

(a)

(b)

Figure 3: The MCRC radiation test setup inside the hatch. (a) Side view
without the lead shielding blocks that shows the alignment of the ASIC to the
source position. (b) View from behind the setup with lead shielding blocks in
place.

To identify, characterize, and time stamp a failure mechanism, certain ASIC
parameters were contentiously monitored and logged on the motherboard.
Specifically, these included the supply currents from all voltage rails (VDDA,
VDDB and VDDD), the operating points (bias voltages) of all four main analog
signal chain sub-circuits (the active cascode, the I2V amplifier, the
preamplifier, and the output buffer). In addition, some internal registers of
the MCRC-V1 were monitored for bit errors by continuously writing and reading
back random digital data. We note that during the testing of the first chip,
one of the two diagnostic ADCs that were part of the test motherboard failed
after approximately 2.5 hours of exposure time. It was later determined that
this failure occurred due to the position of that component being close to the
ASIC under test, where the shielding was insufficient. Subsequently, three out
of four biases were rewired to a set of unused auxiliary inputs on the second
ADC.

All four chips survived the radiation exposure. No bit errors were detected on
the digital interface. Figures 4 and 5 show the supply currents and analog
circuitry biases as functions of time and TID for all four chips. The chip
circuitry remained unaffected until a TID dose of approximately 25 krad had
been reached. Following higher doses, a shift in the bias voltages and supply
currents was observed.

To further quantify the impact of the radiation doses on performance,
measurements of the MCRC-V1 analog chain were performed before and after
radiation exposure for all chips under test. Figure 6(a) shows the output
pulse amplitude as a function of input pulse amplitude. Board 2 indicates a
lowered saturation threshold between the non-irradiated and irradiated pulse
response, although the difference is very small. Figure 6(b) shows the
measured gain for all four irradiated boards along with two non-irradiated
chips. The gain is very uniform with minimal differences between the
irradiated and non-irradiated boards. That is, the observed differences
between irradiated and non-irradiated devices falls within the channel-to-
channel variation that is inherent to the manufacturing process. We conclude
that no noticeable performance degradation between irradiated and non-
irradiated chips was observed for TID doses of up to 50 krad.

---
Figure 4: Currents of the MCRC-V1 supply voltage rails as functions of time
and TID for the four MCRC v1 chips tested. The current consumption stays
almost constant up to radiation doses of $\sim$ 25krad.
---
Figure 5: MCRC-V1 analog circuitry bias voltages as functions of time and TID
for the four chips tested. The bias voltages are a proxy for threshold voltage
shifts of the bias transistors. No significant change is measured for
radiation doses up to $\sim$ 25 krad, after which voltages deviate by up to
$\sim$ 50 mV for 45 krad.

(a)

(b)

Figure 6: Performance tests before and after irradiation. (a) Output pulse
amplitude as a function of input pulse amplitude, showing the linearity of the
MCRC V1 ASIC response. (b) Comparison of gain variation between irradiated and
non-irradiated chips.

##  4 Operational experience and test results

The baseline performance of the standalone MCRC-V1 readout ASIC has been
measured and reported in 3. A summary of the results is given in Table 1.

Table 1: Summary of the MCRC-V1 performance parameters. Parameter |  Measured Value
---|---
Gain |  $<$G16$>$ = 12.14 $\pm$ 0.35 V/V
|  $<$G8$>$ = 6.17 $\pm$ 0.59 V/V
Input dynamic range |  SF input: $\approx$ 320 V_PP
|  DR input: $\approx$ 35 A_PP ($\approx$ 500 A_PP with DRCS offset)
Input referred noise |  $<$N_RMS$>$ = 56.94 $\pm$ 13.47 V_RMS
|  $<$N_RMS$>$ = 1.63 $\pm$ 0.38 e^-_RMS @ k = 35 V/e^-
|  $<$N_VSD$>$ = 6.18 $\pm$ 1.46 V/Hz
Crosstalk |  $\leq$ -75 dB in passband
|  I_OB_BIAS = 75 A |  I_OB_BIAS = 150 A
Bandwidth | G16: 42.75 $\pm$ 5.91 | G16: 86.05
| G8: 54.95 $\pm$ 7.30 | G8: 116.38
Power consumption | 30.8 mW/ch | 39.6 mW/ch
|  Digital core: 37.2 mW

To develop the user case of the MCRC as a high-speed, low-noise, and low-power
readout-on-a-chip system, the ASIC prototype has been simultaneously deployed
as a replacement for discrete electronics at both Stanford and MIT. In the
Stanford case, it has been paired with single channel CCID93 detectors, which
feature one p-jfet output similar in construction to the outputs on the CCID85
detector [6]. The primary purpose was to make direct performance-wise
comparisons of the ASIC to its discrete electronics counterparts and to
optimize its operating points. The MIT tests had the MCRC-V1 paired with an 8
channel CCID89 detector to evaluate and gain confidence in its multichannel
operation.

###  4.1 Single channel operation and optimization

The characterization and optimization tests were carried out in the newly
developed and commissioned 2.5 meter-long X-ray beamline test system [7]. An
STA Archon CCD controller was used, which features 8 ADC channels and a
variety of voltage biasing options and clock lines to control and drive the
CCD [8]. Figure 7(a) shows the electronics part of the test setup. The CCID93
detector is mounted on the detector board by means of a zero insertion force
(ZIF) socket connector. Similarly, to achieve maximum modularity, the MCRC-V1
has been wirebonded to a daughter PCB board which is mounted on the detector
board without soldering. The connection is achieved using a Samtec high-
density 1.27 mm thick interposer [9], that provides the lowest parasitic
capacitance possible on a modular interface. The detector board acts solely as
an interconnect layer between the detector, MCRC-V1, and the ADCs in the
Archon controller. To that end, a rigid-flex PCB board is used to connect the
detector board from inside the vacuum to the STA Archon controller outside, as
shown in Figure 7(b). Figure 7(c) shows a picture of the entire beamline from
the X-ray source on the left to the chamber door on the right.

(a)

(b)

(c)

Figure 7: The test setup with electronic units connected to form the readout
system. (a) A custom flex lead connects the detector board inside (b) the
chamber to the outside. The beamline (c) is designed to efficiently produce
monoenergetic X-ray fluorescence lines in the 0.3 - 10 keV energy range, while
maintaining detector temperatures as low as 173 K [7].

System performance parameters such as gain, read noise, and full-width-at-
half-maximum (FWHM) energy resolution were determined at X-ray line energies
of 1.5 keV, 5.9 keV, 8.04 keV and 8.9 keV, using Aluminium (Al), Iron-55
(55Fe) and Copper (Cu) sources. In addition, a Teflon source was used to
calculate the maximum observed continuum energy (MOCE) as reported in row 7 of
Table 2. The low gain setting (G8) of the MCRC-V1 has been measured to be
approximately 6 V/V, while the high gain setting (G16) is 12 V/V, which
matches the standalone measurements summarized in Table 1. These gains are
lower than the nominal design values of 8 V/V and 16 V/V, respectively, with
the differences traced to a voltage divider effect caused by the output series
resistance of the MCRC-V1 output buffer and the 100 parallel termination.

Table 2: Test results from system response optimization. MCRC-V1 gain setting |  low |  low |  low |  high |  high |  high
---|---|---|---|---|---|---
Clamping voltage [V] |  +0 |  +0.7 |  +2 |  +0 |  +0.7 |  +2
Spectral peak
@1.5 keV [mV] |  84.3 |  84.4 |  84.4 |  166.5 |  166.9 |  167.0
Spectral peak
@5.9 keV [mV] |  335.6 |  335.6 |  335.8 |  658.2 |  659.1 |  658.7
Spectral peak
@8.04 keV [mV] |  457.8 |  458.1 |  457.9 |  869.7 |  869.1 |  868.9
System gain [V/e^-] | 207.0 $\pm$ 1.39 | 402.7 $\pm$ 6.65
MOCE [keV] |  9.58 |  9.64 |  9.57 |  9.54 |  9.75 |  9.61
Dynamic range [keV] |  27.9 |  38.8 |  59.1 |  11.1 |  18.1 |  27.0
Noise [$e^{-}$] |  3.67 (55Fe) 3.46 (Cu) 3.37 (Al) |  3.47 (55Fe) 3.49 (Cu) 3.40 (Al) |  3.46 (55Fe) 3.50 (Cu) 3.38 (Al) |  3.68 (55Fe) 3.76 (Cu) 3.24 (Al) |  3.21 (55Fe) 3.35 (Cu) 3.19 (Al) |  3.21 (55Fe) 3.48 (Cu) 3.14 (Al)
FWHM @1.5 keV [eV] |  75.72 |  75.05 |  74.16 |  74.58 |  73.46 |  74.06
FWHM @5.9 keV [eV] |  122.81 |  121.27 |  123.27 |  125.90 |  111.49 |  117.48
FWHM @8.04 keV [eV] |  151.89 |  145.45 |  146.74 |  160.26 |  144.64 |  146.05

####  4.1.1 System response optimization

As expected, the high gain setting approximately doubles the system gain,
while adjusting the clamping voltage of the ADC input does not have a
significant effect. The systematic uncertainty on the system gain is (very)
small, confirming a (very) linear response over the energy range studied. At
high gain, the higher signal to noise ratio (SNR) delivers an overall lower
readout noise. The dynamic range of the system is limited by the range of the
16-bit Archon ADCs. That is, the full scale input voltage range is constrained
at the upper limit of 4 _PP while the lower limit is set by the distance
between the bottom of the ADC range and the input signal baseline. The system
dynamic range can be increased by decreasing the gain or increasing the
clamping voltage, which shifts the baseline from the center towards one of the
rails, depending on the input signal polarity. We note that during actual
operations, the MCRC-V1 may have been saturated before the maximum range was
reached for the larger range spans. The high gain setting with a clamping
voltage of +0 V provides an energy spectrum range of up to 13 keV. The power
draw of the system was unaffected by the gain or clamping voltage settings
studied.

Operating point optimisation was carried out to determine the best ASIC
performance values in terms of gain, noise, speed, and current draw. The
MCRC-V1 analog circuitry has three adjustable parameters that can affect not
only the ASIC but also the detector output response. More precisely, the ASIC
has an input current source (SFCS), for which the source voltage
(V_SFCS_SOURCE) can be externally adjusted to set the proper operating point
of the detector output. The other two adjustable parameters are: the
preamplifier bias current (I_PRE_BIAS) and the output buffer bias current
(I_OB_BIAS). Unlike the V_SFCS_SOURCE, these two can be set by internal DACs.
To optimize the overall system response, all three parameters were varied and
the corresponding performance analyzed. Gain and noise performances were
determined by taking 200 illuminated frames followed by 50 dark frames. Speed
was evaluated by comparing the raw transient waveform settling behaviour at
each bias point. For the transient figure, in general, a smaller reset peak
indicates that the system is slew-limited (large signal response), while a
shallower transition between the baseline and signal means the system is
bandwidth-limited (small signal response).

Figure 8(a) shows the gain and noise of the system as functions of the SFCS
source voltage applied to the MCRC-V1 pin named NCUR_V. Gain performance
improves as the V_SFCS_SOURCE increases, while the optimal noise performance
is achieved for V_SFCS_SOURCE voltages between -3 V and -2 V. Figure 8(b)
shows a set of transient waveforms for various V_SFCS_SOURCE voltages. A clear
effect on both the slew rate and bandwidth is observed, where a maximum
V_SFCS_SOURCE voltage of -2 V is needed to maintain a fast enough response.
The obtained optimal V_SFCS_SOURCE value is -2.8 V.

(a)

(b)

Figure 8: (a) Gain and noise as functions of SFCS source voltage (NCUR_V pin).
(b) Transient waveform for V_SFCS_SOURCE voltages ranging from -1 V to -4 V.
The MCRC-V1 operating point was: gain = 12 V/V, I_PRE_BIAS = 75 A, I_OB_BIAS =
50 A.

Figure 9(a) shows gain and noise as functions of the preamplifier bias
current. Overall, I_PRE_BIAS does not appear to have a significant affect on
the performance. However, the gain exhibits a worsening trend with increasing
bias current, while the noise seems to be improving. Figure 9(b) shows input
signal transient waveforms for different preamplifier bias current settings. A
minimum bias current of 35 is required to maintain the nominal slew rate of
the system.

(a)

(b)

Figure 9: (a) Gain and noise as functions of the preamplifier bias current.
(b) Transient waveform for I_PRE_BIAS ranging from 15 A V to 105 A. The
MCRC-V1 operating point was: gain = 12 V/V, V_SFCS_SOURCE = -2.8 V, I_OB_BIAS
= 50 A.

Figure 10(a) shows the gain and noise as functions of the output buffer bias
current. Both the gain and the noise do not appear to be affected by the
change in I_OB_BIAS. However, it does affect the slew rate of the buffer, as
can be seen in Figure 10(b). A minimum of 50 A is necessary to properly buffer
the analog signal. In addition, an increasing I_OB_BIAS affects the power draw
of the ASIC. Both the buffer rail (VDDB/VSSB) and analog circuitry rail
(VDDA/VSSA) power consumption increases linearly with increasing output buffer
bias current, as shown in Figure 11.

(a)

(b)

Figure 10: (a) Gain and noise as functions of the output buffer bias current.
(b) Transient waveforms for I_OB_BIAS ranging from 20 A V to 100 A. The
MCRC-V1 operating point was: gain = 12 V/V, V_SFCS_SOURCE = -2.8 V, I_PRE_BIAS
= 75 A.
---
Figure 11: MCRC-V1 power consumption for the analog (VDDA/VSSA) rail, output
buffer (VDDB/VSSB), and the total ASIC power consumption. Digital power
consumption is not displayed, remaining stable at $\sim$ 34 mW.

The MCRC-V1 preamplifier has a switched capacitor based feedback that needs to
be periodically reset to baseline to avoid saturation. The reset can be
applied at the end of each CCD line or at the end of every pixel window. Both
cases show a comparable performance in terms of gain and noise. Similarly,
sweeping the reset pulse width does not appear to have a significant effect.
On the other hand, a minimum reset pulse width of 40 ns is necessary to
provide an adequate transient response. The best performance, without
sacrificing readout time, is achieved with a reset pulse width of 70 ns. We
note that the ability to reset the readout ASIC at the pixel-by-pixel level
might become necessary for large CCD detectors.

Table 2 summarizes the results for gain, noise, dynamic range, MOCE, and FWHM.

####  4.1.2 Saturation recovery

To ensure that minimal dead time occurs, the MCRC-V1 amplification chain
requires prompt recovery from saturation events. On the detector side, the
reset clock (RG) pulse drains the charge packet away from the output stage of
the CCD after reading out each pixel. In normal operation, the RG pulse is too
narrow (10 ns) for the system to saturate. However, increasing the RG reset
pulse width and measuring the amplitude of the RG pulse directly has been
found to saturate the MCRC-V1. More accurately, saturation becomes apparent
for an RG pulse amplitude of $\sim$ 1.27 V, when the RG pulse width is greater
than 100 ns. Nevertheless, the MCRC-V1 recovers with only marginal degradation
in gain and noises, providing an overall performance comparable to that under
the normal operation.

####  4.1.3 Overall system noise

The effects of the MCRC-V1 on the overall system noise were also explored.
Configuration wise, chip channel 6 was connected to the CCD p-jfet output,
while five other channels had their inputs floating. The remaining two
channels were disconnected from the Archon ADC, leaving the ADC inputs
floating. To provide continuous time domain data without transient artifacts,
the RG reset signal was kept high, meaning no actual charge packets were read
out. A PSD analysis was then applied to obtain the noise spectral density of
each channel. Table 3 reports the measurement results.

Table 3: Summary of noise measurements with the MCRC-V1 over all channels in various configurations. channel |  configuration |  IRN [nV] |  thermal noise floor [nV/$\sqrt{Hz}$] |  thermal noise [$e^{-}$]
---|---|---|---|---
CH1 |  ASIC+ADC |  937.4 |  5.66 |  0.75
CH2 |  ADC only |  109.12 |  1.52 |  0.20
CH3 |  ASIC+BUFF+ADC |  1104.9 |  5.97 |  0.79
CH4 |  ASIC+BUFF+ADC |  1041.1 |  6.06 |  0.80
CH5 |  ASIC+ADC |  924.1 |  5.61 |  0.74
CH6 |  Detector+ASIC+ADC |  16070.6 |  12.92 |  1.71
CH7 |  ASIC+ADC |  909.6 |  5.66 |  0.75
CH8 |  ADC only |  96.5 |  1.42 |  0.19
CH1 - CH2 |  ASIC only (derived) |  931.1 |  5.45 |  0.72
CH6 - CH1 |  Detector only (derived) |  16043.3 |  11.60 |  1.53

Both the MCRC-V1 and Archon noise performance show a high level of consistency
across all channels. Figure 12 shows the noise spectral density for all system
channels. Channels 4 and 3 have a slightly higher noise spectral density due
to the additional 100 buffers. The ADC and MCRC-V1 noise spectra appear to be
mostly thermal, while a larger flicker (1/f) noise contribution can be seen
coming from the detector. The large bump at approximately 7 MHz originates
from coupling with a non-grounded metal piece of the detector socket close to
the detector output pin; once grounded the bump was amplitude reduced
significantly. The components at higher frequencies are coupled to the system
through the wire leads of the temperature sensors located on the detector
board, as well as on the cold head of the detector mount.

---
Figure 12: Noise spectral density for all 8 channels of the MCRC-V1 in
different configurations.

####  4.1.4 Crosstalk isolation

Channel to channel crosstalk can significantly degrade system performance by
introducing phantom ”signals” in adjacent channels. Using the same channel
configuration as in the noise tests, data were taken operating the detector
and one ASIC channel operating in a normal mode (RG reset pulse nominal),
while simultaneously gathering raw waveforms from the other channels. Dark,
Iron-55 (55Fe) and copper(Cu) frames were taken for each channel. Figures
13(a) and 13(b) show the transient waveforms and the corresponding spectra,
respectively, for channels 5, 6, and 7. Channel 6 has the detector signal,
while channels 5 and 7 are neighbouring channels. Evidence of capacitive
crosstalk can be seen around the RG reset pulse in all of the channels
connected, but the effect is most pronounced in channels 5 and 7. The measured
isolation to the neighbouring channels is approximately 56 dBc, which is a
lower value then the 75 dBc observed during the standalone MCRC-V1
measurements [3]. The exact coupling mechanism is currently unconfirmed.
However, the board and detector layouts are the main suspects. Nevertheless,
this crosstalk is only seen during pixel resets, where the acquired data is
considered invalid. To investigate this further, images of the pixel values
for each channel were examined. When the detector is dark or unconnected, the
spread of the pixel values is Gaussian. Figures 14 a, b, and c show histogram-
ed pixels for channels 5, 6, and 7, respectively. Comparing the dark and 55Fe
source frame pixel values for unconnected channels, we see a negligible change
in spread. The same has been observed for the Cu source. This confirms that
crosstalk does not have a noticeable effect on the actual readout performance
of the MCRC-V1, with 56 dB of channel-to-channel isolation representing an
attenuation factor of $\sim$ 1000 V/V.

(a)

(b)

Figure 13: (a) Transient waveform showing the detector response on channel 6
and the neighbouring channels 5 and 7. (b) Voltage spectrum of channels 5, 6,
and 7.

(a)

(b)

(c)

Figure 14: Pixel values in terms of probability density (dark and 55Fe frames)
as functions of normalized analog digital units (ADU) or counts for the
detector channel (b) and the adjacent unconnected MCRC-V1 channels 5 (a), and
7 (c), respectively.

###  4.2 Comparison with discrete electronics

The detector board used is designed such that both the ASIC and the discrete
preamplifier are available to the same detector output. The MCRC-V1 has been
operated in the previously obtained optimal operating point: gain = 12 V/V,
V_SFCS_SOURCE = -2.8 V, I_PRE_BIAS = 75 A, and I_OB_BIAS = 50 A. Table 4
reports the performance parameters (gain, noise, and FWHM) for each of the two
cases cases.

Table 4: Summary of gain, noise, and FWHM measurements with the MCRC-V1 and the discrete electronics. |  system gain @5.9 keV [V/e^-] |  electronics gain [V/V] |  detector conversion gain [V/e^-] |  FWHM @5.9 keV [eV] |  noise [$e^{-}$] |  power consumption [W] |  area footprint [%]
---|---|---|---|---|---|---|---
MCRC-V1 |  402.6 |  12 |  33.5 |  120.9 |  3.05 |  0.35 |  3.87
Discrete |  340.7 |  10 |  34.1 |  122.1 |  3.12 |  4 |  100

Figures 15(a) and 15(b) show the direct comparison of the MCRC-V1 readout ASIC
and the discrete electronics implementation in terms of noise spectral density
and speed, respectively.

(a)

(b)

Figure 15: Comparison plots of (a) Noise spectral density and (b) transient
response of the MCRC-V1 and the discrete electronics implementation.

Our results confirm that the noise, gain, and speed performance of the MCRC-V1
is comparable to that of the discrete preamplifier. The total MCRC-V1 power
consumption, at the optimal bias conditions, is $\sim$ 350 mW, while a single
channel of the discrete preamplifier has a power consumption closer to 500 mW.
Consequently, eight channels reach a power consumption of 4 W. The MCRC-V1 has
an effective power consumption $\sim$ 11.5 times lower then the discrete
preamplifier. In addition, the ASIC has a smaller footprint area than the
layout of one single discrete preamplifier channel.

###  4.3 Multichannel measurement results

The MCRC-V1 is an 8 channel readout ASIC. However, the tests described at
Stanford employed only single output detectors. To test all 8 channels in
parallel, an MCRC-V1 ASIC was also installed on an MIT-designed PCB board with
an 8 output CCID89 CCD [6]. Figure 16 shows a photograph of the PCB board that
hosts the CCID89 detector along with both the MCRC-V1 and discrete electronics
implementation.

---
Figure 16: PCB board with 8 channel CCDID89 p-jfet output CCD with both the
MCRC-V1 and discrete electronics.

Initial testing of the CCD board was carried out using the discrete component
chains, When that was completed, the ASIC chip was installed and the discrete
chains were disabled. Another round of testing was then performed. All 8
readout channels were found to work well, with performance quality very close
to that demonstrated by with the discrete components, but at a greatly reduced
power consumption.

CCD readout noise values were measured over a wide range of temperatures, both
before and after ASIC installation for 4 CCD channels, as shown on Figure 17.
Noise units were converted into electrons using X-rays emitted by an 55Fe
radioactive source. This conversion takes into account gain changes with
temperature. The difference in noise between ASIC and discrete component
readout is very small, a fraction of an electron.

(a) Discrete components readout

(b) Readout with ASIC

Figure 17: Noise as a function of CCD temperature for 4 different output
nodes.

Crosstalk between the CCD channels was measured by observing the signal levels
in the other channels at the time when an X-ray event was registered in one of
the sectors. The results are shown in the picture on Figure 18 for the same 4
sectors of the CCD, named A, B, G, H.

Figure 18: Signal amplitudes in the island surrounding 55Fe event and
corresponding islands in the other sectors.

Signal amplitudes are reported in islands of 3 x 3 pixels surrounding the
central pixel of an X-ray event. The signal amplitudes corresponding to that
same event in other sectors are shown in the pixel islands over the same
column. Examining the signal values indicates that at the time of the event,
amplitudes in the central pixels of other sectors drop by 1-2 ADUs relative to
an undisturbed value. This constitutes approximately 0.06 % of the signal
causing the disturbance, identifying such crosstalk to be a very small effect.
Overall, the ASIC works very well in the multichannel regime and is ready to
be used in real world applications.

###  4.4 Drain readout performance

The MCRC-V1 drain current input has a high speed p-MOSFET based active cascode
(ACAS) followed by an adjustable current source (DRCS) and a current to
voltage converter (I2V). The ACAS circuit is designed to isolate the very
sensitive I2V negative input while also providing a stable voltage on the
detector drain output. The adjustable current source provides the biasing
current for the p-MOSFET drain and the ability to adjust the input current
offset of the I2V amplifier. That is, when there is no signal present, the I2V
input current is zeroed out to avoid saturation. The I2V is a two-stage
operational amplifier with a transimpedance of 100 . The drain readout input
is an experimental circuit designed to be interfaced with detector output
stages that use current modulation instead of voltage as the means of
transmitting information. The advantage of such an architecture is its low
impedance operation where the impact of parasitic capacitances is
significantly diminished compared to the source follower, high impedance,
based technology. The measured impedance at the ACAS input is $\sim$ 180 . In
theory, drain current based readouts can achieve higher speeds, lower noise,
and better disturbance immunity. One such detector output is the so called
Single electron Sensitive Readout (SiSeRO) [10, 11, 12, 13, 14] output. The
SiSeRO output is composed of a p-type MOSFET transistor, which has two gates:
an external and an internal gate. The external gate is used to set the
operating point while the internal gate is used to modulate the drain-source
current of the p-MOSFET output. The amplitude of the modulation is
proportional to the charge that gets transferred to the internal gate from the
last serial gate of the CCD serial register.

Figure 19 shows the simulated and measured noise spectral densities referred
to the input of the current readout circuit. Both cases show good agreement in
terms of the thermal noise floor with an input referred spectral noise density
of $\sim$ 966 A Hz.

---
Figure 19: Drain current readout input referred noise spectral density.

Figure 20(a) shows a gain scan of the current readout circuit at the output of
the I2V. The small signal response shows good agreement with the simulated
values, where the small signal bandwidth is $\sim$ 23 MHz. At large signals
the response quickly degrades with the bandwidth dropping below 10 MHz. Figure
20(b) shows the I2V output voltage as a function of input current for
different source voltages of the DRCS. Adjusting the source voltage stirs the
I2V response over the DR input current range. The input dynamic range of the
circuit is limited by the input current range of the I2V, which is measured to
be around 30 A.

(a)

(b)

Figure 20: (a) Gain scan of the current readout input circuit for different
signal amplitudes. (b) I2V output voltage as a function of the input DC
current at various current source voltages.

##  5 Conclusion and future upgrades

The MCRC-V1 prototype has been proven to provide a reliable substitute for
discrete electronics implementations at a fraction of the power consumption
and a significant reduction in real state area. The main findings from testing
the MCRC-V1 prototype are summarized below:

  * •

The behavior of the MCRC-V1 is consistent with simulations. That is, the
simulated optimal gain, bias, and reset settings closely match measurement
results.

  * •

The high gain setting of 12 V/V provides a satisfactory dynamic range of
$\sim$12 keV.

  * •

Channel to channel variation in the MCRC-V1 is very low.

  * •

There appears to be no significant effect on performance due to crosstalk (56
dB of channel-to-channel isolation).

  * •

The noise, gain and spectral energy resolution performance of the MCRC-V1 is
comparable to that of our best discrete electronics solutions but for only a
fraction of the power and physical footprint.

  * •

The MCRC-V1 noise contribution is $\sim$18 % of thermal noise to the total
system noise.

  * •

Multichannel operation has been verified.

  * •

Radiation tolerance has been demonstrated for a TID dose of 50 krad.

  * •

Current readout input working with a noise floor of about 1 A Hz and input
impedance of roughly 180 .

  * •

Optimal operating point settings:

    * –

Source follower input current source voltage: -2.8 V.

    * –

Preamplifier bias current: 75 A.

    * –

Output buffer bias current: 45 A.

    * –

MCRC-V1 reset mode: Line end, but pixel-by-pixel also possible.

    * –

NCRC-V1 reset pulse width: 70 ns.

Notwithstanding the overall success of the MCRC-V1 prototype, some bugs were
discovered. These have been thoroughly analysed and understood. For the next
iteration of the chip (MCRC-V2) we plan to apply all of the bug fixes known to
date and also implement some additional features. One of these is an increase
in channel count from 8 to 16 channels, to be optimally compatible with the
upcoming CCID100 CCD detector, which will feature 16 p-jfet based outputs and
will be the representative detector prototype for the AXIS flight hardware.
Other new features include: the ability to enable/disable each output
individually; an internal temperature sensor for better diagnostics; RG
detector clock drivers to further reduce the local footprint area and power
consumption, and alos provide better synchronization between the detector
charge transfer window and readout ASIC reset times.

###### Acknowledgements.

This work has been supported by NASA APRA grants 80NSSC19K0499 and
80NSSC22K1921, SAT grant 80NSSC23K0211. We also thank the Kavli Institute of
Particle Astrophysics and Cosmology for support via a KIPAC decadal funding
grant.

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