IEEEexample:BSTcontrol

#  Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-
Grained DRAM Architecture

Ataberk Olgun§ F. Nisa Bostancı§$\dagger$ Geraldo F. Oliveira§ Yahya Can
Tuğrul§$\dagger$ Rahul Bera§
A. Giray Yağlıkcı§ Hasan Hassan§ Oğuz Ergin$\dagger$ Onur Mutlu§

§ _ETH Zürich_ $\dagger$_TOBB University of Economics and Technology_

###### Abstract

Modern computing systems access data in main memory at _coarse_ _granularity_
(e.g., at 512-bit cache block granularity). Coarse-grained access leads to
wasted energy because the system does _not_ use all individually accessed
small portions (e.g., _words_ , each of which typically is 64 bits) of a cache
block. In modern DRAM-based computing systems, two key coarse-grained access
mechanisms lead to wasted energy: large and fixed-size (i) data transfers
between DRAM and the memory controller and (ii) DRAM row activations.

We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduces
wasted energy by enabling _fine-grained_ DRAM data transfer and DRAM row
activation. To retrieve only useful data from DRAM, Sectored DRAM exploits the
observation that many cache blocks are not fully utilized in many workloads
due to poor spatial locality. Sectored DRAM predicts the words in a cache
block that will likely be accessed during the cache block’s residency in cache
and: (i) transfers only the predicted words on the memory channel by
dynamically tailoring the DRAM data transfer size for the workload and (ii)
activates a smaller set of cells that contain the predicted words by carefully
operating physically isolated portions of DRAM rows (i.e., mats). Activating a
smaller set of cells on each access relaxes DRAM power delivery constraints
and allows the memory controller to schedule DRAM accesses faster.

We evaluate Sectored DRAM using 41 workloads from widely-used benchmark
suites. Compared to a system with coarse-grained DRAM, Sectored DRAM reduces
the DRAM energy consumption of highly-memory-intensive workloads by up to (on
average) 33% (20%) while improving their performance by up to (on average) 36%
(17%). Sectored DRAM’s DRAM energy savings, combined with its system
performance improvement, allows system-wide energy savings of up to 23%.
Sectored DRAM’s DRAM chip area overhead is 1.7% of the area of a modern DDR4
chip. Compared to state-of-the-art fine-grained DRAM architectures, Sectored
DRAM greatly reduces DRAM energy consumption, does _not_ reduce DRAM
bandwidth, and can be implemented with low hardware cost. Sectored DRAM
provides 89% of the performance benefits of, consumes 12% less DRAM energy
than, and takes up 34% less DRAM chip area than a high-performance state-of-
the-art fine-grained DRAM architecture (Half-DRAM). We hope and believe that
Sectored DRAM’s ideas and results will help to enable more efficient and high-
performance memory systems. To this end, we open source Sectored DRAM at
https://github.com/CMU-SAFARI/Sectored-DRAM.

##  1 Introduction

DRAM [22] is hierarchically organized to improve scaling in density and
performance. At the highest level of the hierarchy, a DRAM chip is partitioned
into banks that can be accessed simultaneously [87, 57, 58, 59, 63]. At the
lowest level, a collection of DRAM rows (DRAM cells that are activated
together) are typically divided into multiple _DRAM mats_ that can operate
individually [52, 42, 125, 58]. Even though DRAM chips are hierarchically
organized, standard DRAM interfaces (e.g., DDRx [43, 44, 45]) do _not_ expose
DRAM mats to the memory controller. To access even a single DRAM cell, the
memory controller needs to activate a large number of DRAM cells (e.g., 65,536
DRAM cells in a DRAM row in DDR4 [80]) and transfer many bits (e.g., a cache
block, typically 512 bits [32]) over the memory channel. Thus, in current
systems, both DRAM data transfer and activation are _coarse-grained_. Coarse-
grained data transfer and activation cause significant energy inefficiency in
systems that use DRAM as main memory for two major reasons.

First, coarse-grained DRAM data transfer causes unnecessary data movement.
Standard DRAM interfaces transfer data at cache block granularity over fixed-
size data transfer bursts (e.g., 8-cycle bursts in DDR4 [44, 80]), but a large
fraction of data (e.g., more than 75% [98]) in a cache block is not used
(i.e., referenced by CPU load/store instructions) during the cache block’s
residency in the cache hierarchy (i.e., from the moment the cache block is
brought to the on-chip caches until it gets evicted) [61, 62, 97, 98, 131,
132]. Thus, transferring unused words of a cache block over the power-hungry
memory channel wastes energy [68, 135, 3, 116, 92, 15, 30, 124, 96, 127, 69].

Second, coarse-grained DRAM activation causes an unnecessarily large number of
DRAM cells in a DRAM row to be activated. Subsequent DRAM accesses to the
activated row can be served faster. However, many modern memory-intensive
workloads with irregular access patterns cannot benefit from these faster row
accesses as the spatial locality in these workloads is lower than the DRAM row
size [68, 29, 85, 82, 86, 121, 133, 88, 120]. Thus, the energy cost of
activating all cells in a DRAM row is not amortized over many accesses to the
same row, leading to energy waste from activating a disproportionately large
number of cells.

Prior works [68, 136, 135, 3, 116, 92, 15, 18, 30, 124] develop DRAM
substrates that enable _fine-grained_ DRAM data transfer and activation,
allowing words of a cache block to be individually retrieved from DRAM and a
small number of DRAM cells to be activated with each DRAM access. However,
these prior works (i) cannot provide high DRAM throughput [18, 124], (ii)
incur high DRAM area overheads [136, 30, 135, 3, 116, 92, 15], and (iii) do
_not_ fully enable111This class of prior works either do _not_ enable fine-
grained data transfer (i.e., they perform data transfers at cache block
granularity) [136, 18, 124, 30] or do _not_ enable fine-grained data transfer
for both read and write operations [68]. fine-grained DRAM [18, 124, 136, 30,
68] (section 3.1).

Our goal is to develop a new, low-cost, and high-throughput DRAM substrate
that can mitigate the excessive energy consumption from both (i) transmitting
unused data on the memory channel and (ii) activating a disproportionately
large number of DRAM cells. To this end, we develop _Sectored DRAM_. Sectored
DRAM leverages two key ideas to enable fine-grained data transfer and row
activation at low chip area cost. First, a cache block transfer between main
memory and the memory controller happens in _a fixed number of_ DRAM interface
clock cycles where only a word of the cache line is transferred in each cycle.
Sectored DRAM augments the memory controller and the DRAM chip to perform
cache block transfers in a _variable number of_ clock cycles based on the
workload access pattern. Second, a large DRAM row, by design, is _already_
partitioned into smaller independent physically isolated regions. Sectored
DRAM provides the memory controller with the ability to activate each such
region based on the workload access pattern.

Sectored DRAM implements (i) Variable Burst Length ($VBL$) to enable fine-
grained DRAM data transfer, and Sectored Activation ($SA$) to enable fine-
grained DRAM activation. $VBL$ dynamically adjusts the number of cycles in a
burst to transfer a different word of a cache block with each DRAM interface
cycle, thus enabling fine-granularity DRAM data transfer. To do so at low
cost, $VBL$ builds on existing DRAM I/O circuitry that already selects one
word of a cache block to transfer in one cycle of a burst.

To enable $SA$ with low hardware cost, we leverage the fact that DRAM rows are
already partitioned into independent physically isolated regions (mats) that
can be individually activated with small modifications to the DRAM chip. We
refer to a mat that incorporates these modifications as a _sector_.222We use
the word _sector_ to distinguish between what exists today in DRAM chips
(mats) and what we propose in Sectored DRAM (sectors). Activating a sector
consumes considerably smaller energy than activating a DRAM row as a sector
typically contains almost an order of magnitude fewer cells (e.g., 1024 in a
DDR4 chip) than a DRAM row (e.g., typically 8192 in a DDR4 chip). $SA$ (i)
implements _sector transistors_ that are each turned on to activate one of the
independent mats, and (ii) _sector latches_ that control the sector
transistors. $SA$ exposes the sector latches to the memory controller by using
an existing DRAM command (section 4.1), therefore, $SA$ can be implemented
without any changes to the physical DRAM interface. As the power required to
activate a mat in a DRAM row is only a fraction of the power required to
activate the whole row, Sectored DRAM also relaxes the power delivery
constraints in DRAM chips [68, 136, 92]. Doing so allows for the activation of
DRAM rows at a higher rate, increasing memory-level parallelism for memory-
intensive workloads.

$VBL$ and $SA$ provide two key primitives for power-efficient, sub-cache-
block-sized (e.g., 8-byte or one-word) data transfers between main memory and
the rest of the system. However, because modern systems are typically designed
to have cache-block-sized (e.g., 64-byte) data transfers between system
components, making performance- and energy–efficient use of two Sectored DRAM
primitives ($VBL$ and $SA$) requires system-wide modifications in hardware. We
develop two hardware techniques (section 5.2), (i) Load/Store Queue (LSQ)
Lookahead and (ii) Sector Predictor (SP) to effectively integrate Sectored
DRAM into a system. At a high level, LSQ Lookahead and SP determine and
predict, respectively, which words of a cache block should be retrieved from a
lower-level component of the memory hierarchy. Accurately determining the
words of a cache block that are used during the cache block’s _residency_ in
system caches enables high system performance and low system energy
consumption by improving data reuse in system caches as opposed to repeating a
high-latency main memory access for each used word of a cache block.

LSQ Lookahead accumulates the individual words in a cache block accessed by
younger load/store instructions in older load/store instructions’ memory
requests. Thus, the execution of a load/store instruction prefetches the
portions of cache blocks that will be accessed by the in-flight (i.e., not yet
executed) load/store instructions. SP predicts which portions of a cache block
will be accessed by a load/store instruction based on that instruction’s past
cache block usage patterns. This allows SP to accurately predict the portions
of a cache block that will be used by the processor during the cache block’s
residency in the cache hierarchy.

R3min/2aWe evaluate the performance and energy of Sectored DRAM using 41
workloads from SPEC2006 [118] and 2017 [119] and DAMOV [91, 106] benchmarks
using Ramulator [104, 105, 59, 74], DRAMPower [12], and Rambus Power Model
[99]. Sectored DRAM significantly reduces system energy consumption and
improves system performance for memory-intensive workloads with irregular
access patterns (which amounts to 10 of our workloads). For such workloads,
compared to a system with conventional coarse-grained DRAM, Sectored DRAM
reduces DRAM energy consumption by 20%, improves system performance by 17%,
and reduces system energy consumption by 14%, on average. Sectored DRAM does
so as it 1) improves workload execution time by issuing activate commands at a
higher rate and thereby reducing average memory latency and 2) activates fewer
DRAM cells and retrieves fewer sectors from DRAM at lower power. We estimate
the DRAM area overheads of Sectored DRAM using CACTI [84] and find that it can
be implemented with low hardware cost. Sectored DRAM incurs 0.39 $mm^{2}$ DRAM
area overhead (1.7% of a DRAM chip) and does _not_ require modifications to
the physical DRAM interface. Compared to the evaluated state-of-the-art fine-
grained DRAM architectures [18, 136, 68, 132], Sectored DRAM greatly reduces
DRAM energy consumption, does _not_ reduce DRAM bandwidth, and can be
implemented with low hardware cost. Sectored DRAM provides 89% of the
performance benefits of, consumes 12% DRAM energy than, and takes up 34% less
DRAM chip area than a high-performance state-of-the-art fine-grained DRAM
architecture [136]. Sectored DRAM provides 10% larger performance and 13%
larger DRAM energy benefits compared to a low-cost state-of-the-art fine-
grained DRAM architecture [68]. We open source our simulation infrastructure
and all datasets to enable reproducibility and help future research [107].

We make the following contributions:

  * •

We introduce Sectored DRAM and its two key mechanisms: Variable Burst Length
and Sectored Activation. Sectored DRAM improves system performance and
alleviates system energy consumption by enabling fine-grained DRAM data
transfer and activation.

  * •

We develop two techniques (Load Store Queue Lookahead and Sector Predictor) to
effectively integrate Sectored DRAM into a system. Our techniques reduce the
number of high-latency memory accesses by accurately identifying the words of
a cache block that will be used by the processor.

  * •

We evaluate Sectored DRAM with a wide range of workloads and observe that it
provides higher system performance and energy efficiency than coarse-grained
DRAM as well as multiple prior fine-grained DRAM proposals.

  * •

We open source Sectored DRAM at https://github.com/CMU-SAFARI/Sectored-DRAM.

##  2 DRAM Background

We provide the most relevant background on DRAM organization for our
work.333We refer the reader to various prior works [29, 110, 58, 136, 109, 65,
108, 22, 52, 128, 75, 92, 134, 10, 13, 14, 34, 35, 53, 54, 55, 64, 66, 67, 89]
for a more detailed description of the DRAM architecture.

###  2.1 DRAM Organization

A typical computing system implements a _memory controller_ in the processor
chip. The memory controller connects to multiple _DRAM modules_ over multiple
_memory channels_. Fig. 1 illustrates the hierarchical DRAM organization
inside a DRAM module (a). Multiple _DRAM chips_ (b) constitute a DRAM module.
All DRAM chips in a module operate in lockstep where they receive the same
DRAM commands from the memory controller at the same time and respond to
commands in unison [54, 14]. A DRAM chip has multiple _DRAM banks_ (c) that
can be accessed in parallel. All banks in a chip share an input/output logic.

Figure 1: DRAM module, chip, and bank organization, as depicted in [90]

A DRAM bank consists of a _global row buffer_ (or _prefetch buffer_), a
_global row decoder_ (or a global wordline driver), and multiple _subarrays_.
The global row decoder drives a _global wordline_ signal in every subarray.
_Global bitlines_ connect the DRAM cells in each subarray to the global row
buffer via column select logic (CSL). Each subarray contains a set of _local
row decoders_ (or local wordline drivers), a _local row buffer_ , which is an
array of sense amplifiers (SAs), _helper flip-flops (HFFs)_ , and _mats_ (d).
Inside every mat, _DRAM cells_ are placed in a two-dimensional array of _local
wordlines_ and _local bitlines_. A DRAM cell (e) is comprised of an _access
transistor_ and a _cell capacitor_. DRAM cells that lie on the same local
wordline across different mats form a _DRAM row_ (not shown in the figure).

###  2.2 Accessing DRAM

The memory controller accesses DRAM in two steps. First, the memory controller
sends an $ACTIVATE$ ($ACT$) command with a _row address_ to open (i.e., make
accessible) a DRAM row. The global row decoder drives the global wordline
(master wordline) corresponding to the higher-order bits of the row address.
The master wordline enables _a single local wordline_ , addressed by the
lower-order bits of the row address, in every mat in a subarray. A driven
local wordline enables the access transistors of all cells in the DRAM row,
causing the cells to share their charge with their bitlines and the sense
amplifiers to read the values in the cells. Second, the memory controller
sends a $READ$ command with a _column address_ to retrieve multiple bytes of
data (e.g., $8\text{\,}\mathrm{B}$ for an x8 DDR4 chip [44]) from the open
DRAM row. The $READ$ command moves the data in the local row buffer, over the
helper flip-flops (HFFs), to the global row buffer (the prefetch buffer).
Thus, the _throughput_ of internal DRAM data transfers (i.e., between the
global and local row buffer) is constrained by the number of HFFs per mat.

Row buffer. Once a row is opened (i.e., the row is buffered in the local row
buffer), subsequent $READ$ and $WRITE$ commands targeting the row can be
served at a fast rate. An access that targets an open row is a _row buffer
hit_ and an access that targets a row other than the open row in a bank is a
_row buffer conflict_.

Accessing another row. When a bank already has an open row, and the memory
controller wants to access another row, the memory controller first issues a
$PRECHARGE$ ($PRE$) command to close the open DRAM row.

###  2.3 Data Transfer Bursts

DRAM modules transfer data on the memory channel over multiple _interface
clock cycles_. For example, a $READ$ command transfers a cache block (e.g.,
512 bits) over eight interface cycles in DDR4 [80]. Each such transfer is
referred to as a burst, and the _burst length_ defines the number of double-
data-rate (DDR) interface cycles it takes to transfer the data. A cache block
is divided into equally-sized pieces and placed in different chips (e.g., if
there are eight chips, each chip receives $\frac{1}{8}$ of the cache block).
These equally sized blocks are further split into multiple mats inside a bank
in the chip. We depict how a cache block is scattered across multiple chips
and mats for a DDR4 module in Fig. 2 (left). Fig. 2 (right) shows the timing
diagram of the command and data buses during a $WRITE$ transfer.

Figure 2: Example cache block placement in DRAM mats (left) and diagram
depicting an 8-cycle data transfer burst to Chip 0 (right). “B” means “byte”.

A DRAM data transfer happens in three steps (we use a $WRITE$ transfer as an
example; a $READ$ data transfer happens analogously). First, the memory
controller drives 64 _DQ_ (data) signals to transfer a 64-bit portion of the
cache block in each _beat_ (i.e., data transmitted in one DDR interface cycle)
of the data transfer burst ❶. Second, each chip receives 8 bits in a beat ❷. A
chip accumulates 64 bits during the burst in its prefetch buffer. Third, these
64 bits are copied into the mats inside the chip ❸. In our example, only 8
bits are transferred in a burst to (from) a mat with a $WRITE$ ($READ$)
command. Thus, the _maximum DRAM throughput_ can _only_ be obtained if every
mat contributes 8 bits to the data transfer burst.

###  2.4 The $t_{FAW}$ Timing Parameter

DDRx specifications (e.g., DDR4 [44] and DDR5 [45]) define the $t_{FAW}$
timing parameter, which specifies the time window where no more than four
$ACT$ commands are allowed (i.e., the memory controller can only schedule four
$ACT$ commands in any $t_{FAW}$-wide time window). $t_{FAW}$ allows a DRAM
chip to correctly provide the chip’s various components with the power
required to activate large DRAM rows. $t_{FAW}$ typically limits row
activation frequency and diminishes memory-level parallelism, degrading the
performance of memory-intensive workloads [51].

##  3 Motivation

We study the impact of coarse-grained DRAM data transfer (_Coarse-DRAM-
Transfer_) and activation (_Coarse-DRAM-Act_) in 41 single-core workloads from
a variety of domains (see section 6 for our methodology). We compare their
energy consumption to a system that performs (i) fine-grained DRAM data
transfer (_Fine-DRAM-Transfer_) at word granularity, and (ii) fine-grained
DRAM activation (_Fine-DRAM-Act_) at mat granularity.

Fig. 3 (left) shows the DRAM access energy across workloads from our three
benchmark suites for the _Coarse-DRAM-Transfer_ system, normalized to the
_Fine-DRAM-Transfer_ system. We observe that the DRAM access energy of the
_Coarse-DRAM-Access_ system is 1.27$\times$ that of the _Fine-DRAM-Access_.
The large increase in energy consumption in the _Coarse-DRAM-Access_ system is
caused by retrieving words in a cache block that the processor does _not_
entirely use. This leads to a 45% increase in the data movement between DRAM
and the CPU in the _Coarse-DRAM-Access_ system, on average. We conclude that
current systems that perform coarse-grained DRAM accesses and activation
_significantly_ waste energy by transferring and activating a fixed number of
words from DRAM to the processor, which are not entirely used by the
processor.

Figure 3: Normalized DRAM access (left) and DRAM activation (right) energy
consumption.

Fig. 3 (right) shows the DRAM activation energy across workloads from our
three benchmark suites for the _Coarse-DRAM-Act_ system, normalized to the
_Fine-DRAM-Act_ system. We observe that the DRAM activation energy of the
_Coarse-DRAM-Act_ system is 1.04$\times$ that of the _Fine-DRAM-Act_ system.
Like the system that performs coarse-grained DRAM accesses, the increase in
energy consumption in the coarse-grained DRAM activation system is caused by
activating a large, fixed-size DRAM row that the processor does _not_ entirely
use. As prior works [68, 29, 85, 82, 86, 121, 133, 88, 120] show, such an
increase in energy consumption when executing coarse-grained DRAM activation
is because modern memory-intensive workloads with irregular access patterns
suffer from low spatial locality, which reduces the benefit of a large DRAM
row buffer. We conclude that systems that employ coarse-grained DRAM
activation suffer from energy inefficiency.

Figure 4: Wordline organization in a conventional DRAM subarray (left), in a
Sectored DRAM subarray (right)

###  3.1 Enabling Fine-Grained DRAM: Challenges and Limitations

Efficiently enabling fine-grained DRAM data transfer and activation can
significantly improve system energy. However, to do so, we must overcome three
main challenges.

(1) Maintaining high DRAM throughput. Current DRAM systems leverage coarse-
grained data transfers to maximize DRAM’s throughput. Enabling fine-grained
DRAM in a straightforward way, e.g., by placing a piece of the cache block
stored by a DRAM chip in the same mat instead of distributing the piece across
multiple mats, reduces DRAM throughput as one mat contributes only a fraction
of the total DRAM internal throughput (section 2.3). This issue can be
alleviated by increasing the number of the HFFs. However, this approach is
costly since it severely complicates DRAM array routing [136, 68, 125].

(2) Incurring low DRAM area overhead. DRAM manufacturing is highly optimized
for density and cost [70, 85, 76]. While enabling fine-grained DRAM, one must
avoid applying intrusive modifications to the DRAM array since such
modifications are difficult to integrate into real designs.

(3) Fully exploiting Fine-Grained DRAM. The energy waste of coarse-grained
DRAM systems stems from rigid DRAM data transfer and activation granularities.
Thus, a fine-grained DRAM system must enable flexible DRAM data transfer _and_
activation granularities for _both_ read and write operations to eliminate
such energy waste. However, integrating fine-grained DRAM into current systems
is challenging as systems are typically designed to access DRAM at cache block
granularity.

Prior works [68, 136, 135, 3, 116, 92, 15, 18, 30, 124] propose different
mechanisms to enable fine-grained DRAM substrates, aiming to alleviate the
energy waste caused by coarse-grained DRAM. Such works can be divided into two
broader groups: (1) works that propose _intrusive_ modifications to the DRAM
array circuit and organization (e.g., new DRAM interconnects, considerably
more HFFs) [135, 3, 116, 92, 15] and (2) works that aim to enable coarse-
grained DRAM _without intrusive_ modifications to DRAM [18, 124, 136, 30, 68].
The intrusive DRAM modifications proposed by the first group lead to
significant DRAM area overheads, which makes it difficult to integrate the
first group of works into real DRAM designs.

Table 1 qualitatively compares how prior works from the second group address
the three challenges of enabling fine-grained DRAM. We observe that no prior
work can _simultaneously_ provide (i) high DRAM throughput (FGA [18] and SBA
[124] change the cache block mapping such that DRAM transfers can be served
from only one mat, but reduce the throughput of data transfers by doing so);
(ii) low area overhead (HalfDRAM [136] and HalfPage [30] require changes to
the number and organization of DRAM’s HFFs, leading to non-negligible area
overheads); and (iii) mechanisms that fully exploit fine-grained DRAM (PRA
[68] only enables fine-grained DRAM data transfer and activation for write
operations; HalfDRAM, HalfPage, FGA, and SBA still impose a rigid DRAM data
transfer granularity). We conclude that no prior work efficiently enables
fine-grained DRAM access (i.e., both data transfer and activation).

Table 1: Sectored DRAM vs. prior works

|  | High (100%)
---
Throughput
| Low (<2%)
---
Area Overhead
| Fully Exploit
---
Fine-Grained DRAM
|  |  | Activation | Data Transfer
FGA [18] | ✗ | ✓ | ✓ | ✗
SBA [124] | ✗ | ✓ | ✓ | ✗
HalfDRAM [136] | ✓ | ✗ | ✓ | ✗
HalfPage [30] | ✓ | ✗ | ✓ | ✗
PRA [68] | ✓ | ✓ | ✓ | ✗
This Work | ✔ | ✔ | ✔ | ✔

Our goal is to address prior works’ limitations while efficiently mitigating
the energy consumed by transferring unused data on the memory channel and
activating unused DRAM cells. To this end, we develop Sectored DRAM, a new,
practical, and high-performance fine-grained DRAM substrate.

##  4 Sectored DRAM

We leverage two key observations regarding DRAM chip design to implement
Sectored DRAM at low cost. First, we observe that DRAM mats naturally split
DRAM rows into fixed-size portions. Second, the DRAM I/O circuitry already
implements a mechanism to select one portion of a cache block to transfer it
in one beat (i.e., data transmitted in one DDR interface cycle) of a burst.

Sectored DRAM consists of two new mechanisms implemented in a DRAM chip:
Sectored Activation ($SA$) and Variable Burst Length ($VBL$). $SA$ enables
fine-grained control over the activation of sectors in DRAM by making minimal
modifications to how local wordlines are driven. $VBL$ enables fine-grained
control over data transfer bursts by transferring only the portions of a cache
block that correspond to the activated sectors in the DRAM chip.

We expose the two mechanisms to the memory controller such that the system can
benefit from Sectored DRAM, with _no_ changes to the physical DRAM interface
and only small changes to DRAM interface specification.

###  4.1 Sectored Activation

Fig. 4-A depicts the architecture of a DRAM array with 8 mats in one subarray
[60, 30, 52, 136, 92]. We make a key observation: DRAM mats split DRAM rows
into fixed-size portions. $SA$ augments these portions by allowing them to be
activated individually. We refer to these augmented portions as _sectors_.

SA Design. To implement $SA$, we propose minor modifications to the existing
architecture. Fig. 4-B depicts our modifications to the DRAM subarray with 8
mats (the modifications are highlighted in blue color).444We consider DRAM
subarrays with 8 sectors. See section 8.4 for a discussion of a finer-
granularity activation mechanism. First, we insert new local wordline drivers
(LWDs) (❶) such that each LWD drives only one local wordline (LWL). Thus, when
a single LWD is enabled, only the cells in a single sector are activated as
opposed to cells from all mats in a subarray getting activated in the existing
architecture (e.g., LWDs between mat 0 and mat 1 in Fig. 4-A drive two LWLs
that extend onto both of the mats). Second, to select which sectors are opened
with an $ACT$ command, we place one _sector latch_ (❷) for every sector in the
horizontal direction. Third, we isolate the master wordline (MWL) from the
LWDs using _sector transistors_ (❸), such that a driven MWL does _not_ enable
all LWDs in all sectors, but only enables LWDs in the open sector(s). With
these three modifications, a sector with a set (i.e., logic-1) sector latch is
activated when the MWL is driven (with an $ACT$ command) because two sector
transistors connect the MWL to the LWDs.

Exposing SA to the memory controller. To make use of $SA$, the memory
controller needs to control sector latches. To implement $SA$ with no
modifications to the DRAM interface signals, we use the unused bits in the
$PRE$ command’s encoding [44] to encode the _sector bits_. Each sector bit
identifies/encodes if a sector latch is set or reset. The memory controller
sends a bitvector of sector bits with every $PRE$ command to the Sectored DRAM
chip. These sector bits are used for the $ACT$ command that follows the $PRE$
command. When the bank is closed (i.e., there are no open rows in the bank),
the memory controller schedules a $PRE$ command before the first $ACT$ command
to convey the sector bits to the DRAM chip. The minimum timing delay between
successive $PRE$ and $ACT$ commands targeting the same bank (dictated by
$t_{RP}$, $\sim{}\\!13ns$ [44, 80]) is sufficiently long555We determine
$t_{RP}$ to be sufficiently long based on the overall latency of a READ
command in a conventional DRAM chip. A READ command 1) propagates from the
memory controller to the DRAM chip, 2) accesses data in a portion of the row
buffer in the corresponding bank, and 3) sends the data back to the memory
controller. In the DDR4 standard [44], the latency between issuing a READ and
the first data beat appearing on the data bus is defined as $tAA$
($12.5\text{\,}\mathrm{ns}$). Because sector bits need _only_ to propagate
from the memory controller to a DRAM bank (and not back to the memory
controller from a bank), the $t_{RP}$ timing parameter is likely longer than
what is needed (which we estimate as half $tAA$ or $6.25\text{\,}\mathrm{ns}$)
for sector bits to propagate from the memory controller to a DRAM bank. such
that the sector bits can propagate from the DRAM chip’s inputs to the sector
latches before the $ACT$ command following a $PRE$ command is issued to the
same DRAM bank. R4/6To issue regular, row-level DRAM commands (e.g., a
periodic refresh or an activate command), the memory controller simply sets
all sector bits (to enable all sectors) before issuing the row-level command.

Because activating one sector requires considerably less power consumption
(section 7.1) than activating all sectors, the $t_{FAW}$ timing constraint can
be relaxed to allow for, within a $t_{FAW}$, a larger number of $ACT$ commands
that activate fewer than all eight sectors in a DRAM row [136, 68, 92, 78,
79]. Section 6.3 describes how exactly we relax $t_{FAW}$ based on how many
sectors an $ACT$ command activates.

###  4.2 Variable Burst Length

$VBL$’s goal is to allow a DRAM chip to transmit (i.e., $READ$) and receive
(i.e., $WRITE$) data in variable length bursts666Commodity DDR4 chips already
implement a relatively constrained version of $VBL$ called _burst-chop_.
Burst-chop enables 256-bit (in 4-beat bursts) data transfers [44]. such that
each beat of the burst transfers only the data corresponding to one of the
enabled sectors.

VBL design. Fig. 5 depicts the I/O read/write circuitry of a modern DRAM chip
[80]. In such a chip, data is first moved from the DRAM array to the _Read
FIFO_ (❶) with every $READ$ command. The _Read FIFO_ comprises eight entries,
and each entry stores the data that will be transmitted over the DQ pins in
one beat of the data transfer burst. The _Read MUX_ (❷) selects one entry in
the _Read FIFO_ based on the value of the _burst counter_ (not shown in the
figure), which counts the number of beats in the transfer.

Figure 5: I/O circuitry of a DRAM chip and Variable Burst Length

By studying the I/O read/write circuitry of modern DRAM chips, we observe that
a DRAM chip selects (using the burst counter) individual entries in the _Read
FIFO_ to drive the DQ pins within a beat [80]. Based on this observation,
$VBL$’s key idea is to slightly modify the DRAM chip’s Read FIFO entry
selection criteria. We replace the burst counter with an 8$\times$3 encoder
(❸) that takes sector bits as input, and outputs only the indices for the
_Read FIFO_ entries that contain data from one of the closed sectors. Using
the encoder, the _Read MUX_ skips the entries in the _Read FIFO_ that
correspond to the closed sectors, driving the DQ pins _only_ with the data
that comes from the open sectors (❹ in Fig. 5, right). Since the _Write FIFO_
is organized in the same way as the _Read FIFO_ , $VBL$ reuses the same
encoder for $WRITE$ transfers to correctly fill the entries in the _Write
FIFO_.

Exposing VBL to the memory controller. To use $VBL$, the memory controller and
the DRAM chip need to agree on the burst length _before_ the data transfer
starts. This is important for both parties to calibrate their I/O drivers
correctly and capture the signals on the high-frequency DRAM interface [44,
45, 43]. We use the sector bits that are already communicated to the DRAM chip
by fine-grained DRAM activation operations to determine the burst length
(section 4.1) of data transfers, before the transfers start.

We make two modifications. First, we implement a low overhead 8-bit _popcount_
circuit [27, 19] in both the DRAM chip and the memory controller to count the
number of set sector bits in the DRAM bank targeted by a $READ$ or a $WRITE$.
The popcount circuitry requires _only_ 34 logic gates to be implemented [19],
introducing almost negligible area overhead. Second, we extend the _bank state
table_ of the memory controller with sector bits. The bank state table already
contains metadata, such as the address of the enabled row, for every bank. The
additional storage requirement for sector bits in the bank state table is
small, only 128 bits (8 bits for each of the 16 banks [80, 44]).

##  5 System Integration

We describe the challenges in integrating Sectored DRAM into a typical system
and propose solutions. We assume that the system uses a DDR4 module with
_eight chips_ as main memory and that each chip has _eight sectors_ to explain
the challenges and our solutions clearly.777In section 8, we discuss how
Sectored DRAM can be integrated into systems with different parameters (e.g.,
more sectors per chip). Since there are eight sectors in every chip, one
sector from each DRAM chip collectively stores _one word_ (64 bits) of the
cache block.

Integration challenges. We identify two challenges in integrating Sectored
DRAM into a system. First (section 5.1), to benefit from Sectored DRAM’s
potential energy savings, the system and main memory (DRAM) must conduct data
transfers at sub-cache-block granularity (e.g., transfer one or multiple
words). Therefore, a cache block may have both _valid_ (up-to-date) and
_invalid_ (stale or evicted) words present in system caches. However, caches
keep track of the valid on-chip data at cache block granularity. This
granularity is too coarse to keep track of valid words in a cache block.
Second (section 5.2), because some words in a cache block can be invalid,
references to these words (e.g., made by load/store instructions) would result
in a cache miss. This can induce performance overheads.

We propose the following minor system modifications to overcome Sectored
DRAM’s integration challenges. First, to track which words in a cache block
are valid, we extend cache blocks with additional bits each of which indicates
if a 64-bit word in the cache block is valid. Second, to accurately retrieve
all _useful_ words in a cache block, i.e., words that will be used until the
cache block is evicted, we develop two techniques: (i) Load-Store Queue (LSQ)
Lookahead, and (ii) Sector Predictor.

###  5.1 Tracking Valid Words in the Processor

Since a Sectored DRAM-based system can retrieve individual words of a cache
block from DRAM, system caches must store data at a granularity that is finer
than the typical 512-bit granularity. One straightforward approach to allow
finer-granularity storage in caches is to reduce the cache block size from 512
bits to the size of a word (e.g., 64 bits). However, for the same cache size,
doing so requires implementing $8\times{}\\!$ as much storage for _cache block
tags_ , which introduces significant area overhead. Instead, we extend cache
blocks with just eight additional bits each of which indicates whether a word
in the cache block is valid or invalid, using sectored caches [72, 112, 4, 36,
101, 50, 7, 103, 73].

Sector cache organization. We add storage for eight sector bits to all system
caches. We store sector bits in a CAM array (similar to how cache block tags
are stored). This allows a cache to find out if a _sector is missing_ (i.e., a
word is invalid) in a cache block in parallel with the tag lookup. We divide a
cache block into eight sectors, each corresponding to a word. Thus, we only
add eight sector bits to a cache block, which incurs low storage overhead
(section 7.5).

Sector cache operation. We describe the three-step process performed by a
memory request to access a word in the highest-level sector cache (i.e., the
L1 cache). First, the processor sends a memory request with a memory address
and a vector of eight sector bits to the highest-level cache. The sector bits
identify the words in the cache block that the processor core demands. Second,
the L1 cache uses the memory address to identify the addressed cache set.
Third, the L1 cache uses the cache block tag component of the memory address
and the sector bits to access the words requested by the processor. The third
step can result in three different scenarios: 1) if both the tag and the
sector bits match one of the cache blocks in the cache set (i.e., there is
both a tag and a sector bit match), the cache has the word that the processor
core demands and this is a _sector hit_ , 2) if there is a tag match but no
sector bit match, the cache has to request the missing sectors from a lower-
level cache or main memory and this is a _sector miss_ , and 3) if there is no
tag match, this is a _cache miss_.

Sector misses. On a sector miss, the cache controller creates a memory request
to retrieve the missing sector(s) from a lower-level cache or main memory. The
cache controller determines the missing sector(s) by bitwise AND’ing the
memory request’s (the request that triggers the sector miss) sector bits and
the sector bits that are _not_ set in the cache block. When the created memory
request returns from a lower-level cache, the cache controller sets the cache
block’s missing sector bits.

Sector cache compatibility. Sector caches do not require any modifications to
existing _cache coherence protocols_ (we explain how in the next paragraph).
Sector caches are compatible with existing SRAM ECC schemes [77, 122, 81], as
the invalid words (i.e., missing sectors) in a cache block can still be used
to correctly produce a codeword.

R2/1Cache Coherence. Sectored DRAM requires no modifications to existing cache
coherence protocols that operate at the granularity of a cache block since
cache coherence in Sectored DRAM is still maintained at cache block
granularity. A processor core can only modify a sector in a cache block if the
core owns the entire cache block (e.g., the cache block is in the M state in a
MESI protocol). A cache block shared across multiple cores may have different
valid sectors among its copies in different private caches. However, this does
not violate cache coherence protocols.

Other cache architectures. There are numerous other multi-granularity cache
architectures [98, 97, 102, 111, 62, 38] that could be used instead of
sectored caches in Sectored DRAM to improve cache utilization (e.g., by
reducing the number of invalid words stored in a cache block) at the cost of
increased storage for tags and hardware complexity [62]. We use sectored
caches to minimize the storage and hardware complexity overheads in Sectored
DRAM and leave the exploration of other cache architectures in Sectored DRAM
to future work.

###  5.2 Accurate Word Retrieval from Main Memory

With sector caches, a Sectored DRAM-based system can transfer data at word
granularity between components in the memory hierarchy (e.g., between the L1
and the L2 cache) instead of transferring data at cache block granularity.
However, retrieving cache blocks word-by-word from DRAM can reduce system
performance compared to bringing cache blocks as a whole because the processor
needs to complete multiple high latency DRAM accesses to retrieve a word (on a
sector miss) as opposed to completing a single memory access to retrieve the
whole cache block. To minimize the performance overheads induced by the
additional DRAM accesses and to better benefit from the energy savings
provided by Sectored DRAM, we propose two mechanisms that greatly reduce the
number of sector misses.

Load/Store Queue (LSQ) Lookahead. The key idea behind LSQ Lookahead is to
exploit the spatial locality in subsequent load/store instructions that target
the same cache block. A load or a store instruction typically _references_ one
word in main memory. LSQ Lookahead, at a high level, looks ahead in the
processor’s load/store queues888The LSQ stores the necessary metadata (e.g.,
register destination identifiers, operands, and virtual and physical addresses
of memory operands) to correctly execute and commit load and store
instructions. We refer the readers to [113, 129, 114] for implementation
details of the LSQ in modern microprocessors. and finds load and store
instructions that reference _different words/sectors in the same cache block_.
LSQ Lookahead then collects the word/sector references, made by younger
load/store instructions to the same cache block as the oldest load/store
instruction, and stores the collected sector references in the oldest
load/store instruction’s sector bits. This way, a load/store instruction, when
executed, retrieves all words in a cache block that will be referenced in the
near future (by younger load/store instructions) to the L1 cache with _only_
one cache access.

Fig. 6(a) depicts how LSQ Lookahead is implemented over an example using load
instructions. We extend each load address queue (LAQ, stores metadata for load
instructions) entry with sector bits (SB). LSQ Lookahead works in two steps.
First, when a new entry is allocated at LAQ’s tail (❶), the LSU compares the
new entry’s cache block address (CB address) with each of the existing
entries’ cache block addresses (❷). Second, when it finds a matching cache
block address, it updates the existing entry’s sector bits by setting the bit
that corresponds to the word referenced by the new entry (❸).

Sector Predictor (SP). Although LSQ Lookahead prevents some of the sector
misses, it alone _cannot_ significantly reduce the number of sector misses.
This is because load/store queues are typically _not_ large enough to store
many load/store instructions, and dependencies (e.g., data dependencies)
prevent the processor core from computing the memory addresses of future
load/store instructions. Thus, we require a more powerful mechanism to
complement LSQ Lookahead and minimize sector misses. To this end, we develop
the Sector Predictor (SP).

SP, at a high level, records which words are used while a cache block is in
the cache. The next time the same cache block misses, SP uses that signature
to predict that the load would need the same words. SP leverages two key
observations to accurately predict which words a load needs to access. First,
the processor will “touch” (access or update) one or multiple words in a cache
block from the moment a cache block is fetched to system caches (from main
memory) until it is evicted to main memory. The touched words in a cache block
_will likely be touched again_ when the cache block is next fetched from main
memory. Second, dynamic instances of the same static load/store instruction
likely touch the same words in different cache blocks. For example, a static
load/store instruction in a loop may perform strided accesses to the same word
offset in different cache blocks. SP builds on a class of predictors referred
to as spatial pattern predictors (e.g., [61, 16]). We tailor SP for predicting
a cache block’s useful words (those that are referenced by the processor
during the cache block’s residency in system caches), similar to what is done
by [132].

Fig. 6(b) depicts the organization of the SP. The Sector History Table (SHT)
stores the _previously used sectors_ that identify the sectors (words) that
were touched by the processor in a now evicted cache block in the L1 cache
(❶). SHT is accessed with a _table index_ that is computed by XOR-ing parts of
the load/store instruction’s address with the _word offset_ of the load/store
instruction’s memory address upon an L1 cache miss (❷). We extend the L1 cache
to store the table index and the _currently used sectors_ (❸). The currently
used sectors in the cache track which sectors are used during a cache block’s
residency. The table index is used to update the previously used sectors in an
entry in the SHT with the currently used sectors stored in the cache block
upon the cache block’s eviction (❹).

(a) LSQ Lookahead mechanism

(b) Sector Predictor table and indexing

Figure 6: Two system components of Sectored DRAM: a) LSQ Lookahead and b)
Sector Predictor

We describe how SP operates (not shown in the figure) in five steps based on
an example where a memory request accesses the L1 cache. First, when the
memory request causes a cache miss or a sector miss, the SHT is queried with
the table index to retrieve the previously used sectors. Second, the
previously used sectors are added to the sector bits of the memory request and
forwarded to the next level in the memory hierarchy. Third, the L1 miss
allocates a new cache block in the L1 cache. Fourth, the table index of the
newly allocated cache block is updated with the table index used to access the
SHT, and the cache block’s currently used sectors are set to logic-0. Fifth,
once the missing cache block is placed in the L1 cache, the cache block’s
currently used sectors start tracking the words that are touched by future
load/store instructions. When the same cache block is evicted from the L1
cache, the SHT entry corresponding to the cache block’s table index is updated
with the currently used sectors.999Due to aliasing in SHT index computation,
multiple cache blocks can point to the same SHT entry. SHT receives
conflicting updates if two or more such cache blocks are evicted from L1 in
the same clock cycle. SHT selects and applies only one update among
conflicting updates.

##  6 Evaluation Methodology

We describe the workloads (section 6.1), power model (section 6.2), and
simulation infrastructure used to evaluate Sectored DRAM (section 6.3).
R4/3Table 3 shows our system configuration that we simulate using Ramulator
[59, 104, 74, 105]. Ramulator implements all standard DDR4 timing parameters.
Our simulation infrastructure is open source [107].

###  6.1 Workloads

We use 41 workloads from the SPEC2006 [118] (23 workloads), SPEC2017 [119] (12
workloads)101010Due to our trace generation infrastructure limitations, we
evaluate _only_ those workloads that we could successfully generate traces
for., and DAMOV [91] (6 DRAM-bandwidth-bottlenecked representative application
functions) to evaluate Sectored DRAM. For every workload, we generate memory
traces corresponding to 100 million instructions from representative regions
in each workload using SimPoint [31]. We classify the workloads into three
memory intensity categories (as also done by prior work [91, 33]), which Table
3 describes, using their observed last-level-cache (LLC) misses-per-kilo-
instruction (MPKI).

R4/1table  Processor 1–16 cores, 3.6 GHz clock frequency, 4-wide issue 8 MSHRs
per core, 128-entry issue window 32 KiB L1, 256 KiB L2, 8 MiB L3 caches
Dynamic Power: 101.7 W [71], Static Power: 32.0 W [71] Mem. Ctrl. 64 entry
read/write request queue, FR-FCFS-Cap [86] scheduling policy, Open-page row
buffer policy, Auto-precharge on last read/write to a row Row-Bank-Rank-
Column-Channel address mapping [59] DRAM DDR4 [44], 3200 MT/s data transfer
rate, 1, 2, and 4 channels 4 ranks, 16 banks/rank, 32K rows/bank 64
subarrays/bank, 8 sectors/subarray $tRCD$/$tRAS$/$tRC$/$tFAW$
13.75/35.00/48.75/25 ns $tRRD\\_L$/$tRRD\\_S$ 5.00/2.50 ns Sectored DRAM
128-entry LSQ Lookahead (default) 512-entry Sector Predictor (default) LLC
MPKI Workloads $\geq{}10$ (High) ligraPageRank, mcf-2006, libquantum-2006,
gobmk-2006, ligraMIS, GemsFDTD-2006, bwaves-2006, lbm-2006, lbm -2017,
hashjoinPR $1..10$ (Medium) omnetpp-2006, gcc-2017, mcf-2017, cactusADM-2006,
zeusmp-2006, xalancbmk-2006, ligraKCore, astar-2006, cactus-2017, parest-2017,
ligraComponents $\leq 1$ (Low) splash2Ocean, tonto-2006, xz-2017, wrf-2006,
bzip2-2006, xalancbmk-2017, h264ref-2006, hmmer-2006, namd-2017, blender-2017,
sjeng-2006, perlbench-2006, x264-2017, deepsjeng-2017, gromacs-2006, gcc-2006,
imagick-2017, leela-2017, povray-2006, calculix-2006

Table 2: System configuration Table 3: Evaluated workloads. -2006/-2017
indicates SPEC

Multi-core workloads. We create 2-, 4-, 8-, and 16-core workloads by
replicating the same single-core workload over multiple cores. We create 16
eight-core workload mixes for each memory intensity category by randomly
picking eight single-core workloads from every category.

###  6.2 Power Model

DRAM power model. We use the Rambus Power Model [125, 99] to model a DDR4 chip
(Table 3) that supports Sectored DRAM. We modify the model to (i) activate a
smaller number of sectors ($SA$) and (ii) reduce the burst size of data
transfers for partially activated DRAM rows ($VBL$). Our model considers the
power overheads introduced by the sector transistors and latches. R3/1aRambus
Power Model computes and reports the current consumed by a sequence of DRAM
commands (e.g., $ACT$, $RD$, $WR$, and $NOP$). We use three command sequences
described in one major DRAM manufacturer’s power calculation guide [100] to
calculate three important current values: IDD0 ($ACT$), IDD4R ($READ$), and
IDD4W ($WRITE$).

R3/2Processor power model. We use an IPC-based model [132, 1] to estimate the
power consumed by the entire processor. The total power our 8-core processor
consumes is equal to: $\frac{IPC}{4}\times Dynamic\ Power+Static\ Power$. We
comprehensively account for all Sectored DRAM power overheads. Our model
includes the dynamic and static power consumed by the sector predictor and the
additional cache storage (modeled by CACTI [84]). Our system energy results
represent the energy consumed by main memory and the entire processor during
the execution of an evaluated workload.

###  6.3 Performance and Energy

R3min/4We evaluate Sectored DRAM’s performance and energy using a modified
version of Ramulator [59, 74], a cycle-accurate, trace-based DRAM simulator,
and a modified version of DRAMPower [12], a DRAM power and energy estimation
tool. We extend Ramulator by implementing Sectored DRAM’s LSQ Lookahead and
Sector Predictor as described in section 5. We modify how Ramulator enforces
the $t_{FAW}$ timing constraint. Our modification allows for 32 sectors (i.e.,
the number of sectors in four rows) to be activated within a $t_{FAW}$ (e.g.,
the memory controller can activate 4 sectors from 8 different rows and 8
sectors from 4 different rows). The rate of $ACT$ commands is still
constrained by the $tRRD\\_{L}$ and $tRRD\\_{S}$ parameters in our modified
Ramulator model. Therefore, our memory controller issues up to 10 activate
commands (calculated as
$$25.0\text{\,}\mathrm{ns}$/$2.5\text{\,}\mathrm{ns}$$) in a $tFAW$ window. To
verify that the peak power draw imposed by the higher rate of finer-
granularity $ACT$ commands (e.g., an $ACT$ command that activates _only_ one
sector from a row) does _not_ increase the power requirements of a DRAM chip,
we compare the power draw of 1) four activate commands each of which activates
all eight sectors in a row (the rate of activate commands are constrained by
$tFAW$) to 2) 10 activate commands each of which activates one sector in a row
(the rate of activate commands are constrained by $tRRD\\_S$), in a default
$tFAW$ long time window ($25\text{\,}\mathrm{ns}$ in our configuration) using
Rambus Power Model [99]. We find that 10 activate commands each of which
activates one sector from a row consume 20.34% less power than four activate
commands each of which activates all eight sectors in a row (and as such
Sectored DRAM operates within the region that conventional DRAM is designed to
operate). R3/1bWe modify DRAMPower by integrating Sectored DRAM’s current
values (e.g., IDD0, IDD4R, and IDD4W) that we obtain from the modified Rambus
Power Model.

Performance metrics. We measure single-workload performance using _parallel
speedup_ (i.e., the baseline single-core execution time divided by the multi-
core Sectored DRAM execution time), which allows us to evaluate Sectored
DRAM’s scalability for a single workload. We measure workload mix performance
using _weighted speedup_ [115], which allows us to evaluate Sectored DRAM’s
system throughput [26] in a heterogeneous computing environment.

##  7 Evaluation Results

We evaluate Sectored DRAM’s impact on DRAM power, LLC MPKI, performance,
energy, and DRAM area.

###  7.1 Impact on DRAM Power

Fig. 7 shows Sectored DRAM’s impact on DRAM power consumption. We analyze the
DRAM array power, DRAM peripheral circuitry power, and DRAM energy consumed by
Sectored DRAM to perform $ACT$, $READ$, and $WRITE$ DRAM operations for 8, 4,
2, and 1 sectors. Our results show that $READ$ and $WRITE$ power and energy
greatly reduces as fewer sectors are read or written to.

Figure 7: DRAM command power and energy for varying number of sectors

We make three observations from Fig. 7. First, $SA$ and $VBL$ significantly
improve $READ$ and $WRITE$ power consumption. We find that the power consumed
by DRAM while reading from and writing to a sector is 70.0% and 70.6% smaller
than reading from and writing to all sectors, respectively. This improvement
is due to the (i) reduced sense amplifier activity in the DRAM array, (ii)
reduced switching on the DRAM peripheral circuitry that transfers data between
the DRAM array and the DRAM I/O, and (iii) smaller number of beats in a burst
to transfer data between the DRAM module and the memory controller.

Second, activating only one sector greatly reduces the power consumed by the
DRAM array compared to activating all eight sectors. Because $SA$ enables
activating a small set of DRAM sense amplifiers in a DRAM row, activating a
single sector consumes 66.5% less DRAM array power compared to activating
eight sectors. However, we find that activating one sector reduces the overall
power consumption of an $ACT$ operation by only 12.7% compared to the baseline
DDR4 module. This effect is small since the power consumed by the peripheral
circuitry makes up a large proportion of the activation power and is not
affected by the number of sectors activated. Third, the circuitry required to
implement $SA$ incurs little activation power overhead. Compared to the
baseline DDR4 module, $SA$ increases activation power by only 0.26% due to
additional switching activity in master wordline drivers (section 4.1).

Effects of DRAM Bus Frequency. R4/5We investigate how DRAM bus frequency
affects the read power (IDD4R) relative to the activate power (IDD0). We
repeat our experiments using 2$\times{}$ the frequency of the baseline bus
frequency (i.e., 3200 MHz or 6400 MT/s). The read power (IDD4R) is
$12.39\times$ and $12.42\times$ higher than the activate power (IDD0) at the
baseline bus frequency (3200 MT/s) and twice the baseline bus frequency (6400
MT/s), respectively (this observation is in line with that of a prior work’s
[21]).

We conclude that 1) Sectored DRAM’s fine-grained DRAM data transfer and
activation provide a significant reduction in DRAM read and write power and
energy and 2) the bus frequency does _not_ significantly affect DRAM read
power relative to DRAM activate power.

###  7.2 Number of Sector Misses

To quantify the number of sector misses (see section 5.1), we look at the LLC
MPKI of workloads run with different Sectored DRAM configurations. Fig. 8
plots the LLC MPKI for different LSQ Lookahead (LA$<$_number_ $>$ where
_number_ is the number of entries looked ahead in the LSQ) and Sector
Predictor (SP$<$_number_ $>$ where _number_ is the number of entries in the
SHT) configurations along with the _Basic_ Sectored DRAM configuration which
does not use LSQ Lookahead nor SP. Each bar shows the average LLC MPKI across
all evaluated workloads in each benchmark suite (x-axis, see Table 3 for a
list of all workloads classified according to their LLC MPKI) for a Sectored
DRAM configuration.

Figure 8: LLC MPKI for different Sectored DRAM configurations

We make three major observations. First, Sectored DRAM without LSQ Lookahead
and SP (Basic) greatly increases the LLC MPKI of a workload, on average by
3.1$\times{}$, compared to the baseline, due to sector misses. Second, LSQ
Lookahead reduces the number of LLC misses of Basic by 25%, 41%, and 51% by
looking ahead 16, 128, and a currently very costly 2048 younger entries in the
LSQ, respectively. This is because LSQ Lookahead can identify the words that
will be used in a cache block and retrieve these from DRAM with a single
memory request. Third, LSQ Lookahead together with SP (LA128-SP512) reduces
the number of LLC misses of Basic by 52% and of LA128 by 18%. LA128-SP512
performs as well as the currently very costly implementation of LSQ Lookahead
which looks ahead 2048 entries in the LSQ. LA128-SP512 does so as SP greatly
reduces the number of additional LLC misses by recognizing intra-cache-block
access patterns from previously performed memory requests and correctly
predicts the words that will be used in a cache block.

We conclude that LSQ Lookahead with a 128 lookahead size together with SP
minimizes the LLC misses caused by sector misses. We use the LA128-SP512
configuration in the remainder of our evaluation.

###  7.3 Single-Workload Performance and Energy

We evaluate Sectored DRAM’s performance and energy using (i) single-core
workloads, and (ii) 2-, 4-, 8-, and 16-core multi-programmed workloads made up
of identical single-core workloads. We compare Sectored DRAM’s performance and
system energy to a baseline coarse-grained DRAM system.

Microbenchmark performance. Fig. 9 shows the normalized parallel speedup of a
random access (Random, left) and a strided streaming access (Stride, right)
workload for the baseline system and Sectored DRAM (LA128-SP512). The Random
workload accesses i) one randomly determined word in main memory (8 bytes) by
executing a load instruction every five instructions and ii) has a very high
LLC MPKI of 178.29. These two properties of Random make it a good fit for
Sectored DRAM as Random accesses _only_ one sector in every cache line. The
Stride workload accesses i) every word address in a contiguous, 16 MiB large
memory address range with a stride of 64 bytes, i.e., Stride accesses the
following addresses [0, 64, 128, …, 8, 72, 132, …, 16, …] and ii) has a very
high LLC MPKI of 78.57. Stride is a poor fit for Sectored DRAM because every
access to a word in a cache line results in a _sector miss_ (none of the
accessed 8-byte words are cached and these words have to be fetched from main
memory), where the large cache block reuse distance prevents LSQ Lookahead
from prefetching all useful words in a cache block.

Figure 9: Normalized parallel speedup of random and strided streaming
microbenchmarks for varying number of cores

We make two major observations from Fig. 9. First, Sectored DRAM provides
significant performance benefits for workloads that randomly access words
(e.g., Random). Sectored DRAM’s performance benefits increase with the number
of cores (i.e., with increasing LLC MPKI) for Random because a larger fraction
of all memory requests (random word accesses) benefit from Sectored DRAM’s
reduction in $tFAW$ (section 4.1). Sectored DRAM provides 1.11$\times{}$,
1.69$\times{}$, 1.87$\times{}$, 1.87$\times{}$, and 1.87$\times{}$ normalized
parallel speedup for 1, 2, 4, 8, and 16 cores, respectively for Random.
Second, Sectored DRAM reduces system performance for workloads that frequently
cause sector misses (e.g., Stride). Sectored DRAM provides 0.67$\times{}$,
0.95$\times{}$, 1.00$\times{}$, 1.00$\times{}$, and 1.00$\times{}$ the
normalized parallel speedup of Baseline for 1, 2, 4, 8, and 16 cores,
respectively for Stride. Sectored DRAM’s performance becomes closer to
Baseline as the number of cores increases. This is because the LLC is _not_
large enough to store all cache lines accessed by four or more cores for
Stride (i.e., Baseline accesses main memory to retrieve each word, similarly
to Sectored DRAM).

Performance. The two lines in Fig. 10(a) show the normalized parallel speedup
(on the primary/left y-axis) of three representative high MPKI (top row),
medium MPKI (middle row), and low MPKI (bottom row) workloads for the baseline
system (solid lines) and Sectored DRAM (dashed lines). Fig. 10(b) (top row)
shows the distribution of normalized parallel speedups of all high, medium,
and low MPKI workloads.111111Each box is lower-bounded by the first quartile
and upper-bounded by the third quartile. The median falls within the box. The
inter-quartile range (IQR) is the distance between the first and third
quartiles (i.e., box size). Whiskers extend to the minimum and maximum data
point values on either side of the box, while a bubble depicts average values.

(a) Normalized parallel speedup (primary/left y-axis) and system energy
(secondary/right x-axis) of representative high, medium, and low LLC MPKI
workloads for 1–16 cores

(b) Normalized parallel speedup (top) and system energy (bottom) distribution
of all high, medium, and low LLC MPKI workloads for varying number of cores11

Figure 10: Sectored DRAM system performance and energy

We make three observations from the two figures. First, Sectored DRAM provides
higher parallel speedup over the baseline for high MPKI workloads when the
number of cores is larger than two. For example, Sectored DRAM provides 26%
higher parallel speedup than the baseline for all 16-core high MPKI workloads
on average.121212R1/1We observe a decrease in normalized parallel speedup for
hmmer-2006 and mcf-2017 as the number of cores increase from 8 to 16. This is
because the two workloads, when ran on 16 cores, contend for memory at a
higher degree than when ran on 8 cores in the simulated system. For example,
16-core hmmer-2006 has 24.41% higher average latency for memory requests than
8-core hmmer2006. As the average row buffer hit rate for 16-core high MPKI
workloads is only 18%, the memory controller needs to issue many $ACT$
(activate) commands to serve the memory requests. Sectored DRAM’s $t_{FAW}$
reduction (section 4.1) allows the memory controller to issue the large number
of $ACT$ commands required by these workloads (i.e., 82% of all main memory
requests) at a higher rate, reducing the average memory access latency for
these workloads (by 25% on average for 16-core high MPKI workloads). Second,
Sectored DRAM, on average, provides a smaller parallel speedup compared to the
baseline for low and medium MPKI workloads. Although Sectored DRAM’s $t_{FAW}$
reduction reduces the proportion of processor cycles where the memory
controller has to stall to satisfy the $t_{FAW}$ timing parameter from 14.4%
in the baseline to 6.5% in Sectored DRAM for 16-core low and medium MPKI
workloads, the average memory latency for these workloads increases by 0.5% in
Sectored DRAM compared to the baseline. Moreover, for these workloads, sector
misses increase the number of memory requests on average by 69%. Because a
larger number of memory requests experience higher latencies in Sectored DRAM
compared to the baseline, Sectored DRAM provides a smaller parallel speedup
for these workloads. R4/8Third, Sectored DRAM incurs 5.41% performance
overhead on average across all single-core workloads. We attribute this to
sector misses that increase the number of memory requests and the average
memory latency.

System energy consumption. The bars in Fig. 10(a) show the system energy
consumption (on the secondary/right y-axis) of Sectored DRAM normalized to the
system energy consumption of the baseline. Fig. 10(b) (bottom) shows the
distribution of normalized system energy consumption for workloads from three
categories (low, medium, and high MPKI). We make two observations. R1/3First,
Sectored DRAM reduces system energy consumption for high MPKI workloads when
the number of cores is larger than two. On average at 16 cores, high MPKI
workloads’ system energy consumption reduces by 20%. Sectored DRAM achieves
this by a combination of (i) reduced DRAM energy consumption due to $SA$ and
$VBL$ (we present a detailed breakdown of $SA$ and $VBL$’s effects on DRAM
energy consumption in section 7.4), and (ii) reduced background power
consumption by the computing system as workloads execute faster. Second, for
medium and low MPKI workloads, Sectored DRAM increases system energy
consumption. We observe that Sectored DRAM increases the average DRAM energy
consumption by 12% for 16-core medium/low MPKI workloads. The increase in DRAM
energy consumption together with the increase in background power consumption
by the 1computing system (as workloads execute slower, Fig. 10(a)) increases
the system energy consumption for these workloads.

We conclude that Sectored DRAM improves system performance and reduces system
energy consumption in high MPKI workloads where: (i) a high number of $ACTs$
targets different DRAM banks (i.e., the workload is bound by $t_{FAW}$), and
(ii) the sector predictor can accurately predict the used words.

###  7.4 Multiprogrammed Workload Performance and Energy

We evaluate Sectored DRAM’s performance and energy using multi-programmed
workload mixes. To stress DRAM and cache hierarchy, we use high MPKI workload
mixes. We compare Sectored DRAM’s performance and main memory access energy to
a baseline coarse-grained DRAM system and three state-of-the-art fine-grained
DRAM mechanisms: (i) Fine-Grained Activation (FGA) [18, 124], (ii) Partial Row
Activation (PRA) [68], and (iii) HalfDRAM [136] and HalfPageDRAM [30]131313We
estimate HalfPageDRAM’s [30] performance and energy benefits using HalfDRAM
[136] as both techniques enable half-size DRAM row activations at high DRAM
throughput.. Unless otherwise stated, HalfDRAM depicts the evaluated
performance and energy of both HalfDRAM and HalfPageDRAM in the remainder of
the paper.

Performance. Fig. 11 (top) shows the weighted speedup [20, 26, 56] of 16
workload mixes for Sectored DRAM and the three state-of-the-art fine-grained
DRAM mechanisms, normalized to the baseline system. We make four observations.
First, Sectored DRAM’s weighted speedup is 1.17$\times$ (1.36$\times$) that of
the baseline, on average (maximum), across all workload mixes. This is due to
Sectored DRAM’s $t_{FAW}$ reduction. Sectored DRAM serves $READ$ requests
faster (Sectored DRAM’s average DRAM read latency is approximately 25% smaller
compared to the baseline) and thus improves the performance of the memory-
intensive workloads. Second, Sectored DRAM greatly outperforms naive fine-
grained DRAM mechanisms (i.e., FGA [18, 124]). We observe that Sectored DRAM’s
weighted speedup is 2.05$\times$ that of FGA, on average across all workloads.
FGA mechanisms greatly reduce the throughput of DRAM data transfers as they
are limited to fetching a cache block from a single mat (section 3.1). Third,
Sectored DRAM’s weighted speedup is 1.10$\times$ that of PRA, on average
across all workloads. Sectored DRAM outperforms PRA by enabling fine-grained
DRAM access and activation for _both_ $READ$ and $WRITE$ operations, while PRA
is limited to $WRITE$ operations.

Figure 11: Weighted speedup improvement over the baseline (higher is better)
on top. DRAM energy normalized to the baseline (lower is better) on the
bottom.

Fourth, Sectored DRAM’s weighted speedup is 0.89$\times$ that of HalfDRAM, on
average across all workloads. Sectored DRAM _cannot_ improve performance as
much as HalfDRAM since, in Sectored DRAM, the memory controller needs to
service additional memory requests caused by sector misses. However, as we
show next, HalfDRAM’s higher performance benefits come at the cost of _higher_
area overheads (section 7.5) and _lower_ energy savings than Sectored DRAM.

DRAM energy consumption. Fig. 11 (bottom) shows the DRAM energy consumption of
each workload mix for Sectored DRAM and the state-of-the-art mechanisms.
Values are normalized to the DRAM energy in the baseline system. We observe
that (i) Sectored DRAM _significantly_ reduces DRAM energy consumption
compared to the baseline, leading to up to (average) 33% (20%) lower DRAM
energy consumption, and (ii) Sectored DRAM enables larger DRAM energy savings
compared to prior works. On average, across all workload mixes, Sectored DRAM
reduces DRAM energy consumption by 84%, 13%, and 12% compared to FPA, PRA, and
HalfDRAM.

We analyze the impact of Sectored DRAM on the energy consumed by DRAM
operations. Fig. 12 (left) shows the DRAM energy broken down into $ACT$,
background, and $RD/WR$ consumption, normalized to the baseline system DRAM
energy consumption, averaged across all workload mixes. We make two
observations.

Figure 12: DRAM energy breakdown normalized to total DRAM energy consumed by
the baseline (left). System energy normalized to the baseline (right) for
different workload mixes.

First, Variable Burst Length ($VBL$) greatly reduces the $RD/WR$ energy by
51%, on average. Using $VBL$, the system retrieves only the required (and
predicted to be required) words of a cache block from the DRAM module. On
average, the number of bytes transferred between the memory controller and the
DRAM module is reduced by 55% (not shown) with Sectored DRAM compared to the
baseline. In this way, the system uses the power-hungry memory channel more
energy-efficiently, eliminating unnecessary data movement. Second, Sectored
Activation ($SA$) can reduce the energy spent on activating DRAM rows by 6% on
average. The reduction in $ACT$ energy is relatively small. This is because
the memory controller issues more $ACT$ commands compared to the baseline in
Sectored DRAM. The new $ACT$ commands (i) respond to the additional memory
requests caused by sector misses, and (ii) resolve the row conflicts that
occur due to interference created by the sector misses.

System energy consumption. Fig. 12 (right) shows the energy consumed by the
Sectored DRAM system (processor _and_ DRAM) normalized to the energy consumed
by the baseline system for all workloads. We observe that Sectored DRAM
reduces system energy consumption, on average (at maximum), by 14% (23%).
Sectored DRAM does so by (i) reducing DRAM energy consumption, and (ii)
reducing background power consumption by the processor as workloads execute
faster.

###  7.5 Area Overhead

Modeled DRAM chip. We use CACTI [84] to model the area of a DRAM chip (Table
3) using $22nm$ technology. Our model is open source [107]. Our modeled DRAM
chip takes up, in each bank: (i) $8.3\text{\,}{\mathrm{mm}}^{2}$ for DRAM
cells, (ii) $3.2\text{\,}{\mathrm{mm}}^{2}$ for wordline drivers, (iii)
$4.6\text{\,}{\mathrm{mm}}^{2}$ for sense amplifiers, (iv)
$0.1\text{\,}{\mathrm{mm}}^{2}$ for row decoder, (v)
$<$$0.1\text{\,}{\mathrm{mm}}^{2}$ for column decoder, and (vi)
$<$$0.4\text{\,}{\mathrm{mm}}^{2}$ for data and address bus.

Sectored DRAM. We model the overhead of (i) 8 additional LWD stripes, (ii)
sector transistors, (iii) sector latches, and (iv) wires that propagate sector
bits from sector latches to sector transistors to implement Sectored
Activation (section 4.1). Sectored DRAM introduces $2.26\%$ area overhead
(0.39 $mm^{2}$) over the baseline DRAM bank. Overall, Sectored DRAM increases
the area of the chip (16 banks and I/O circuitry) by _only_ $1.72\%$.

FGA [18, 124] and PRA [68]. We estimate the area overhead of these
architectures to be the same as Sectored DRAM because they require the same
set of modifications to the DRAM array to enable Fine-DRAM-Act.

HalfDRAM [136] and HalfPage [30]. We estimate the chip area overheads of
HalfDRAM and HalfPage as 2.6% and 5.2%, respectively. Both HalfDRAM and
HalfPage require 8 additional LWD stripes like Sectored DRAM does. HalfDRAM
further requires implementing double the number of CSL signals [136] to enable
mirrored connection, and HalfPage requires doubling the number of HFFs per mat
[30].

Processor. R3min/3We use CACTI to model the storage overhead of sector bits in
caches (1 byte/cache block) and the sector predictor (1088 bytes/core). The
sector bits (200 KiB additional storage for a system with 12.5 MiB cumulative
L1, L2, and L3 cache capacity) and the predictor storage increase the area of
the 8-core processor by $1.22\%$.

##  8 Discussion

###  8.1 Sectored DRAM with More Memory Channels

R4/1aWe evaluate 2- and 4-channel systems to study Sectored DRAM’s impact on
memory performance in systems equipped with more than one memory channel. Fig.
13 shows the normalized parallel speedup of all high, medium, and low LLC MPKI
homogeneous workloads for varying numbers of cores on the x-axis. Different
boxes show Baseline and Sectored DRAM configurations with 1, 2, and 4 memory
channels.

R4/1fig

Figure 13: Normalized parallel speedup of all low, medium, and high LLC MPKI
homogeneous workloads for varying number of cores11

R4/1bWe observe that more memory channels increase system performance on
average across all workloads for Baseline and Sectored DRAM. For example, for
HIGH MPKI 16-core workloads Sectored DRAM provides 2.74$\times{}$,
5.09$\times{}$, and 8.94$\times{}$ average normalized parallel speedup for
1-channel, 2-channel, and 4-channel systems, respectively.

###  8.2 Non-Memory-Intensive Workloads

Sectored DRAM’s current system integration can lead to varying performance
benefits depending on the workload’s memory intensity. We propose two
approaches to overcome the performance degradation in non-memory-intensive
workloads.

Dynamically turning Sectored DRAM off. Sectored DRAM can be turned off while
the system executes non-memory-intensive (i.e., low and medium MPKI workloads)
workloads. To do so, we leverage the performance counters already present in
modern processors [39, 6, 40] to periodically compute the average occupancy of
the memory controller’s read request queue (i.e., the average number of
requests in the read request queue) and turn Sectored DRAM on/off when the
computed value exceeds an empirically determined threshold. We (i)
periodically (every 1000 cycles) compute the average occupancy of the memory
controller’s read request queue, and (ii) turn Sectored DRAM on for the next
1000 cycles if the average occupancy exceeds $30$ or turn Sectored DRAM off
otherwise. Fig. 14 shows the weighted speedup for 16 workload mixes from each
memory intensity category, normalized to the coarse-grained DRAM baseline. We
show results for two configurations: _Always ON_ never turns Sectored DRAM off
and _Dynamic_ turns Sectored DRAM on and off as described above.

Figure 14: Weighted speedup for _Always ON_ and _Dynamic_

We observe that the _Dynamic_ configuration allows Sectored DRAM to perform as
well as the baseline for non-memory-intensity workloads and maintain better
performance than the baseline for memory-intensive workloads. _Dynamic_
provides higher speedups than _Always ON_ , on average across all workload
mixes and classes, even though _Dynamic_ provides slightly lower speedups than
_Always ON_ for high memory-intensive workloads.

Better sector prediction. Improving the SP’s accuracy would reduce the
additional LLC misses. A more sophisticated SP could be developed by tracking
the access patterns of instructions with deeper history, or other techniques
(e.g., reinforcement learning [9, 41], perceptron-based prediction [47, 48,
46, 123, 49, 28, 8]) could be used to predict the useful words.

###  8.3 Sectored DRAM with Prefetching

We implement Sectored DRAM support in a simple region-based single-stride
prefetcher (based on [37, 117]) to demonstrate Sectored DRAM’s performance in
a system with prefetching enabled. We model two new system configurations
_Baseline-Prefetch_ and _Sectored DRAM -Prefetch_. Baseline-Prefetch
incorporates the simple prefetcher that partitions physical memory address
space into 4-KiB (i.e., page-sized) regions and assigns a _stream_ to each
region. A region is _trained_ after four consecutive memory accesses with the
same stride, and the prefetcher starts issuing prefetch requests for
subsequent last-level cache (LLC) accesses (hits and misses) that target the
memory region. We configure the prefetcher to have a degree of four, and the
first prefetch request targets four cache blocks ahead of the memory request
that accesses the LLC. Sectored DRAM-Prefetcher augments this prefetcher with
support for sector bits. Sectored DRAM-Prefetcher sets the sector bits of a
prefetch request based on the sector bits of the memory request that resulted
in the prefetch request (i.e., hit or missed in the LLC). For example, if a
memory request asks for the first three sectors of a cache line, the prefetch
request also asks for the first three sectors of their respective cache lines.

Fig. 15 shows the normalized speedup (x-axis) for Baseline and Sectored DRAM
(with and without prefetching) across all evaluated single-core workloads.

Figure 15: Normalized speedup (x-axis) of all single-core workloads for
Baseline and Sectored DRAM11

We observe that Sectored DRAM-Prefetch improves system performance by 1.07%
(37.56%) on average (at maximum) compared to Sectored DRAM without
prefetching.141414Performance drop induced by the prefetcher can be curbed
using prefetch throttling techniques [24, 25, 23], e.g., Feedback Directed
Prefetching [117]. We conclude that the simple stride prefetcher design
improves Sectored DRAM’s performance. We leave the design and analysis of a
more sophisticated Sectored DRAM prefetcher for future work.

###  8.4 Finer-Granularity Sector Support

We design and evaluate Sectored DRAM with 8 sectors. Extending Sectored DRAM
to support more sectors could enable higher energy and performance benefits
but would require (i) transferring additional sector bits to DRAM from the
memory controller and (ii) more DRAM circuit area to place additional sector
latches.

Our implementation allows us to transfer up to 14 sector bits with each $PRE$
command to DRAM (section 4.1). To transfer more than 14 sector bits, (i) DRAM
command encoding could be extended with new signals to carry the sector bits
(e.g., another signal/pin for every additional sector bit), (ii) a new DRAM
command with enough space allocated in its encoding for sector bits could be
implemented, or (iii) sector bits for a single $SA$ operation could be
transferred to DRAM over multiple $PRE$ commands.

We evaluate the area required by additional sector latches and find it to be
very small. Implementing 8 more sector latches brings Sectored DRAM’s DRAM
chip area overhead from 1.72% to 1.78%.

###  8.5 DRAM Error Correcting Codes (ECC)

SECDED-ECC [83] used in today’s systems is naturally compatible with Sectored
DRAM. Some systems make use of more specialized, Chipkill-like ECC (e.g.,
single symbol error correction [5, 130, 17]). Sectored DRAM can easily support
the single symbol error correction (SSC [5, 130, 17]) scheme. In this scheme,
the ECC codeword consists of 32 4-bit data symbols and four 4-bit ECC symbols
with a total size of 144 bits. 128 data bits are encoded to form ECC symbols.
The DRAM module consists of 16 x4 chips to store data symbols and 2 x4 chips
to store ECC symbols. The module transmits 72 bits with each beat of the data
burst and an ECC codeword is transmitted over two beats of a data burst. To
support the SSC scheme, Sectored DRAM can use burst lengths that are multiples
of two, which allows the DRAM module to transmit whole ECC codewords with
every DRAM access.

R2/2Recent DRAM chips implement on-die ECC which allows the DRAM chip to
correct errors transparently from the memory controller [93, 94, 95]. Sectored
DRAM is compatible with on-die ECC schemes that operate at the granularity of
a single sector (e.g., 8 bits). To develop an on-die ECC scheme for Sectored
DRAM, existing on-die ECC schemes could be modified to operate at the
granularity of a single sector or new ECC schemes could be developed. We leave
such exploration for future work.

###  8.6 Sector Cache Benefits

R4/10We use sector caches to integrate Sectored DRAM into a full system. A
comprehensive design space exploration for sector caches is out of the scope
of this work (we refer the reader to [72, 112, 4, 36, 101, 50, 7, 103, 73, 62,
97]). Sector caches incur chip area costs but offer power and performance
benefits beyond those that we demonstrate in our work (using Sectored DRAM).
For example, powering off SRAM subarrays that contain invalid words in a cache
block could save power (e.g., [97]), or filling up these invalid words with
valid words from other cache blocks could increase effective cache capacity
and improve system performance (e.g., [62]).

##  9 Related Work

Sectored DRAM is the first low-cost and high-performance DRAM substrate that
alleviates the energy waste on the DRAM bus, by enabling (i) Fine-grained DRAM
data transfer (Fine-DRAM-Transfer) and (ii) Fine-grained DRAM row activation
(Fine-DRAM-Act). We extensively compare Sectored DRAM qualitatively and
quantitatively with the most relevant, low-cost, state-of-the-art fine-grained
DRAM architectures [18, 136, 68, 30, 124] in section 3.1 and section 7.4. In
this section, we discuss other related works.

Other Fine-Grained activation mechanisms. Prior works [135, 3, 116, 92, 15]
propose other fine-grained DRAM architectures. These architectures require
intrusive reorganization of the DRAM array and/or modifications to the DRAM
on-chip interconnect. Some works [15, 92, 116] target higher-bandwidth DRAM
standards and offer significant performance and activation energy
improvements. [135] develops a new interconnect that serializes data from
multiple partially activated banks. [3] divides DRAM mats into submats by
adding more helper flip-flops to mitigate the throughput loss of fine-grained
activation. These works do _not_ reduce the energy wasted on the memory
channel by avoiding the transfer of unused words, which Sectored DRAM does at
low chip area cost.

DRAM-module-level Fine-DRAM-Transfer. A class of prior work [131, 132, 2, 137,
11, 126] proposes new DRAM module designs (e.g., subranked DIMMs [2, 131, 132,
126]) that allow independent operation of each DRAM chip in a DRAM module
(section 2.1) in order to implement Fine-DRAM-Transfer. From a system
standpoint, Sectored DRAM is a more practical mechanism to implement compared
to module-level mechanisms because Sectored DRAM requires no modifications to
the physical DRAM interface. Similar to Sectored DRAM, these mechanisms (e.g.,
DGMS [132]) require modifications to DRAM (i.e., modifications to the DRAM
module in DGMS and to the DRAM chip in Sectored DRAM) and the processor.
However, on top of these modifications, module-level mechanisms also require
modifications to the physical DRAM interface (e.g., three additional pins to
select one of the eight chips in a rank [2]), thus making module-level
mechanisms incompatible with current industry standards (i.e., JEDEC
specifications [44]). In contrast, Sectored DRAM does _not_ require
modifications to the physical DRAM interface, and thus, Sectored DRAM chips
comply with existing DRAM industry standards and specifications.

We quantitatively evaluate a subranked DIMM design (DGMS [132]) that can be
implemented with minimal modifications to the physical DRAM interface. This
design can operate subranks independently and each subrank can receive one
DRAM command per DRAM command bus cycle (i.e., 1x ABUS scheme [131]). We find
that this design _reduces_ system performance for the high MPKI workload
mixes, causing a 23% reduction in weighted speedup on average. Even though the
subranked DIMM allows requests to be served from different subranks in
parallel, the DRAM command bus bandwidth is insufficient to allow timely
scheduling of these requests to different subranks [132] (i.e., the command
bus becomes the bottleneck). The DRAM command bus bandwidth can be increased
to enable higher-performance subranked DIMM designs. However, this comes at
additional hardware cost and modifications to the physical DRAM interface
[132]. In contrast, Sectored DRAM improves the weighted speedup for the same
set of workloads by 17% on average and requires no modifications to the
physical DRAM interface.

##  10 Conclusion

We designed a new, high-throughput, energy-efficient, and practical fine-
grained DRAM architecture, Sectored DRAM. Compared to prior fine-grained DRAM
architectures, our design significantly improves both system energy and
performance. It does so by eliminating (i) the energy waste caused by
transferring unused words between the processor and DRAM, and (ii) the energy
spent on activating DRAM cells that are not accessed by memory requests.
Activating a smaller number of cells allows the memory controller to serve
memory requests with lower memory access latency. While effective at improving
both system energy and performance, Sectored DRAM is also practical and can be
implemented at low hardware cost.

## Acknowledgements

We thank the anonymous reviewers of MICRO 2022, HPCA 2023, and TACO for their
feedback. We thank the SAFARI Research Group members for providing a
stimulating intellectual environment. We acknowledge the generous gifts from
our industrial partners; including Google, Huawei, Intel, and Microsoft. This
work is supported in part by the Semiconductor Research Corporation, the ETH
Future Computing Laboratory, and the AI Chip Center for Emerging Smart Systems
(ACCESS).

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