# Performance Investigation of p-FETs Based on Highly Air-stable Mono-layer
Pentagonal PdSe2

Keshari Nandan, Amit Agarwal, Somnath Bhowmick, and Yogesh S. Chauhan This
work was partially supported by the Humboldt Foundation and the Swarnajayanti
Fellowship (Grant No. – DST/SJF/ETA-02/2017-18) of the Department of Science
and Technology (DST), Government of India.K. Nandan and Y. S. Chauhan are with
the NanoLab, Department of Electrical Engineering, Indian Institute of
Technology Kanpur, India, 208016, e-mail<EMAIL_ADDRESS><EMAIL_ADDRESS>Agarwal is with the Department of Physics, Indian
Institute of Technology Kanpur, India.S. Bhowmick is with the Department of
Material Science and Engineering, Indian Institute of Technology Kanpur,
India.

###### Abstract

Pentagonal PdSe2 is a promising candidate for layered electronic devices,
owing to its high air-stability and anisotropic transport properties. Here, we
investigate the performance of p-type FET based on PdSe2 mono-layer using
multi-scale simulation framework combining Density functional theory and
quantum transport. We find that mono-layer PdSe2 devices show excellent
switching characteristics ($<$ 65 mV/decade) for the source-drain direction
aligned along both [010] and [100] directions. Both directions also show good
on-state current and large transconductance, though these are larger along the
[010] direction for a 15 nm channel device. The channel length scaling study
of these p-FETs indicates that channel length can be easily scaled down to 7
nm without any significance compromise in the performance. Going below 7 nm,
we find that there is a severe degradation in the sub-threshold swing for 4 nm
channel length. However, this degradation can be minimized by introducing an
underlap structure. The length of underlap is determined by the trade-off
between on-state current and the switching performance.

###### Index Terms:

Field-effect transistors (FETs), Density functional Theory (DFT), Maximally-
localised Wannier functions (MLWFs), Non-equilibrium Greens function (NEGF),
Quantum Transport (QT).

##  I Introduction

The demonstration of mono-layer molybdenum disulfide ($\rm MoS_{2}$) based FET
by Radisavljevic $\it{et~{}al.}$ [1] in 2011 opened up the field for
exploration of layered materials’ based FETs for future technology nodes.
Since then, there has been remarkable progress on the synthesis of layered
materials and devices based on them. Both the material and device communities
are actively exploring novel 2D materials[2] and device concepts based on
them. Several promising devices viz. two-dimensional electrostrictive field-
effect transistor (2D-EFET)[3], Dirac-source FET (DS-FET) [4], and dual
transport FET (DT-FET)[5] have been demonstrated employing these materials
properties, in the last five years.

Beyond $\rm MoS_{2}$ [6, 7, 8], several other layered materials have been
explored for device applications. Most of them are isotropic, but some of them
show interesting anisotropic behavior. The isotropic/anisotropic property is a
consequence of high/low lattice symmetry. The anisotropic materials, with
hexagonal buckled or puckered structure such as phosphorene[9, 10, 11, 12],
silicene[13, 14], arsenene[15, 16], germanene[17, 18], and stanene[19], have
great potential for device application, but their realization in a stable form
is still a great challenge. Stability is one of the most important parameters
for a material to be considered for electronic applications and large-scale
production.

Motivated by this, we study the electronic properties and device
characteristics of mono-layer PdSe2 based devices. It is another low symmetric
material that has no soft modes in their mono- and few- layers’ phonon
spectrum[20, 21]. Experimentally, it has been shown that the air-stability of
pentagonal-PdSe2 is higher ($>$ 60 days) than other puckered and buckled
layered materials[20]. The experimental band gap value is
$1.3\text{\,}\mathrm{eV}$ for this mono-layer. This band gap value indicates
an excellent semiconductor that can absorb light for electronic and
optoelectronic devices. This value is not far from silicon, and it is
satisfactory for logic switches to sharply discriminate between two logic
states. Till now, only few-layer pentagonal-PdSe2 based FETs have been
demonstrated[20, 22], and, hence the performance for mono-layer is unknown.
Mono-layer of pentagonal PdSe2 has better electrical transport properties for
holes than electrons[21]. Hence, We have chosen to study p-type FET.

In contrast to conventional materials (bulk Si/Ge, III-V), for new materials,
the device simulation becomes more challenging as their characterization
parameters are not known. Thus, we start from first-principles calculations of
the electronic properties and use these to construct tight-binding (TB)
Hamiltonian within maximally-localised Wannier functions (MLWFs) basis. Our
device simulations are based on the effective TB model[23, 24, 25, 26, 27,
28], which makes them computationally more efficient, compared to first-
principles based device simulation approaches. Our device simulations reveal
the following:

  1. 1.

The best performance of our devices meets the high-performance (HP) expections
of International Technology Roadmap for Semiconductors (ITRS) 2013 for the
year 2028.

  2. 2.

The best performance of our device for low power (LP) fulfils $\sim$ 51%
requirement of ON current mentioned in ITRS 2013 roadmap for the year 2028.

  3. 3.

Our device’s best performance is better than Si FinFET (see Table III).

This paper is organized as follows: The methodology is described in section
II. Results and discussion on electronic structures and device performance are
presented in section III, and the conclusive remarks are given in section IV.

##  II Methodology

Figure 1 shows the simulation methodology used in this work and this
methodology is described as follows:

###  II-A Electronic Structure Calculations

We use Quantum Espresso (QE) [29, 30], a Density-functional theory (DFT) based
tool, for electronic structure calculations from first-principles. The
Projector Augmented Wave method (PAW) [31, 32] with a plane wave basis set is
used for the DFT calculations. The exchange correlation effect are
approximated by the generalized gradient approximation (GGA) within the
Perdew-Burke-Ernzerhof (PBE) formulation [33]. The energy cutoffs for wave-
functions and charge-density are set to $\rm 60~{}Ry$ and $\rm 600~{}Ry$,
respectively. The Brillouin zone is sampled using $10\times 10\times 1$
Monkhorst-Pack grids [34]. A $\rm 30~{}\AA$ thick vacuum layer is used in
simulations to avoid the interaction between spurious neighboring layers in
the out of plane direction. The primitive unit cell structure is optimized
until all components of forces are less than $\rm 10^{-3}$ Ry/a.u..

Figure 1: Methodology: Schematic of simulation flow (from DFT to QT). It
starts with solving the Kohn-Sham equation for a relaxed and periodic system,
followed by Wannier transformation and device simulation. Figure 2: Geometric
and Electronic Structures : (a) Top view, (b) side view in x-z plane, and (c)
side view in y-z plane of pentagonal PdSe2. The Crystallographic directions
[100] and [010] are equivalent to X and Y directions of Cartesian coordinate
system. The black and blue balls represent Pd and Se atoms, respectively. The
dotted red color rectangle in (a) is primitive unit cell of the system. (d)
Comparison of energy bands calculated from DFT and tight binding Hamiltonian
(in MLWF basis) along high symmetry paths ($\rm\Gamma$-$\rm X$-$\rm S$-$\rm
Y$-$\rm\Gamma$) in Brillouin zone for mono-layer of pentagonal-PdSe2. VBM is
shifted to zero energy. (e) Contour plot of the highest valance band. High
symmetry points and transport directions are also indicated in (e).

###  II-B Maximally-localised Wannier Functions (MLWFs) Tight-Binding
Hamiltonian

First-principles calculations provide the electronic structure in terms of
Bloch states. The Bloch states corresponding to conduction and valance bands,
which lie near the band gap, are mapped to MLWFs using the Wannier90 suite of
codes[35] in continuous space of unitary matrices[36, 37, 38]. Five d-orbitals
and three p-orbitals of each Pd and each Se atom are used to generate an
initial guess for mapping of Bloch states, to capture eighteen highest valance
bands and four lowest conduction bands. Once the Wannier functions (WFs) are
known, the on-site energy and hopping parameters are calculated to generate
the elements of Hamiltonian matrix ($H_{ijk}^{mn}$). The $H_{ijk}^{mn}$
couples $\rm m^{th}$ Wannier function in the home unit cell (0, 0, 0) to the
$\rm n^{th}$ Wannier function in the unit cell (i, j, k). Using unit cell
coupling terms, we construct the device Hamiltonian, which is given as input
to the NEGF solver.

###  II-C Device Simulations

At each bias point ($V_{GS}$, $V_{DS}$), Non-equilibrium Green’s functions
(NEGF) and Poisson equation are solved self-consistently to obtain the
converged values of charge, potential, and transmission coefficient for the
device. In this formalism, transmission coefficient can be expressed as,

$\displaystyle
T(E,k,V_{GS},V_{DS})=Trace[\Gamma_{L}(E,k,V_{GS},V_{DS})G^{R}(E,k,$
$\displaystyle
V_{GS},V_{DS})\Gamma_{R}(E,k,V_{GS},V_{DS})G^{A}(E,k,V_{GS},V_{DS})]~{}.$ (1)

Here, $G^{R}$ and $G^{A}=[G^{R}]^{\dagger}$ are retarded and advance Green
functions, respectively.
$\Gamma_{L/R}(=i[\Sigma_{L/R}-\Sigma^{\dagger}_{L/R}]$) is the broadening from
left/right contacts. $\Sigma_{L/R}$ is the left/right contact self-energy
matrix. k is the wave-vector in transverse (channel width) direction.

The current is calculated using the Landauer-$\rm B\ddot{u}ttiker$
approach[39]. The source to darin current ($I_{SD}$) for a given bias
($V_{GS}$, $V_{DS}$) can be expressed as,

$\displaystyle
I_{SD}(V_{GS},V_{DS})=\frac{2q}{h}\int_{-\infty}^{\infty}\sum_{k}T(E,k,V_{GS},V_{DS})$
$\displaystyle[f(E-\mu_{D})-f(E-\mu_{S})]dE~{},$ (2)

Equation. 2 can also be written as,

$\displaystyle
I_{SD}(V_{GS},V_{DS})=\int_{-\infty}^{\infty}I_{SD}(E,V_{GS},V_{DS})dE~{},$

where, $V_{GS}$ and $V_{DS}$ are gate to source and drain to source voltages,
respectively. $q$ is the elementry charge, $h$ is the Planck constant,
$T(E,V_{GS},V_{DS})=\sum_{k}T(E,k,V_{GS},V_{DS})$ is the transmission
coefficient at Energy $E$ for a given bias ($V_{GS}$, $V_{DS}$), $\mu_{S/D}$
is the chemical potential at source/drain, and $f(E-\mu_{S/D})$ is the Fermi-
Dirac distribution function at source/drain.
The $I_{SD}$ has three components, namely thermionic ($I_{thermal}$), source-
to-drain tunneling ($I_{SDT}$) and BTBT ($I_{BTBT}$) currents. These
components shown in Fig. 3 (b), can be expressed as,

$\displaystyle
I_{thermal}(V_{GS},V_{DS})=\int_{-\infty}^{E_{V_{min},Ch}}I_{SD}(E,V_{GS},V_{DS})dE~{},$
(3a) $\displaystyle
I_{SDT}(V_{GS},V_{DS})=\int_{E_{V_{{min}},Ch}}^{E_{V,source}}I_{SD}(E,V_{GS},V_{DS})dE~{},$
(3b) $\displaystyle
I_{BTBT}(V_{GS},V_{DS})=\int_{E_{V,source}}^{\infty}I_{SD}(E,V_{GS},V_{DS})dE~{},$
(3c)

Here, $E_{V_{min},Ch}$ and $E_{V,source}$ are the minimum valance band energy
level in the channel and valance band energy level in the source.
$I_{SD}(E,V_{GS},V_{DS})$ is current value at energy E for given bias
$(V_{GS},V_{DS})$.

We use Poisson and NEGF modules implemented in NanoTCAD ViDES suites of
codes[26]. Periodic boundary conditions in the transverse direction are
considered using 30 uniform wave vector points. Transport is assumed to be
ballistic in nature due to short channel length used in this work. All
transport simulations are performed at room temperature ($T=300~{}K$).

##  III Results

###  III-A Geometric and Electronic Structures

Figure 2 (a) shows the top view and (b) and (c) show side view along two
different lateral directions of pentagonal PdSe2 mono-layer. The mono-layer of
pentagonal-PdSe2 is buckled type and belongs to the space group $P2_{1}/c$.
This mono-layer is a net of pentagonal networks, and each network consists of
two Pd and three Se atoms (see Fig. 2 (a)). We start with the experimental
bulk structure having lattice parameters a = 5.741 Å, b = 5.886 Å, and c =
7.691 Å. Then, we take out mono-layer structure from bulk and optimize it with
30 Å thick vacuum layer in the $\rm|z|$-direction. Comparison of optimized
lattice constants (a and b) and bond lengths ($\rm d_{Pd-Se}$ and $\rm d_{Se-
Se}$) with earlier works is shown in Table I. It’s clear from Table I that our
values are consistent with earlier results[40, 21, 41, 42, 20].

Figure 2 (d) shows the electronic band structure of monolayer pentagonal-PdSe2
from DFT (navy blue line) and TB (hollow green circle) along the high symmetry
path ($\Gamma$-$\rm X$-$\rm S$-$\rm Y$-$\Gamma$). The red and black color
circles in Fig. 2 (d) indicate the location of conduction band minima (CBM)
and valance band maxima (VBM), respectively. The band gap value is 1.35 eV
(indirect) and is very close to experimental value ($\rm E_{G,exp}\sim 1.3\pm
0.2eV$)[20]. The band structure from TB shows good agreement with DFT in the
vicinity of VBM. The VBM lies on the way from $\Gamma$ to $\rm X$, hence the
valley degeneracy is two. Figure 2 (e) shows the contour plot of the highest
valance band. In the plot, symbols and black lines indicate the high symmetry
points ($\Gamma$, $\rm X$, $\rm S$, $\rm Y$) and transport directions ([100]
($\Gamma$-$\rm X$) and [010] ($\Gamma$-$\rm Y$)), respectively.

Figure 3: Device Structure and Current Components: (a) Schematic of the device under investigation. $\rm L_{Ch}$ and $\rm L_{S/D}$ are channel length and source/drain extension. $\rm L_{G}$ is gate length. UL is underlap length. $\rm t_{ox}$ is thickness of top and bottom gate oxide. (b) The schematic of p-MOSFET band diagram in the OFF state for two different conditions of $\rm E_{G}$ ($\rm E_{V}$ is taken as reference): i) if $\rm E_{G}<V_{DD}+V_{T}$ (solid black line represents $\rm E_{C}$) and ii) if $\rm E_{G}>V_{DD}+V_{T}$ (dashed black line represent $\rm E_{C}$). The red, violet, and green arrows indicate the path for thermionic, SDT, and BTBT, respectively. A large $\rm E_{G}$ in this material ensures the condition $\rm E_{G}>V_{DD}+V_{T}$. Hence, BTBT is negligible in our devices. TABLE I: The optimized lattice constants (a and b) and bond lengths between Pd-Se and Se-Se for mono-layer pentagonal PdSe2.  lightgray Work | a (Å), b (Å) |  $\rm d_{Pd-Se}$ (Å), $\rm d_{Se-Se}$ (Å)
---|---|---
This work | 5.748, 5.923 | (2.457, 2.469), 2.420
Soulard et al. [40] (Exp.) | 5.7457, 5.8679 | —-
Lan et al. [21] | 5.74, 5.91 | (2.45, 2.46), 2.41
Deng et al. [41] | 5.749, 5.495 | —-
Qin et al. [42] | 5.7538, 5.9257 | —-
Oyedele et al. [20] | 5.72, 5.93 | —-

###  III-B Electrical Characteristics and Performance Metrics

Figure 3 (a) shows the schematic of the device. The device is a double gate
(DG) MOSFET. The gate oxide is SiO2, and the thicknesses of top and bottom
gate oxides are the same. The channel material is pentagonal-PdSe2. The
source/drain is highly doped with p-type doping density of $2\times
10^{17}~{}m^{-2}$. $\rm L_{Ch}$, $\rm L_{G}$, $\rm t_{ox}$, $\rm L_{S/D}$ and
$\rm UL$, which are geometrical parameters of the device, represent channel
length, gate length, oxide thickness, source/drain extension, and underlap
length, respectively.

Figure 4: Transfer Characteristics: $I_{SD}$ vs $V_{GS}$ of FET for transport
direction (a) [100] and (b) [010] with $\rm L_{Ch}$ $\sim$ 15.50 nm. The UL
length and EOT are 0.0 nm and 0.6 nm, respectively. The power supply voltage
($\rm V_{DD}$) is 0.5V. (c) ON current ($\rm I_{ON}$) vs ON-OFF ratio ($\rm
I_{ON}/I_{OFF}$).  TABLE II: Performance comparison of mono-layer pentagonal
$\rm PdSe_{2}^{**}$ p-FETs against International Roadmap for Devices and
Systems (IRDS) $\rm 2020^{*}$[43] requirements for the year 2034.

lightgray | $\rm L_{G}$ | Transport | UL |  | $\rm I_{ON}$ | $\rm I_{OFF}$
---|---|---|---|---|---|---
lightgray | (nm) | direction | (nm) | mV/decade | (A/m) | (A/m)
|  $\sim$ 15.50 | [100] | 0.00 | 61 | 618 | $10^{-1}$
|  $\sim$ 15.50 | [100] | 0.00 | 61 | 463 | $10^{-2}$
|  $\sim$ 15.50 | [100] | 0.00 | 61 | 176 | $10^{-4}$
|  $\sim$ 15.50 | [010] | 0.00 | 63 | 1205 | $10^{-1}$
|  $\sim$ 15.50 | [010] | 0.00 | 63 | 883 | $10^{-2}$
|  $\sim$ 15.50 | [010] | 0.00 | 63 | 348 | $10^{-4}$
Y-2034 |  |  |  |  |  |
HP | 12 | - | - | 70 | 1504 | $10^{-2}$
LP | 12 | - | - | 65 | 861 | $10^{-4}$

*$\rm V_{DD}$ = 0.55 V; **$\rm V_{DD}$ = 0.50 V, EOT = 0.60 nm, and $\rm L_{S/D}$=10 nm.

####  III-B1 Transfer Characteristics and the On Current

Figure 4 (a) and (b) show the transfer characteristics of the device for
channel with transport directions along [100] and [010] axes. The channel
length is 15.50 nm without underlap (i.e., $\rm L_{Ch}=L_{G}$), the supply
voltage ($\rm V_{DD}$) is 0.50 V, and the source/drain extension region ($\rm
L_{S/D}$) is 10 nm. For this channel length, source-to-drain tunneling (SDT)
is negligible. The band-to-band tunneling (BTBT) is also negligible due to
large band gap of this material. Figure 4 (c) shows the ON current ($\rm
I_{ON}$) vs. ON/OFF ratio ($\rm I_{ON}/I_{OFF}$) for both transport
directions. $\rm I_{ON}$ is one of the important metrics for logic switches,
because the maximum operating speed is proportional to $\rm I_{ON}$. For $\rm
I_{ON}/I_{OFF}$ $\sim$ $10^{4}$ ($10^{5}$), ON current for [010] direction
$\rm I_{ON-[010]}$ ($\sim$ $1.38\times 10^{3}A/m$ ($1.14\times 10^{3}A/m$)) is
approximately double than ON current for [100] direction $\rm I_{ON-[100]}$
($\sim$ $6.86\times 10^{2}A/m$ ($5.23\times 10^{2}A/m$)). The reason for
higher ON current in the [010] direction compared to the [100] direction is
smaller effective mass in the [010] direction, ($m_{[010]}^{*}\sim 0.25m_{o}$)
than [100] ($m_{[100]}^{*}\sim 0.40m_{o}$).

We benchmark the performance of mono-layer pentagonal PdSe2 p-FETs against
International Roadmap for Devices and Systems (IRDS) $\rm 2020$[43]
requirements for the year 2034 in Table II. According to the IRDS roadmap,
option for the logic device is lateral gate-all-around (LGAA)-3D for the year
2034. The [010] ([100]) transport direction based p-FETs meets $\sim$ 41%
(21%) and $\sim$ 60% (31%) requirement of ON current expected in IRDS roadmap
for LP and HP applications, respectively.

####  III-B2 Channel Length Scaling

Now, we scale the channel length to study the impact of SDT on the device
performance. The SDT decides the limit of gate length scaling[44] and plays a
significant role in determining the subthreshold slope (SS) and, hence OFF
current ($\rm I_{OFF}$) at short channel length. Figure 5 (a) and (b) show the
transfer characteristics for different channel lengths with transport
directions along [100] and [010]. The EOT, UL, and $\rm V_{DD}$ are 0.60 nm,
0.0 nm, and 0.50 V, respectively. The effect of SDT is more prominent for
[010] transport direction than [100], because tunneling probability from
source to drain is proportional to $exp{(-\sqrt{m^{*}})}$ [45] and
$m_{[010]}^{*}<m_{[100]}^{*}$. Figure 5 (c) and (d) show the energy resolved
current spectrum and valance band for $\rm L_{Ch}$ = 15.50 and 3.70 nm,
channel with transport direction [010] for ($V_{DS}$, $V_{GS}$) = (0.50, 0.30)
V, which clearly indicate that $I_{SDT}$ majorly contributes to $I_{SD}$ for
$\rm L_{Ch}$ = 3.70 nm. We plot the contribution percentage of $I_{SDT}$ to
$I_{total}$ vs. $\rm L_{Ch}$ at $V_{GS}$ = 0.3 and 0.0 V in Fig. 5 (e) and 5
(f). For short channel lengths ($\sim$ 1.5 and 4.0 nm), the contribution of
$I_{SDT}$ is $\sim$ 100% to $I_{total}$ (i.e., $I_{total}$ $\simeq$ $I_{SDT}$)
for both transport directions at $V_{GS}$ = 0.30 V. But, for $V_{GS}$ = 0.00 V
and $\rm L_{Ch}$ $\sim$ 4 nm, it decreases to $\sim$ 30% and $\sim$ 75% for
tansport directions [100] and [010], respectively. For $\rm L_{Ch}$ $>$ 10 nm,
the contribution is $\sim$ 0% (i.e., $I_{total}$ $\simeq$ $I_{thermal}$) for
both transport directions at $V_{GS}$ = 0.0 V and 0.3 V. For $V_{GS}$ = 0.3 V
and $\rm L_{Ch}$ $\sim$ 7 nm, it is $\sim$ 1% and 2.5% for transport
directions [100] and [010], respectively. Whereas, for $V_{GS}$ = 0.0 V and
$\rm L_{Ch}$ $\sim$ 7 nm, the contribution is 0% for both transport
directions. Figure 6 (a) shows the thermionic part of total current and total
current vs. $V_{GS}$ for transport direction [010] and $\rm L_{Ch}$ = 3.70 nm.
The contribution percentage of $I_{SDT}$ to $I_{total}$ and $I_{thermal}$ to
$I_{total}$ vs. $V_{GS}$ for transport directions [010] and [100] are shown in
Fig. 6 (b) and (c), respectively.

Figure 5: Channel Length Scaling: Transfer characteristics for different
values of $\rm L_{Ch}$ (down to $\sim$ 1.5 nm) for transport directions (a)
[100] and (b) [010]. Energy resolved current spectrum for (c) $\rm L_{Ch}$ =
15.50 nm and (d) $\rm L_{Ch}$ = 3.70 nm for transport direction [010]. The
contribution percentage of $I_{SDT}$ to $I_{total}$ (= $I_{SDT}+I_{thermal}$)
vs $\rm L_{Ch}$ for transport directions (e) [100] and (f) [010]. Insets in
(e) and (f) show the contribution percentage for 5 nm $\rm<~{}L_{Ch}~{}<$15.50
nm. Figure 6: (a) $I_{thermal}$ and $I_{SDT}$ vs. $V_{GS}$, (b) and (c)
contribution percentage of $I_{SDT}$ and $I_{thermal}$ to $I_{total}$ vs.
$V_{GS}$ for transport direction [100] and [010], respectively.

The benchmarking of [010] transport direction (because this transport
direction gives best performance) based p-FETs against ITRS 2013 requirements
for the year 2028 is shown in Fig. 9. For LP applications, the OFF state
current is not meeting expected ITRS requirements. For HP applications, our
device shows 15% more ON current than expected in ITRS roadmap. Our
simulations provide an upper-performance limit, as the transport is assumed to
be ballistic in nature. However, the effect of phonon-scattering is very weak
for short-channel devices. For $\sim$ 10 nm channel length, at least $\sim$
80% ballisticity has been shown for $\rm MoS_{2}$[46] and BP[47] based FETs.
In fact, $>$ 90 % ballisticity is reported for channel length below 5 nm[46].

Figure 7: Gate Control Parameters : (a) SS vs $\rm L_{Ch}$. (b) Peak
transconductance vs EOT. (c) SS vs EOT.

####  III-B3 Gate Control

In addition to $\rm I_{ON}$, SS and $g_{m}$ are crucial figures of merit for
device performance. They reveal the gate control in the sub-threshold and
above-threshold region. Smaller value of SS indicates better gate control.

Figure 8: Underlap Scaling : Transfer characteristics for transport directions
(a) [100] for $\rm L_{G}$ = 4.20 nm and (b) [010] for $\rm L_{G}$ = 3.70 nm
for different UL lengths. (c) SS vs. UL length for the same $\rm L_{G}$ in (a)
and (b). (d) Valance band diagram of device for transport direction [100] for
different UL lengths. The contribution percentage of $I_{SDT}$ to $I_{total}$
vs UL lengths for transport directions (e) [100] and (f) [010]. EOT = 0.60 nm,
$\rm V_{DD}$ = 0.50 V.

Figure 7 (a) shows that variation of SS with $\rm L_{Ch}$. The SS degradation
in transport direction [010] is more prominent than [100]. The excellent
switching characteristics (SS $<$ 70 mv/decade) are seen in both transport
directions for $\rm L_{Ch}$ $>$ 7 nm. For $\rm L_{Ch}<7~{}nm$, SDT plays a
significant role in deciding OFF-current and SS (see Table II, Fig. 7 (a), 5
(e), and 5 (f)).

The variation of gate control parameters peak of $g_{m}$ and SS with EOT are
shown in Fig. 7 (b) and (c). The $g_{m}$ is given by,

$\begin{split}g_{m}&=\frac{\partial I_{DS}}{\partial V_{GS}},\\\ \end{split}$
(4)

and, hence

$\begin{split}g_{m}&\propto v_{h}\frac{\partial Q_{Ch}}{\partial V_{GS}}.\\\
\end{split}$ (5)

The density of states (D(E)) determines $\partial Q_{Ch}/\partial V_{GS}$ and
is given by,

$\displaystyle D(E)$
$\displaystyle=\frac{g_{s}g_{v}m_{o}}{2\pi\hbar^{2}}\sqrt{m_{[100]}^{*}m_{[010]}^{*}}$
(6)

where, $g_{s}$ and $g_{v}$ are spin and valley degeneracy. $Q_{Ch}$ is channel
charge and $v_{h}$ is carrier velocity.
We find that both control parameters degrade almost linearly with EOT. The
$g_{m}$ is higher for the [010] direction because small variation in $V_{GS}$
leads to same amount of change in channel charge (as D(E) is independent of
channel orientation) for both transport directions and carrier velocity is
more in [010] than [100] direction. In this work, we consider the gate as an
ideal insulated electrode, but thin gate oxide leads to gate leakage current
and hence, insulator thickness has a limit.

####  III-B4 Underlap Scaling

The tunneling width and the barrier height play vital roles in reducing the
SDT at short channel length, which in turns leads to weaker gate control. Gate
underlap[48] structures overcome these shortcomings by increasing the
effective channel length and consequently the tunneling width and the barrier
height. But, a large underlap region can degrade the device performance,
because the gate has better control underneath gate length region in channel
compared to the UL region. Therefore, the UL length has to be optimized.
Figure 8 (a) and (b) show the transfer characteristics for different UL
lengths for $\rm L_{G}\sim$ 4 nm for channel orientation along [100] and [010]
directions. The SS vs UL length is plotted in Fig. 8 (c) to see the effect of
UL length on gate control in sub-threshold region.

Figure 9: Performance comparison of mono-layer pentagonal $\rm PdSe_{2}^{**}$
p-FETs against $\rm ITRS~{}2013^{*}$[49] requirements for the year 2028.

*$\rm V_{DD}$ = 0.64 V, EOT = 0.41 nm; **$\rm V_{DD}$ = 0.50 V, EOT = 0.60 nm, and $\rm L_{S/D}$=10 nm; ***$\rm I_{OFF}$ requirement can not be reached.

The impact of SDT in transport direction [100] is lower than in [010] and
hence, in [100] channel, when UL length is increased from 0.0 to 1.15 nm, the
contribution percentage of $I_{SDT}$ to $I_{total}$ reduces from $\sim$ 100%
to 30% for $V_{GS}$ = 0.3 V and 30% to 6% for $V_{GS}$ = 0.0 V (see Figure 8
(e)), which in turn reduces the SS from $\sim$ 78 to 66 mV/decade ($\rm
I_{ON}$ drops by $\sim$ 30%). However, in [010] channel, when UL is increased
from 0.0 to 2.4 nm, the contribution percentage of $I_{SDT}$ to $I_{total}$
for $V_{GS}$ = 0.3 V reduces from $\sim$ 100% to 30% and for $V_{GS}$ = 0.0 V,
30% to 4% (see Figure 8 (f)), which in turn reduces the SS from $\sim$ 103 to
66 mV/decade ($\rm I_{ON}$ drops by $\sim$ 83%).

Figure 9 shows the benchmarking of p-FETs ($\rm L_{G}\sim 4nm$ and [010]
transport direction) against ITRS 2013 requirements. For LP applications: (i)
without underlap, the OFF state current is not meeting expected ITRS
requirements, (ii) introduction of underlap structure with UL = 0.60 nm and
1.20 nm meet $\sim$ 13% and 51% requirement of on current expected in ITRS
roadmap, respectively, and (iii) further increasing the UL leads to decrease
in on current. For HP applications, UL = 0.60 nm, 1.20 nm, and 2.40 nm meet
$\sim$ 90%, 55%, and 20% requirement of ON current expected in ITRS roadmap.

##  IV conclusion

We have studied the electronic structure and device characteristics of p-FETs
based on mono-layers of pentagonal PdSe2. We explicitly calculate the TB
parameters of mono-layer PdSe2 in the MLWF basis. Using these TB parameters we
solve the coupled Poisson and Schr$\rm\ddot{o}$dinger equations, via recursive
non-equilibrium Green’s function formulation. We found that: (1) p-FETs show
anisotropic transport behavior, (2) [010] oriented channel gives superior on-
state performance than [100] oriented channel almost double ON current and
$g_{m}$, (3) $\rm I_{ON}$ ($>10^{3}$ A/m) is higher for transport direction
[010] for $\rm I_{ON}/I_{OFF}$ $\sim$ $10^{4}$ and $10^{5}$, (4) Both
transport directions show the sub-threshold slope less than 65 mV/decade, (5)
the impact of SDT is more pronounced for the [010] oriented channel than [100]
for very short channel length, (6) our device meets the HP ON current expected
in ITRS 2013 roadmap for the year 2028, and (7) for LP, the upper performance
limit of device meets $\sim$ 52% ON current expected in ITRS 2013 roadmap for
the year 2028. We expect that our findings may pave the way for realizing
mono-layer pentagonal PdSe2 based p-FETs in the near future.

TABLE III: Comparison of p-FET with experimental data of Si based FinFET technology. $\rm I_{OFF}$ $\sim 10^{-1}A/m$. lightgray | $\rm L_{G}$ | $\rm V_{DD}$ | SS | $\rm I_{ON}$ | $\rm I_{ON}$
---|---|---|---|---|---
lightgray | (nm) | (V) | mV/dec. | (A/m) | /$\rm I_{OFF}$
DG FinFET [50] | 10 | 1.2 | 125 | 446 | 4.46$\times 10^{3}$
GAA FinFET[51] | 5 | 1.0 | 208 | 497 | 4.97 $\times 10^{3}$
PdSe2 p-FET |  $\sim$ 4 | 0.5 | 103 | 1030 | $1.03\times 10^{4}$

##  V Acknowledgment

K. Nandan thanks Prof. Amit Verma for fruitful discussions on electron
transport, Barun Ghosh for help with first principles calculations, and Dr.
Sarvesh S. Chauhan for his valuable feedback.

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