# Monolithic $\beta$-Ga2O3 Bidirectional MOSFET

Pooja Sharma  Saurabh Lodha<EMAIL_ADDRESS>Department of Electrical
Engineering, IIT Bombay, Mumbai, India - 400076

###### Abstract

We report a monolithic bidirectional dual-gate metal-oxide-semiconductor field
effect transistor (MOSFET) fabricated on epitaxially grown $\beta$-Ga2O3,
demonstrating efficient two-way conduction and blocking. It features two
independently controlled gates and operates in four distinct modes, offering
flexibility in managing current and voltage in the first and third quadrants.
This versatility makes it ideal for various power conversion system
applications. The device operates at a low negative threshold voltage (~-2.4 V
for both gates) with a zero turn-on drain voltage and an on-resistance of
approximately 500 $\Omega\cdot$mm. It exhibits a high on/off current ratio of
$10^{7}$ in all three conducting modes. In the blocking mode, the device
breakdown was measured to be more than $\pm$350 V with a current compliance of
0.5 mA/mm. The estimated breakdown field and power figure of merit for the
device are 0.35 MV/cm and 1.6 MW/cm2 respectively.

## Introduction

Bidirectional conductance is utilized in various applications such as AC-AC
power conversion systems 1, battery management systems in electric vehicles
for efficient charging and discharging 2, 3, 4, energy storage systems in
smart grids 5 for effective energy supply and storage and renewable energy
systems such as photovoltaic arrays 6, 7. It s also a key component of
uninterrupted power supplies (UPS) 8, motor drives 9 in industrial machinery,
and base stations for telecommunications 10.

Initially, thyristors with dedicated peripheral circuits were used to create
bidirectional switches, resulting in inefficient and bulky power circuits 11.
Over time, the use of power transistors has made bidirectional power switches
(BPS) smaller and more suitable for complex power circuits12. Typically, BPSs
consist of multiple discrete silicon-based insulated gate bipolar transistors
(IGBTs) or power metal-oxide semiconductor field effect transistors (MOSFETs)
arranged in common source, common drain, anti-parallel reverse blocking, or
diode bridge configurations.12 These commercially available bidirectional
switches offer versatile functionality but come with limitations. These
include complex control requirements 13, large component count, design
complexity and cost, high switching losses, and parasitic effects that can
impact efficiency and performance. Despite these challenges, bidirectional
switches are valuable for their flexibility and capability in managing
bidirectional current flow.

The emergence of monolithic bidirectional power transistor switches (M-BPSs)
marked a significant advancement14, 15. These transistors, fabricated with two
gates, facilitated integration of control and power handling capabilities,
improving performance characteristics such as faster switching speeds and
lower power losses. Monolithic designs also reduced the footprint and
complexity of power conversion modules 15, making them ideal for compact and
high-density electronic applications. The realization of a monolithic
bidirectional switch with dual-gate structure on GaN was reported by Morita et
al. 16, featuring a normally-off design. Subsequently, Peng et al. 17
demonstrated a monolithic fully-controlled high electron mobility transistor
(HEMT) BPS. This design further reduced power loss, featuring a low turn-on
voltage and high threshold voltage ($V_{TH}$) through the use of embedded
Schottky diodes. The dual-gate bidirectional switch takes advantage of a
common drain region to keep the device’s cell pitch as small as possible.15
Panasonic offers a normally-off dual-gate monolithic GaN bidirectional switch
that delivers symmetric 100 A conduction and 1,100 V blocking voltage 18.

Recent developments in SiC-based M-BPSs have resulted in higher blocking
voltages compared to GaN-based devices, which typically achieve up to $\pm$650
V. For example, SiC vertical bidirectional FETs can achieve $\pm$1200 V but
involve a common-drain setup with large chip area.19 A true monolithic 4H-SiC
IGBT, with a shared drain region has shown blocking voltages up to $\pm$7 kV.
However, these vertical SiC M-BPS architectures require complex double-sided
lithography and present cooling challenges 20. The more favourable dual
lateral gate M-BPS design has not been explored on SiC. On the other hand,
most commercially available lateral GaN transistors target the 650 V rating
21, 22 and a kV-range GaN transistor is not available commercially 23.
However, single-gate $\beta$-Ga2O3 transistors are more amenable to lateral
designs and have shown better high voltage (kV-range) handling capabilities
compared to both lateral GaN and lateral SiC devices24. Therefore, exploring
bidirectional transistor capabilities with $\beta$-Ga2O3 is worthwhile.

We demonstrate a simple monolithic bidirectional MOSFET designed and
fabricated on epitaxially grown $\beta$-Ga2O3. Both gates in the transistor
exhibit nearly the same $V_{TH}$ (-2.4 V and -2.3 V), with an on/off-current
($I_{ON}$/$I_{OFF}$) ratio of approximately $10^{7}$ at a drain bias
($V_{DS}$) of 15 V (in saturation region) for both gates. The dual-gate MOSFET
is tested in four distinct modes of operation by applying different gate
biasing schemes. The four modes include bidirectional conduction,
bidirectional blocking, and two diode modes. These tests show its ability to
manage different currents and blocking voltages as needed. In the two diode
modes, the device has non-zero (~$\pm$0.8 V) turn-on voltages due to the
formation of a diode junction in the channel because of two different bias
voltages applied to the two gates. But in the bidirectional conduction mode,
the transistor turns-on at zero volts, which would help in cutting down the
power loss. On-resistance ($R_{ON}$) of ~500 $\ohm$.mm is obtained for the two
transistors in series during the bidirectional conduction mode. In the
blocking mode, it shows voltage blocking capability of more than $\pm$350 V.
These parameters highlight its suitability for compact and efficient power
conversion applications.

## Experimental

The 5 x 5 mm, epi-grown, and $(010)$ oriented $\beta$-Ga2O3 substrate used in
this study was procured from Novel Crystal Technology Inc. Molecular beam
epitaxy grown stack used for the device consists of 200 nm thick, $1-5$ x
$10^{17}$ cm-3 Si-doped and 300 nm thick unintentionally doped (UID) layers on
top of an Fe-doped semi-insulating substrate as shown in Fig. 1. It was
cleaned using a standard cleaning procedure 25, 26, 27. This involved
ultrasonication in methanol and acetone for 3 minutes to degrease, followed by
immersion in piranha solution for 5 minutes to eliminate organic residues.
Next, we used an optical lithography system, microwriter from Durham Magneto
Optics Ltd., to define the source-drain (S-D) regions. $\beta$-Ga2O3 was then
etched in the S-D regions to create ~10 nm recess using BCl3/Cl2/Ar
inductively coupled plasma reactive ion etching (ICPRIE) at a chamber pressure
of 2 Pa, ICP power of 400 W and RF power of 75 W for 100 s. RIE treatment has
been reported to significantly reduce the S-D contact resistance28. This was
done prior to the evaporation and lift-off of a Ti:Au (30/100 nm) metal stack.
To further reduce the contact resistance, the Ti/Au stack was annealed at 470
°C for 3 minutes in an N2 atmosphere using a rapid thermal annealing (RTA)
system.

Figure 1: (a) Cross-section, (b) microscope image and (c) 3D schematic of the
monolithic bidirectional MOSFET with $L_{G}$= 2 $\mu$m, $L_{S1-S2}$= 15
$\mu$m, $L_{GD}$= 10 $\mu$m, and a common drain region of 5 $\mu$m.

The gate dielectric stack was deposited using an atomic layer deposition (ALD)
system. It consists of SiO2 (5 nm), AlN (5 nm), and Al2O3 (12 nm) 29 layers
deposited in a sequential in-situ fashion. SiO2 was deposited using O2 plasma
at 250 °C, AlN with NH3 plasma at 200 °C, and Al2O3 through thermal ALD at 250
°C. MESA isolation of the active transistor region was obtained by etching
using an Ar-ion milling system, achieving an etch depth of approximately 650
nm, exposing/reaching the semi-insulating substrate. The source-drain and MESA
sidewalls were then coated with 200 nm of sputtered SiO2 using optical
lithography and lift-off. Finally, gate metal Ni/Au (30/100 nm) was deposited
using an e-beam evaporator. The fabricated devices were electrically
characterized using the B1500 and B1505 semiconductor device analyzers from
Keysight.

## Results and Discussion

Conventional unidirectional as well as bidirectional MOSFETs were fabricated
together in the same process run on the same substrate to ensure a fair and
direct comparison of their electrical performance, with identical gate stack
and source-drain processing. The single-gate, unidirectional MOSFET helped in
verifying unit transistor characteristics using the triple dielectric layered
gate stack.

Transfer (forward and reverse sweeps are shown in supplementary material,
section 1) and output characteristics of a single-gate MOSFET ($L_{G}$= 2
$\mu$m, $L_{SD}$= 10 $\mu$m, $L_{GD}$= 5 $\mu$m, Fig. 2(a)) are shown in Fig.
2(b) and (c) respectively. The characteristics were measured at room
temperature. The device turns-on at a $V_{TH}$ of -1.6 V, indicating depletion
mode operation. MESFETs on similar substrates (in terms of doping, epi-layer
thickness and orientation) have been reported with $V_{TH}$ values of nearly
~-20 V 30, 31, 32. The dielectric stack was chosen to increase the $V_{TH}$
and move the device operation closer to normally-off state. The increase can
be attributed to a positive flat band voltage for MOS capacitors fabricated
with the SiO2/AlN/Al2O3 dielectric stack reported by Biswas et al. 29. SiO2
prevents gate leakage due to its high conduction band offset ($\Delta$$E_{C}$
~3.1 eV) 33 and forms a good interface with the lowest reported interface trap
density, $D_{IT}$ ($5.1$ x $10^{10}$ cm-2eV-1) on $\beta$-Ga2O3 25, 34. Al2O3
acts as the blocking layer, while AlN serves as the charge trapping layer,
with a smaller conduction band offset ($\Delta$$E_{C}$ ~1.4 eV) with
$\beta$-Ga2O3. The stack altogether shifts $V_{TH}$ towards 0 V. Although the
stack can be used to obtain enhancement mode operation through charge
trapping, we have not tested charge trapping in this study. Extracted
subthreshold slope (SS) and transconductance (gm) values are 220 mV/decade and
3.82 mS/mm respectively. The $I_{ON}$/$I_{OFF}$ obtained is ~7 x 107 at
$V_{DS}$= 15 V with a maximum on-current of 24 mA/mm (at gate bias, $V_{GS}$,
of 10 V) and off-current of nearly 1 nA/mm. The single-gate transistor
exhibits a breakdown voltage of more than 250 V (supplementary material,
section 2), consistent with reported values on similar substrates,35, 32
without incorporating any field management techniques. Extracted key parameter
values have been tabulated in Fig. 2(d). Contact and channel resistance values
extracted from transfer length measurements (TLM) are 5.14 k$\Omega$.mm and
180 k$\Omega$/sq (supplementary material, section 3) respectively. The
$R_{ON}$ value from output characteristics is ~264.3 $\Omega$.mm. The higher
contact resistance accounts for the slightly lower current values compared to
existing transistor reports on similarly doped substrates.32, 31

Figure 2: (a) Cross-section with $L_{G}$= 2 $\mu$m, $L_{SD}$= 10 $\mu$m,
$L_{GD}$= 5 $\mu$m, (b) transfer characteristics, transconductance (gm) and
(c) output characteristics of fabricated conventional single-gate
unidirectional $\beta$-Ga2O3 MOSFET, (d) table containing extracted
parameters, and (e) microscope image of fabricated device. Figure 3: (a) Four
distinct operation modes of the monolithic bidirectional MOSFET, (b)
individual transfer characteristics of the two gates of the bidirectional
transistor, (c) output characteristics with both gates at the same voltage in
on-condition, (d) off-condition with both gates at -6 V, and (e) parameter
values extracted from transfer and output characteristics.

The monolithic dual-gate MOSFET structure shown in Fig. 1 allows for a
bidirectional switch without significant active area penalty, as the drift
layer is shared by two transistors. This device structure was fabricated and
characterized by biasing it in four different modes. Two of the modes are
switch modes (bidirectional blocking and bidirectional conduction) and other
two are diode modes as illustrated in Fig. 3(a). For the first gate (G1), the
source and drain electrodes are designated as S1 and D1. Similarly, for the
second gate (G2), the source and drain electrodes are S2 (same as D1) and D2
(same as S1) respectively.

Transfer characteristics of the bidirectional MOSFET are shown in Fig. 3(b)
where both gates exhibit nearly the same $V_{TH}$ of ~-2.4 V. These
characteristics were measured with G1-to- S1 voltage (VG1-S1) swept from -8 to
20 V with G2-to-S2 voltage (VG2-S1) at 10 V and vice versa. The 0.1 V
difference in threshold voltages ($V_{TH-G1}$ and $V_{TH-G2}$) for the two
unit transistors is possibly due to slight misalignment or asymmetric
placement of gates between the source and the drain. $g_{m}$ and $I_{ON}$
values for the two gates also show a small disparity ($\Delta g_{m}$ ~0.9
mS/mm and $\Delta$$I_{ON}$ ~3 mA/mm), again due to asymmetric placement of the
two gates.

Figure 4:  Electrostatics of the bidirectional MOSFET is demonstrated with the
device biased to operate in two diode modes where (a) G1 is on and G2 is off,
and (b) G1 is off and G2 is on, illustrating how the channel junction
influences the turn-on voltage in the two diode modes. The output
characteristics of the bidirectional MOSFET in reverse diode mode are shown on
(c) logarithmic scale and (d) linear scale, and in forward diode mode on (e)
logarithmic scale and (f) linear scale, with one gate in the on condition and
the other at -6 V (off-state). These measurements are for a fabricated
bidirectional MOSFET with gate length ($L_{G}$) of 2 $\mu$m, source-drain
length ($L_{SD}$) of 15 $\mu$m, gate-drain length ($L_{GD}$) of 10 $\mu$m, and
a common drain region of 5 $\mu$m.

Output characteristics of the bidirectional transistor, shown in Fig. 3(c),
demonstrate 0 V turn-on operation and bidirectional current conduction with
both gates (G1 and G2) biased in the on state, $V_{G1-S1}$ > $V_{TH-G1}$ and
$V_{G2-S2}$ > $V_{TH-G2}$. This can significantly reduce conduction losses. In
bidirectional blocking (off) mode, both gates are biased at -6 V i.e.
$V_{G1-S1}$ < $V_{TH-G1}$ and $V_{G2-S2}$ < $V_{TH-G2}$, and S-D bias is swept
from -350 V to 350 V as shown in Fig. 3(d). The current levels remain below
$10^{-3}$ A (in the $\mu$A/mm range) upto $\pm$350 V. Key parameters extracted
from the transfer and output characteristics are summarized in Fig. 3(e).

In diode mode operation, the transistor can be biased to work in reverse or
forward blocking modes with charge distribution in channel as shown in Fig.
4(a) and (b) respectively. In the reverse conduction mode, where G1 is on and
G2 is off, current $I_{S1-S2}$ flows from terminal S2 (or D1) to terminal D2
(or S1). When $V_{G1-S1}$ > $V_{TH-G1}$ and $V_{G2-S2}$ < $V_{TH-G2}$, the
$\beta$-Ga2O3 region under G1 is in accumulation while that under G2 is in
depletion as illustrated in Fig. 4(a). This creates a lateral junction in the
$\beta$-Ga2O3 channel region, similar to a p-n junction, contributing to the
turn-on voltage as depicted by $I-V$ characteristics shown in Fig. 4(c) and
(d) for forward conduction mode. Similarly, a voltage drop occurs in forward
conduction mode as well, with reversed polarity on the two gates. In this
mode, the current $I_{S2-S1}$ flows from terminal S1 (D2) to terminal D1 (S2)
when $V_{G1-S1}$ < $V_{TH-G1}$ and $V_{G2-S2}$ > $V_{TH-G2}$ as illustrated in
Fig. 4(e) and (f). Both diode modes show an on/off-current ratio of nearly
$10^{7}$. The turn-on voltages are -0.8 V and +0.7 V for reverse and forward
diode-like modes, respectively, with corresponding $R_{ON}$ of 560 $\Omega$·mm
and 447 $\Omega$·mm. The $R_{ON}$ value is nearly twice that of the single-
gate transistor, possibly due to two transistors in series with extended
channel length ($\Delta$$L_{SD}$ ~5 $\mu$m). Extracted breakdown field
($E_{BR}$) values are 0.35 MV/cm for the bidirectional transistor ($V_{BR}$ >
350 V and $L_{GD}$= 10 $\mu$m) and 0.5 MV/cm for the single-gate
unidirectional transistor (with $V_{BR}$ > 250 V and $L_{GD}$= 5 $\mu$m). The
power figure of merit (PFOM) values for the two devices, bidirectional MOSFET
($R_{on,sp}$ ~75 m$\Omega$.cm2) and unidirectional single-gate ($R_{on,sp}$
~26 m$\Omega$.cm2), are calculated to be approximately 1.6 and 2.4 MW/cm2
respectively. Here, the specific-on-resistance, $R_{on,sp}$ is obtained by
normalising the $R_{ON}$ with channel length of the device, $L_{SD}$. The non-
zero turn-on voltage can contribute to conduction losses when the device
operates in either of these two diode modes. This bidirectional switch has no
on-state voltage offsets, enabling low-loss operation, but the slightly
negative $V_{TH}$ i.e. depletion mode operation can contribute to power loss.

## Conclusion

We have demonstrated a monolithic dual-gate bidirectional MOSFET using
$\beta$-Ga2O3. The transistor operates in depletion mode with a small negative
threshold voltage of -2.4 V and a high $I_{ON}$/$I_{OFF}$ ratio of $10^{7}$ at
$V_{DS}$=15 V for both gates with breakdown voltages of $\pm$350 V. The four
modes of operation—bidirectional conduction, bidirectional blocking, and two
diode modes—highlight the versatility of the transistor. Zero turn-on voltage
in the bidirectional conduction mode could significantly reduce power loss,
enhancing overall efficiency. However, the depletion mode operation can
inherently contribute to conduction losses. Future work can address this
limitation by fabricating bidirectional MOSFETs with enhancement mode
operation, further optimizing performance. The blocking mode performance can
also be enhanced with the use of field plates to increase the breakdown
voltages. Additionally, on-current can be improved by employing techniques
such as regrown source-drain contacts during the fabrication process, which
help reduce contact resistance.

In conclusion, this bidirectional transistor with its four modes of operation
in a lateral compact design furthers the potential of $\beta$-Ga2O3 for kV-
class bidirectional power switches in a host of power electronic applications
such as motor drive systems, hybrid vehicles, battery storage, super capacitor
charging, UPS systems and solar power generation.

## Supplementary Material

The supplementary material comprises TLM measurement data and double-sweep
(forward and reverse) hysteresis data for single-gate, unidirectional MOSFET.

## Acknowledgement

The authors thank Dr. Poulomi Chakrabarty, Netaji Suvachintak and Kanchan
Singh Rana for help with Ar-ion milling, ICPRIE etch and e-beam evaporation
for contact deposition respectively. The authors acknowledge the Indian
Institute of Technology Bombay Nano-fabrication Facility (IITBNF) for the
usage of its device fabrication and characterization facilities and support
from the Ministry of Electronics and Information Technology (through project
5(1)/2017-NANO) and Department of Science and Technology (through project
DST/NM/NNetRA/2018(G)-IIT-B), Government of India, for funding this work.
Pooja Sharma thanks University Grants Commission (UGC) for the doctoral
fellowship.

## Data Availability

The data supporting this study’s findings are included within the article [and
its supplementary material].

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