# A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride
Photonics

Venkata Sai Praneeth Karempudi  Department of ECE
University of Kentucky
Lexington, Kentucky, USA
<EMAIL_ADDRESS>Sairam Sri Vatsavai  Department of ECE
University of Kentucky
Lexington, Kentucky, USA
<EMAIL_ADDRESS>Ishan Thakkar  Department of ECE
University of Kentucky
Lexington, Kentucky, USA
<EMAIL_ADDRESS>Oluwaseun Adewunmi Alo  Department of ECE
University of Kentucky
Lexington, Kentucky, USA
<EMAIL_ADDRESS>Jeffrey Todd Hastings  Department of ECE
University of Kentucky
Lexington, Kentucky, USA
<EMAIL_ADDRESS>Justin Scott Woods  Argonne National Laboratory
Chicago, Illinois, USA
<EMAIL_ADDRESS>
###### Abstract

Over the past few years, several microring resonator (MRR)-based analog
photonic architectures have been proposed to accelerate general matrix-matrix
multiplications (GEMMs), which are found in abundance in deep learning
workloads. These architectures have dramatically grown in popularity because
they offer exceptional throughput and energy efficiency compared to their
electronic counterparts. However, such architectures, due to their traditional
realization based on the silicon-on-insulator (SOI) material platform, face
two shortcomings. First, the high-index contrast of the SOI platform incurs
high scattering losses, which mandates the provisioning of high optical input
power. Second, SOI waveguides are susceptible to two-photon absorption (TPA),
which can incur substantial optical signal losses at moderate-to-high signal
fan-in. These shortcomings have severely detrimental effects on the achievable
parallelism, throughput, and energy efficiency of SOI MRR-based GEMM
accelerators. To address these shortcomings, we present a novel Silicon
Nitride (SiN)-Based Photonic GEMM Accelerator called SiNPhAR. SiNPhAR
architecture employs SiN-based active and passive devices to implement analog
GEMM functions. Since the SiN material exhibits lower index contrast and no
TPA, the optical signal losses in our SiNPhAR architecture are very low. This
advantage significantly enhances the achievable processing parallelism,
throughput, and energy efficiency of SiNPhAR architecture, compared to SOI-
based photonic GEMM accelerators from prior work. We quantify and compare
these benefits of SiNPhAR architecture via our cross-layer evaluation for a
benchmark workload comprising four modern deep neural network models. From the
system-level performance analysis, SiNPhAR demonstrates at least 1.7$\times$
better throughput (frames-per-second (FPS)) while consuming at least
2.8$\times$ better energy efficiency (FPS/W) than prior SOI-based GEMM
accelerators.

##  I Introduction

Deep Neural Networks (DNNs) have revolutionized the implementation of various
artificial intelligence tasks, such as image recognition, language
translation, autonomous driving [1, 2], due to their high inference accuracy.
However, DNNs are computationally intensive, due to inherently abundant linear
computations such as general matrix-matrix multiplications (GEMM), which are
at the core of DNN operations [3]. This computational intensity of processing
the GEMM functions of DNNs is on a rapid rise owing to the ongoing rapid
evolution of DNN models. This has pushed for highly customized hardware GEMM
accelerators [4]. Among GEMM accelerators demonstrated in the literature,
silicon-photonic accelerators have shown great promise to provide unparalleled
parallelism, ultra-low latency, and high energy efficiency [5, 6, 7, 8, 9,
10]. In particular, Microring Resonator (MRR)-enabled silicon-photonic GEMM
accelerators have shown disruptive performance and energy efficiencies, due to
the compact footprint of MRRs, low dynamic power consumption of MRRs, and the
ability of MRRs to support a massive fan-in of optical signals through dense-
wavelength-division multiplexing (DWDM). These advantages have rendered up to
1000$\times$ more processing throughput and up to 100$\times$ better energy
efficiency to MRR-enabled silicon-photonic GEMM accelerators than their
electronic counterparts [7, 11].

However, the state-of-the-art MRR-enabled GEMM accelerators that are realized
using the traditional silicon-on-insulator (SOI) material platform face two
shortcomings. First, the high refractive index contrast between the silicon
core (Si) and cladding (SiO2) of an SOI waveguide leads to an enhanced
interaction of the guided optical mode with the rough sidewalls of the
waveguide. This introduces high scattering losses in the SOI waveguides [12].
Second, the presence of Two-Photon Absorption (TPA) in silicon has detrimental
effects on SOI devices, particularly waveguides. These effects lead to
substantial absorption losses in SOI waveguides, particularly when a moderate-
to-high number of multiplexed optical signals are propagating inside an SOI
channel waveguide. To counter these losses, a higher input optical power
becomes necessary. However, this increased input optical power whittles down a
significant part of the optical power budget, significantly hampering the
achievable spatial parallelism, throughput, and energy efficiency of SOI-based
photonic GEMM accelerators.

To address these shortcomings, we present a novel Silicon Nitride (SiN)-on-
SiO2-based photonic GEMM accelerator named SiNPhAR. Our SiNPhAR accelerator
integrates Indium Tin Oxide (ITO)-based SiN-on-SiO2 MRR modulators (MRMs)
within its input and weight banks, that are coupled to SiN-on-SiO2 waveguides.
These MRMs perform high-speed electro-optical encoding of electrical inputs
and weights onto optical signals. These input and weight banks seamlessly
integrate with our invented balanced photo-charge accumulator (BPCA) to
perform dot product operations of a large size. Unlike the SOI platform, the
SiN-on-SiO2 platform has a lower refractive index contrast between the core
(SiN) and cladding (SiO2) materials. This enables the design of ultra-low loss
($<$0.5 dB/cm [13, 12]) photonic waveguides. Additionally, the absence of
free-carriers in the SiN material eliminates the possibility of TPA [14, 12].
This characteristic enables SiN-on-SiO2 photonic waveguides to support a
higher count of multiplexed optical signals (higher fan-in) without incurring
excess absorption or scattering losses. Reduced optical losses empower our
SiNPhAR accelerator to achieve superior spatial parallelism, enhanced
throughput, and energy efficiency compared to prior SOI-based photonic GEMM
accelerators.

Our key contributions in this paper are summarized below:

  * •

We present the structure, operation, and characterization results of our
designed ITO-based SiN-on-SiO2 MRM;

  * •

We illustrate the use of our ITO-based SiN-on-SiO2 MRMs as input and weighting
elements, enabling massively parallel multiplication operations;

  * •

We design an accelerator architecture called SiNPhAR, which is based on the
SiN-on-SiO2 platform, and evaluate its achievable spatial parallelism;

  * •

We compare the throughput and energy efficiency results of our SiNPhAR
architecture with an SOI-based MRR-enabled GEMM accelerator from prior works.

##  II Preliminaries

###  II-A Background on SOI-Based Photonic GEMM Accelerators

Among the SOI-based photonic GEMM accelerators showcased in the literature, we
focus on the MRR-enabled SOI-based incoherent GEMM accelerators[15, 7, 10, 16,
17, 18]. These accelerators mainly employ multiple analog tensor processing
cores (TPCs) that operate in parallel, in which each TPC is utilized to
perform a dot product operation. Typically, each TPC is made up of five
essential blocks [17] (see Fig. 1 for an example TPC organization with five
blocks): (i) a laser block that employs N laser diodes (LDs) to generate N
optical wavelength channels; (ii) an aggregation block that aggregates the
optical wavelength channels generated by LDs into a single photonic waveguide
through DWDM technique by employing a N$\times$1 multiplexer, and then splits
the optical power of each of these wavelength channels equally into M separate
waveguides by using a 1$\times$M splitter; (iii) a modulation block that
consists of M banks of MRMs spread across M dot product elements (DPEs), with
each DPE employing one MRM bank; (iv) a weighting block that consists of
another M banks of MRRs spread across the M DPEs, with each DPE employing one
MRR bank; and (v) a summation block that comprises of a total of M summation
elements (SEs), with each SE corresponding to a DPE and employing two
photodiodes in a balanced configuration, commonly referred to as balanced
photodiode (BPD) configuration, connected to a transimpedance amplifier (TIA)
and an analog-to-digital converter (ADC). Typically, the laser block and SE
block are placed at the two ends of the TPC, whereas the aggregation,
modulation, and weighting blocks are placed in between them. Furthermore,
based on the positioning of these intermediate blocks, the MRR-based TPC
organizations demonstrated in the prior works can be classified into three
categories namely Aggregate, Modulate, Weight (AMW) TPC, Modulate, Aggregate,
Weight (MAW) TPC, and Modulate, Weight, Aggregate (MWA) TPC. In the AMW TPC,
the aggregation block is positioned first, followed by the modulation and the
weighting blocks. On the other hand, in the MAW TPC organization, the
modulation block is positioned first, followed by the aggregation and the
weighting blocks. For additional details on the AMW and MAW TPCs, we direct
the reader to [17].

Figure 1: Illustration of the MWA organization of an SOI-based TPC.

For detailed elucidation, Fig. 1 illustrates the organization of an MWA TPC.
As illustrated, the modulation and weighting blocks are placed before the
aggregation block. In particular, the arrangement of each input-weight MRM
pair is spectrally hitless [8] ensuring that each input-weight MRM pair
produces a multiplication result and modulates this result onto a single-
wavelength optical signal. This design eliminates inter-wavelength
interference known as inter-modulation crosstalk [19], at the MRMs, providing
a notable advantage over the AMW and MAW organizations [17]. There are a total
of M DPEs in the TPC. And, in each DPE, there are a total of N input-weight
MRM pairs, with each MRM pair acting as a multiplier. The modulation and
weighting blocks are connected to the aggregation block via a set of mono-
wavelength filter MRRs. The aggregation block consists of positive and
negative aggregation lanes that guide the signals to the SE block.

###  II-B Shortcomings of SOI Photonic GEMM Accelerators

The SOI-based photonic GEMM accelerators face two major shortcomings that
hinder their scalability, throughput, and energy efficiency.

####  II-B1 High Scattering Losses Due to High Index Contrast

The high refractive index contrast between the silicon core (Si, 3.5) and the
cladding (SiO2, 1.5) in SOI-based waveguides serves as a double-edged sword.
While it allows for the design of compact photonic waveguides by tightly
confining the guided optical modes to the core, it also makes these waveguides
highly susceptible to significant scattering losses. This is because it leads
to an enhanced interaction of the confined optical modes with the rough
sidewalls of the waveguide. This enhanced mode-roughness interaction increases
the scattering losses in the SOI waveguides. Studies have shown that even a
slight RMS roughness of a few nanometers on the sidewalls, which is
unavoidable due to fabrication imperfections, can result in substantial
waveguide losses, often exceeding 3 dB/cm in SOI channel waveguides [20, 12].

####  II-B2 High Absorption Losses Due to Two-Photon Absorption

The presence of free carriers in Si induces Two-Photon Absorption (TPA) in
SOI-based photonic devices at telecom wavelengths. TPA increases the free-
carrier density in the core (Si) material, leading to the Free-Carrier
Absorption (FCA) effect in SOI waveguides [12, 20]. FCA results in higher
absorption losses in SOI waveguides, particularly at elevated optical power
levels. In DWDM applications, where multiple wavelengths are coupled into each
SOI waveguide, the total optical power within the waveguide rises, triggering
TPA-induced FCA effects and subsequently causing high absorption losses.
Previous studies have shown that if the total number of wavelengths
multiplexed into an SOI waveguide exceeds 20, the optical losses experienced
by each additional wavelength channel propagating inside the waveguide
increase by 0.1 dB/cm/wavelength [21, 13].

###  II-C Motivation

To compensate for the high scattering and absorption losses in SOI waveguides,
one option is to increase the input optical power. However, this increased
input power whittles down a large portion of the optical power budget, leaving
a small portion of the power budget available to support the scalability of
size and spatial parallelism in SOI-based photonic GEMM accelerators.
Additionally, the need for higher input optical power undermines the energy
efficiency benefits associated with photonic GEMM accelerators. Therefore,
there is a need for an alternative that can alleviate the optical signal
losses and their detrimental impacts in photonic GEMM accelerators.

##  III SiNPhAR Architecture

To alleviate the high scattering and absorption losses and related issues
present in photonic GEMM accelerators, we propose to redesign photonic GEMM
accelerators with the silicon nitride (SiN)-on-SiO2 material system. Our idea
is to address the root causes of high scattering and absorption losses in SOI-
based designs, namely the high index contrast and TPA effect. The proposed
SiN-on-SiO2 material platform has been shown to exhibit ultra-low waveguide
propagation losses (absorption + scattering losses) ($<$0.5 dB/cm [13, 12])
due to its low refractive index contrast compared to the SOI platform. In
addition, the absence of free carriers in the SiN material eliminates the
possibility of TPA-induced increase in absorption losses [14, 12]. Our forged
GEMM accelerator architecture based on the SiN-on-SiO2 platform, which we call
SiNPhAR architecture, is described in the following subsections.

###  III-A Overview of SiNPhAR Tensor Processing Core (TPC)

The main processing unit of our SiNPhAR architecture is a tensor processing
core (TPC) (illustrated in Fig. 2), which follows the MWA TPC organization
described in Section II.A, with several critical modifications in the
constituent blocks. Across the modulation, aggregation, and weighting blocks,
all the utilized photonic devices, including the waveguides, MRMs, and filter
MRRs, are based on the SiN-on-SiO2 material platform. We take the designs of
the SiN-on-SiO2 waveguides from [22] and filter MRRs from [23], whereas we
invent a new Indium Tin Oxide (ITO)-based all-pass design for SiN-on-SiO2 MRMs
(discussed in Section III-B). In addition, as the summation (SE) block, we
utilize our newly invented balanced photo-charge accumulator (BPCA) (discussed
in Section III-D). Atop these modifications, a SiNPhAR TPC employs all-pass
MRMs in its weighting blocks, which is different from the add-drop MRRs used
in the weighting blocks of SOI-based MWA TPC. Because of this difference, a
SiNPhAR TPC utilizes a filter MRR after each input-weight MRM pair. This
filter MRR allows routing of the optical signal incoming from the input-weight
MRM pair onto the positive or negative aggregation lanes, depending on the
sign of the multiplication result produced by the input-weight MRM pair. The
structure and functionality of various blocks of a SiNPhAR TPC are discussed
in the upcoming subsections.

Figure 2: Schematic of a TPC of our SiNPhAR GEMM Accelerator.

###  III-B ITO-Based SiN MRM for Input Encoding

Structure. Fig. 3(a) and Fig. 3(b), respectively, show the top-view and cross-
sectional schematic of our SiN-on-SiO2 MRM. Fig. 4 shows the scanning electron
microscope (SEM) image of our fabricated SiN-on-SiO2 MRM. The active region in
the upper cladding of the MRM consists of a stack of two ITO thin films with a
silicon dioxide (SiO2) thin film in between (i.e., an ITO-SiO2-ITO stack).
From Fig. 3(b), we have a 300 nm thick SiN-based MRM waveguide, two 10 nm
thick ITO films, and 15 nm thick SiO2 layer. Upon applying voltage across the
ITO-SiO2-ITO stack (through the Au pads shown in Fig. 3(a) and Fig. 4), free
carriers accumulate in the ITO films at the ITO-SiO2 interfaces for up to 5 nm
depth in the ITO films [24], making these accumulation regions in the ITO
films high-carrier-density active regions. In these regions, a free-carriers-
assisted, large-amplitude modulation in the permittivity and refractive index
of the ITO material has been previously reported [24]. This kind of free-
carriers based index modulation in the ITO films of our MRM follows the Drude-
Lorentz model from [25]. Accordingly, as the carrier concentration in the ITO
accumulation regions increases, the refractive index of the ITO films
decreases. As a result, the effective refractive index of our SiN-on-SiO2 MRM
from Fig. 4 also decreases, causing a blue shift in its resonance wavelength
that in turn causes a transmission modulation at the through port of the MRM.
The electro-refractive activity of our SiN-on-SiO2 MRM is confined only in the
ITO-SiO2-ITO cladding. This is different from the Si-SiO2-ITO capacitor-based
MRR modulator from [26], which has the electro-refractive as well as electro-
absorptive activities in both its Si-based MRR core and SiO2-ITO based
cladding.

Figure 3: (a) Top view, (b) Cross-sectional view (along AA’) of our SiN-on-SiO2 MRM. Figure 4: SEM image of our fabricated SiN-on-SiO2 MRM. TABLE I: Free-carrier concentration (N), real index (Re($\eta_{ITO}$)), and imaginary index (Im($\eta_{ITO}$)) for the ITO accumulation layer in our MRM. The real and imaginary effective index (Re($\eta_{eff}$), Im($\eta_{eff}$)), operating voltage (V), and induced resonance shift ($\Delta\lambda_{r}$) for our MRM. | N
---
($cm^{-3}$)
| Re
---
($\eta_{ITO}$)
| Im
---
($\eta_{ITO}$)
| Re
---
($\eta_{eff}$)
| Im
---
($\eta_{eff}$)
V |  | $\Delta\lambda_{r}$
---
(pm)
1 × $10^{19}$ | 1.9556 | 0.0100 | 1.9735 | 0.0001 | 0 | 0
5 × $10^{19}$ | 1.9111 | 0.0403 | 1.9724 | 0.0003 | 1.8 | 830
9 × $10^{19}$ | 1.8667 | 0.0896 | 1.9712 | 0.0006 | 3.7 | 1580
13 × $10^{19}$ | 1.8222 | 0.1289 | 1.9701 | 0.0011 | 5.5 | 2470
17 × $10^{19}$ | 1.7778 | 0.1582 | 1.9692 | 0.0017 | 7.3 | 3210
20 × $10^{19}$ | 1.7333 | 0.1874 | 1.9680 | 0.0022 | 9.2 | 4000

Testing and Characterization Results. To test and characterize our MRM, we
evaluated the required voltage levels across the Au pads (Figs. 3(a) and 4)
for achieving various free-carrier concentrations in the ITO films. Then, we
extracted the corresponding ITO index change values for various free-carrier
concentrations. These results are listed in Table I. We also extracted the
effective index change and transmission spectra of our MRM (shown in Table I
and Fig. 5 respectively) at various applied voltages for the operation around
1.6 $\mu$m wavelength (L-band). From Fig. 5, our MRM achieves a resonance
shift of up to 4 nm upon applying 9.2 V across the thin-film stack, which
renders the resonance tuning (modulation) efficiency of $\sim$450 pm/V. This
is a crucial outcome, as our MRM has a relatively very low overlap between the
optical mode and free-carrier perturbation (only 10% of the guided optical
mode overlaps with the upper cladding based on ITO) compared to the silicon
ITO-based modulators (e.g., [26]).

Further, from the spectra in Fig. 5, we evaluate the FSR of our MRM to be
$\sim$18 nm. We evaluated the insertion loss and loaded Q-factor of our MRM to
be $\sim$0.235 dB and $\sim$2000 respectively. We also evaluated the
capacitance density of the ITO thin-film stack covering the MRM rim to be
$\sim$2.3 fF$/\mu$m2 for the 15 nm thick SiO2 layer. Moreover, we measured the
optical eye diagrams for the MRM at 30 Gb/s and 55 Gb/s operating bitrates and
found that our MRM can achieve 8.2 dB extinction ratio for OOK modulation at
30 Gb/s bitrate, which confirms the high-speed operation of our MRM.

Figure 5: Transmission spectra of our SiN-on-SiO2 MRM.

Use as an Input-Encoding Element. As described above, our MRM can produce a
high-speed optical signal. This signal can be generated as a temporal train of
optical amplitude symbols, similar to how an SOI MRM is used in SOI-based
photonic GEMM accelerators to generate an optical signal as a temporal train
of optical symbols [7]. In this signal, the amplitude of each symbol
represents an analog input value. Thus, our MRM, when used for input encoding,
can produce an optical signal as a temporal train of analog input values.

###  III-C ITO-Based SiN MRM for Weighting

Our unique ITO-based SiN-on-SiO2 MRM serves a dual purpose in our TPC,
functioning not only as a high-speed electro-optic input encoding element but
also as a high-speed electro-optic weighting element. In this paper, we
explored its application in performing precise weighting of input-modulated
optical signals. To assess the effectiveness of our MRM in this context, we
conducted a comprehensive study with weighting values of 3-bit resolution.

Intuitively, a weighting MRM of 3-bit (4-bit) resolution should be able to
alter the transmission of an input optical amplitude/symbol to one of the 23=8
(24=16) distinct output amplitude levels. These 8 or 16 distinct output
amplitude levels are achieved in our MRM at its through port by enabling
electro-optic shifting of its resonance passband to 8 or 16 distinct spectral
locations. Consequently, to imprint a certain 3-bit or 4-bit weighting on an
input optical symbol, the input optical symbol is applied at the input port of
the MRM, and then, the analog-converted (via a digital-to-analog converter)
3-bit or 4-bit weight value is applied to the electrical I/O pads of the MRM
(see Fig. 4) to effect an electro-optic shifting of the MRM’s resonance
passband. The shifted passband programs the through-port transmission of the
input optical symbol to a corresponding output amplitude value from the 8 or
16 possible output amplitude levels. Fig. 6 illustrates how the shifting of
our MRM’s resonance passband enables weighting with 3-bit resolution. In the
figure, $\lambda_{T}$ shows the optical wavelength carrying the input optical
symbol, and the 8 resonance passbands show the electro-optically shifted
spectral locations corresponding to 8 output transmission amplitudes. When the
spectral position of the passband is shifted, the intersection point of the
passband with $\lambda_{T}$ changes, which in turn alters the transmission
amplitude. Thus, our MRM can be used to implement a weighting of an input
optical symbol.

This operation of MRM weighting element can also be used to weight a high-
speed optical signal output from an input-encoding MRM. For that, the MRM
resonance passband is shifted to achieve different weighting amplitudes at a
speed that is matched to the symbol rate of the input high-speed optical
symbol. As a result, each symbol of the input optical signal is weighted with
a unique weighted value to generate a weighted optical signal. Each symbol of
the weighted optical signal, thus, represents a multiplication result
(product) between the input and weight values. Therefore, the weighted optical
signal generated by a weighting MRM is also referred to as an optical product
signal. Each symbol of this optical product signal, depending on its sign, is
routed to the positive or negative aggregation lane, in the aggregation block
of the SiNPhAR TPC.

Figure 6: Transmission spectra measured at the through port of our SiN-on-SiO2
MRM weighting element for various transmission amplitudes. These different
transmission amplitudes at $\lambda_{T}$ signify the weighting of the input
optical amplitude symbol.

###  III-D Summation with Balanced Photo-Charge Accumulator (BPCA)

In a DPE of a SiNPhAR TPC, each weighting MRM outputs one optical product
signal, and a total of N such optical product signals are aggregated into the
positive and negative aggregation lanes. The aggregation lanes deliver these
optical product signals to the BPCA circuit for summation. Our BPCA circuit is
collectively inspired by the time integrating receiver (TIR) design from [27]
and the photodetector-based optical pulse/symbol accumulator design from [28].
As illustrated in Fig. 2, a BPCA circuit employs two photodiodes, each
connected to the positive and negative aggregation lanes. These photodiodes
are interlinked in a balanced configuration, commonly referred to as a
balanced photodiode (BPD) configuration. The BPD is connected to a TIR. The
TIR comprises an amplifier and a feedback capacitor/switch pair (Fig. 2).

A total of N optical product symbols arrive at the BPCA during a symbol cycle.
The constituent BPD of the BPCA performs an incoherent superposition (signed
summation) of all these N optical product symbols received within that cycle.
Consequently, the incoherent superposition first enables the creation of a net
optical symbol. The total optical energy packetized within a new optical
symbol is proportional to the signed summation of the N optical product
symbols. The BPD transduces this net optical symbol into a balanced
photocurrent symbol, which is further transduced by the TIR of the BPCA into
an analog voltage level accrued on the capacitor of the TIR. This accused
analog voltage level, thus, represents a summation of N products, i.e., an
N-sized dot product.

This N-sized dot product result, in the form of the accrued analog voltage
level, can be held by the TIR. As new net optical symbols keep arriving in
subsequent symbol cycles, the TIR enables a gradual integration (temporal
accumulation) of the individual dot product results over multiple symbol
cycles to generate a larger ($>$N-sized) dot product result. This is possible
because the N-sized dot product results arriving at the TIR can sequentially
charge the TIR’s capacitor so that the net accumulated charge and,
consequently, the net analog voltage accrued on the capacitor over multiple
symbol cycles provides the signed sum of the individual dot product results.
This final sum value in the analog voltage format can be sampled and sent to
the analog-to-digital converter (ADC) for conversion in the binary format.
Thus, the BPCA of a SiNPhAR DPE can essentially enable the processing of very
large-sized ($>$N-sized) dot products.

##  IV Evaluation and Discussion

###  IV-A Scalability Analysis

To perform scalability analysis, we utilized the equations provided in [15],
reproduced as Eqs. 1, 2 and 3. The parameters and their corresponding values
[15, 17, 18] required to solve these equations are listed in Table II. We
devised a two-step procedure to determine the optimal value of N and M (N
refers to the count of input-weight MRM pairs per DPE, whereas M refers to the
count of DPEs per TPC) for a given bit precision and data rate (DR), as
outlined below.

Step 1. We calculate the photodiode (PD) sensitivity by solving Eq. 1 for the
specified bit precision and DR.

Step 2. Next, we perform an exhaustive search to find the optimal value of N
(assuming N = M) for the specified bit precision and DR, using Eqs. 2 and 3.
In this step, we solve Eq. 3, which represents the error function (ef). The ef
is the difference between the optical power reaching the photodiode (Poutput),
calculated from Eq. 2, and the PD sensitivity obtained in Step 1/Eq. 1. We
sweep for different values of N, and the optimal value of N for the specified
bit precision, and DR is the one for which the ef yields the minimum positive
value. Notably, when solving Eqs. 2 and 3, we consider Pinc (see Table II for
definition) to be zero for ’N’ values less than 20 wavelengths/waveguide.
However, beyond 20 wavelengths/waveguide, we account for a changing Pinc
between the SOI and the SiN waveguides, as reported in Table II. This is
because the TPA-induced absorption losses in the SOI waveguide substantially
increase if the total number of multiplexed wavelengths in an SOI waveguide
exceeds 20 (as discussed in Section II-B). In contrast, this phenomenon is not
observed in SiN waveguides, as detailed in Section III.

Figure 7: Supported TPC size N(=M) for bit precision = {1,2,3,4}-bits at data
rates (DRs)={1,5,10} GS/s, for SOI-MWA TPC and SiNPhAR TPC.

For our analysis, we considered bit-precision values ranging from 1-bit to
4-bits and a set of DRs namely 1GS/S, 5GS/S, and 10GS/S. The results of our
analysis are illustrated in Fig. 7. In addition to our SiNPhAR, we conducted
the scalability analysis for an SOI-based MWA TPC (Fig. 1) named as SOI-MWA.
From Fig. 7, our SiNPhAR can support a larger value of N compared to SOI-MWA.
For instance, our SiNPhAR can support N=52 for a bit-precision of 3-bits, DR =
1GS/S, and an input laser power of 10dBm, which is larger compared to SOI-MWA
that supports N=35. This advantage primarily stems from the reduced
propagation losses in the SiN-on-SiO2 waveguides and the lower insertion loss
of the ITO-based SiN-on-SiO2 MRMs in SiNPhAR, compared to the SOI waveguides
and MRMs in SOI-MWA. Consequently, this creates a larger room in the optical
power budget, allowing for the accommodation of a larger N in our SiNPhAR TPC.

$B=\frac{1}{6.02}\left[20\log_{10}\left(\frac{RP_{\text{PD-opt}}}{\left(\sqrt{2q\left(RP_{\text{PD-opt}}+I_{d}\right)+\frac{4KT}{R_{L}}+\left(RP_{\text{PD-opt}}\right)^{2}\text{RIN}}+\sqrt{2qI_{d}+\frac{4KT}{R_{L}}}\right)\sqrt{\frac{DR}{\sqrt{2}}}}\right)-1.76\right]$ (1) $\displaystyle P_{\text{output}}(\text{dBm})=$ $\displaystyle P_{\text{L}}-P_{\text{SMF}}-P_{\text{C}}-(P_{\text{WG-IL}}\times d_{\text{MRR}}\times N)-(P_{\text{Inc}}\times d_{\text{MRR}}\times(\text{N-20}))-(P_{\text{sp}}\times\log_{2}(\text{N}))-P_{\text{MRM}}-P_{\text{MRR}}$ (2) $\displaystyle-((\text{N-1})\times P_{\text{MRM-OBL}})-((\text{N-1})\times P_{\text{MRR-OBL}})-P_{\text{penalty}}$ $\text{ ef }(\mathrm{B},\mathrm{DR},\mathrm{N})=P_{\text{output }}(\mathrm{N})-P_{PD-\text{ opt }}(\mathrm{B},\mathrm{DR})$ (3) TABLE II: Definition and values of various parameters used in Eq. 1, Eq. 2, and Eq. 3 (from [15]) for the scalability analysis. Parameter | Definition | Value
---|---|---
PL | Laser Power Intensity | 10 dBm
PSMF |  | Attenuation by the
---
Single Mode Fiber
0 dB
PC |  | Fiber-to-Chip
---
Coupling Insertion Loss
1.6 dB
PWG-IL |  | Propagation Loss of
---
SOI Waveguide
1.5 dB/cm
| Propagation loss of
---
SiN Waveguide
0.5 dB/cm
Pinc |  | Increase in Propagation Loss of the
---
SOI waveguide atop 20 $\lambda$s/waveguide
0.1 dB/cm/$\lambda$
| Increase in Propagation Loss of the
---
SiN waveguide atop 20 $\lambda$s/waveguide
0.01 dB/cm/$\lambda$
PSP | Splitter Insertion Loss | 0.01 dB
PMRM |  | Transmission Insertion Loss
---
of the SOI MRM
4 dB
| Transmission Insertion Loss
---
of the SiN MRM
0.235 dB
PMRR |  | Transmission Insertion Loss
---
of the SOI MRR
0.01 dB
PMRM-OBL |  | Out-of-Band Insertion
---
Loss (OBL) of the MRM
0.01 dB
PMRR-OBL |  | Out-of-Band Insertion
---
Loss (OBL) of the MRR
0.01 dB
PPenalty |  | Network Penalty
---
for SOI-MAW
1.8 dB
| Network Penalty
---
for SiNPhAR
R | PD Responsivity | 1.2
q | Charge of an Electron (C) | 1.6 $\times$ 10-19
Id | PD Dark Current | 35 nA
K | Boltzmann Constant (J/K) | 1.38 $\times$ 10-23
T | Absolute Temperature (K) | 300
RL | Load Resistance (Ohms) | 50
RIN | Relative Intensity Noise (dB/Hz) | -140
B | Bit-Precision |
PPD-OPT | PD Sensitivity | -

###  IV-B System-Level Evaluation Method

####  IV-B1 System-Level Implementation

Fig. 8 illustrates the general system-level implementation of a photonic GEMM
accelerator. It consists of global memory that stores convolutional neural
network (CNN) parameters and a pre-processing and mapping unit. It has a mesh
network of tiles. Each tile contains 4 dot-product units (DPUs) (a DPU is
synonymous/analogous to a TPC) interconnected (via H-tree) with a unified
buffer as well as pooling and activation units. Each TPC/DPU consists of
multiple DPEs and each DPE is equipped with a dedicated input and output FIFO
buffer [29] to store intermittent weights, inputs, and partial sum values. The
generic DPUs/TPCs in the system are replaced with SiNPhAR TPCs and SOI-MWA
TPCs, respectively, to derive SiNPhAR and SOIPhAR accelerator system
architectures.

####  IV-B2 Simulation Setup

In our study, we employed a custom Python-based simulator to emulate the
system-level deployment of SiNPhAR and SOIPhAR accelerator architectures. The
simulation involved the inference of four distinct CNN models (with a batch
size of 1): ShuffleNet V2 [30], GoogleNet [31], and ResNet50 [32]. We
converted the convolutional layers and fully connected layers of these CNNs
into GEMM operations using the Toeplitz matrix transformations or im2col
functions [17, 18], and then accelerated these GEMM operations on our
considered accelerators. We conducted a comparative analysis of SiNPhAR and
SOIPhAR accelerator architectures in the context of inferring 8-bit integer
quantized CNN models. Key metrics such as Frames per second (FPS) and FPS/W
(energy efficiency) were evaluated. All accelerators were operated across data
rates of 1GS/s, 5GS/s, and 10GS/s. Each TPC was operated at 4-bit precision;
therefore, two TPCs were used with back-end shift-and-add circuits to achieve
8-bit computational precision. For these specific data rates, SOIPhAR and
SiNPhAR achieve N (TPC size) as shown in Table III. Our evaluation is based on
output stationary dataflow. To ensure a fair comparison, we carried out an
area proportionate analysis, wherein we adjusted the TPC count for each
SiNPhAR and SOIPhAR variants listed in Table III so that the total area
consumption of all TPCs per variant remained constant across all variants.

Figure 8: System-level implementation of SiNPhAR accelerator. DPU=TPC.

Table II outlines the parameters used for our evaluation, while Table IV
provides the parameters used for assessing the overhead of the peripherals in
our evaluated accelerators. We set each laser diode to emit an input optical
power of 10 mW (10 dBm) (Table II). The parameters for the multiplexer and
splitter were sourced from [5].

TABLE III: TPC size (N) and TPC Count (#) at 4-bit precision across various data rates for various accelerator architectures. | Datarate
---|---
| 1 GS/s | 5 GS/s | 10 GS/s
TPC | N | # | N | # | N | #
SOIPhAR | 22 | 132 | 15 | 155 | 13 | 162
SiNPhAR | 47 | 50 | 28 | 95 | 22 | 116

[b]  Power(mW) Latency Area($mm^{2}$) Reduction Network 0.050 3.125ns 3.00E-5
Activation Unit 0.52 0.78ns 6.00E-5 IO Interface 140.18 0.78ns 2.44E-2 Pooling
Unit 0.4 3.125ns 2.40E-4 eDRAM 41.1 1.56ns 1.66E-1 Bus 7 5 cycles 9.00E-3
Router 42 2 cycles 1.50E-2 DAC [33] 12.5 0.78ns 2.50E-3 ADC(1 GS/s) [34] 2.55
0.78ns 2E-3 ADC(5 GS/s) [35] 11 0.78ns 21E-3 ADC(10 GS/s) [36] 30 0.78ns
103E-3 EO MRM Operation 1.4 pJ/bit - 0.95E-4

TABLE IV: Accelerator Peripherals and TPC Parameters [17].

###  IV-C System-Level Evaluation Results

In Fig. 9(a), the Normalized FPS results for various accelerators with a batch
size of 1, operating at different datarates are presented. These results are
normalized to SOIPhAR for ResNet50 [32] at a datarate of 10 GS/s. SiNPhAR
accelerators outperforms SOIPhAR accelerators in terms of gmean across four
CNN models at all datarates. Specifically, at 1 GS/s, SiNPhAR achieves up to
1.7$\times$ better FPS than SOIPhAR. As the datarate increases to 5 GS/s,
SiNPhAR exhibits further improvements in FPS over SOIPhAR, achieving up to
1.8$\times$ better FPS than SOIPhAR. These remarkable throughput improvements
in SiNPhAR are attributed to two main factors. Firstly, the SiNPhAR
architecture utilizes SiN-based active and passive devices to implement analog
GeMM functions. The low optical signal losses in the SiNPhAR architecture,
owing to the low-index contrast and absence of two-photon absorption (TPA) in
SiN material, enable the support of a larger TPC size (N=47) compared to that
of SOIPhAR (N=22). This larger TPC size, as shown in Table III, increases the
size of the dot product operation N and the number of parallel dot product
operations M, thereby enhancing overall throughput via improved parallelism.
Secondly, a larger N results in fewer buffer accesses of weight and input
values, reducing the buffer access latency. This reduction in access latency
improves FPS. Furthermore, as the datarate increases, the FPS of each
accelerator decreases. At 5 GS/s and 10 GS/s, the N value decreases for all
accelerators, as indicated in Table III, leading to low parallelism and
increased buffer accesses. This increase in access latency with higher
datarates results in lower FPS for the accelerators.

Figure 9: (a) Normalized FPS (log scale) (b) Normalized FPS/W (log scale) for
SiNPhAR versus SOIPhAR accelerators with input batch size=1. Results of FPS
and FPS/W are normalized w.r.t. SOIPhAR ResNet50 at 10 GS/s.

In Fig. 9(b), the energy efficiency (FPS/W) results are presented on a log
scale for both SOIPhAR and SiNPhAR accelerators, using a batch size of 1 at
various datarates. These results are normalized to SOIPhAR for ResNet50 at the
datarate of 10 GS/s. Notably, the SiNPhAR accelerators demonstrate superior
energy efficiency compared to the SOIPhAR accelerators. Specifically, at 1
GS/s, SiNPhAR achieves 2.8$\times$ better FPS/W compared to SOIPhAR, based on
the Gmean across the CNNs. As the datarate increases to 5 GS/s, SiNPhAR
achieves even better improvement over SOIPhAR, with 3.19$\times$ better FPS/W
when compared to SOIPhAR.

These energy efficiency advantages of SiNPhAR stem from several factors.
First, the improved throughput and reduced energy consumption of buffer
accesses contribute to enhanced energy efficiency. As discussed earlier, the
higher N value supported by SiNPhAR results in improved parallelism, which, in
turn, reduces dynamic energy consumption while maintaining higher throughput.
Additionally, SiNPhAR requires overall fewer buffer accesses of input and
weight values, leading to energy savings by reducing the energy consumption
corresponding to buffer accesses. As the datarate increases, the peripheral
components of the accelerator, such as ADCs and DACs, consume more power (as
indicated in Table IV). This additional power consumption decreases the
achieved FPS/W for both SOIPhAR and SiNPhAR accelerators.

##  V Conclusion

In this paper, we presented a novel SiN-based photonic GEMM Accelerator called
SiNPhAR. Our SiNPhAR accelerator employs SiN-on-SiO2 based waveguides ITO-
enabled SiN-on-SiO2-basedmicroring modulators (MRMs) as input and weight
elements, to implement analog GEMM functions. The key advantages of SiNPhAR
over traditional SOI-based photonic GEMM accelerators lie in the absence of
Two-Photon Absorption (TPA) nonlinearity and the low index contrast of the
SiN-on-SiO2 devices. These features enable SiNPhAR to experience significantly
low optical signal losses compared to traditional SOI-based photonic GEMM
accelerators, substantially enhancing its parallelism, throughput, and energy
efficiency. To validate these benefits of our SiNPhAR accelerator, we
evaluated its achievable parallelism and performance and compared it with a
traditional SOI-based GEMM accelerator from prior work. Our analysis reveals
that SiNPhAR supports at least 1.5$\times$ more multipliers than the prior
SOI-based photonic GEMM accelerator. Furthermore, from the system-level
performance analysis, SiNPhAR demonstrates at least 1.7$\times$ better
throughput (FPS) while consuming at least 2.8$\times$ better energy efficiency
(FPS/W) compared to the prior SOI-based GEMM accelerator.

## Acknowledgments

We thank the anonymous reviewers whose valuable feedback helped us improve
this paper. We would also like to acknowledge the National Science Foundation
(NSF) as this research was supported by NSF under grant CNS-2139167.

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