# Noise Analysis for Performance Evaluation of Biopotential Recording Front-
Ends

Taeju Lee T. Lee was with the School of Electrical Engineering, Korea Advanced
Institute of Science and Technology (KAIST), Daejeon 34141, Republic of Korea.
He is now with the Department of Electrical Engineering, Columbia University,
New York, NY 10027, USA. Department of Electrical Engineering, Columbia
University, New York, NY 10027, USA
E-mail<EMAIL_ADDRESS>
Abstract—Noise efficiency factor and power efficiency factor are widely used
as the figure of merit to quantify the performance of biopotential recording
front-ends. The noise efficiency factor provides a dimensionless quantity that
indicates how much better current-noise efficiency is achieved compared to an
ideal bipolar junction transistor when assuming the total bias current and
recording bandwidth of a front-end are the same as an ideal bipolar junction
transistor. The power efficiency factor indicates how much better power-noise
efficiency is achieved compared to an ideal bipolar junction transistor,
taking into account the supply voltage, total bias current, and bandwidth.
Compared to the noise efficiency factor, the power efficiency factor is
calculated using voltage and current values, thereby enabling the power
consumption
$(=\textit{V\textsubscript{DD}}\times\textit{I\textsubscript{DD}})$-considered
noise performance comparison between different front-ends. In this article,
the noise efficiency factor and power efficiency factor of biopotential
recording front-ends are explored according to CMOS technology scaling and
front-end architectures. Index Terms—Analog front-end, biopotential amplifier,
bioelectric signal, brain-machine interface, BMI, brain-computer interface,
BCI, CMOS, figure of merit, FoM, noise analysis, noise efficiency factor, NEF,
power efficiency factor, PEF, technology scaling.

##  I. INTRODUCTION

Biopotential recording front-ends have played an important role in observing
bioelectric signals, which has revolutionized biomedical engineering spanning
personal healthcare, neuroscience, brain-machine interface, etc. Over the last
decades, the performance of biopotential recording front-ends has considerably
advanced in the input-referred noise, design area, energy efficiency, etc. In
reality, the design area of a single front-end has been reduced, the power
consumption has also been reduced as the supply voltage has declined, and
nonlinearity has greatly improved. In addition, various front-end performances
have significantly advanced, enabling reliable in-vivo and in-vitro signal
monitoring.

The performance of biopotential recording front-ends has been quantified using
the common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR),
dynamic range (DR), input impedance, etc. Among them, the noise efficiency
factor (NEF) and power efficiency factor (PEF) have been widely employed to
quantify the performance of front-ends over the last decades.

Figure 1: Frequency of use of each front-end architecture.

NEF and PEF have been widely used as figure of merits (FoMs) to summarize and
compare the front-end performance by taking into account the input-referred
noise, bandwidth, bias current, and supply voltage. Since the 1970s, various
kinds of front-end architectures have been developed to observe bioelectric
signals and appropriate architecture has been used to meet the target
performance. Depending on the front-end architecture, NEF and PEF have been
diversely achieved. Fig. 1 presents how frequently each front-end architecture
has been used over the past decades. Note that Fig. 1 is implemented by
investigating the architectures of biopotential recording front-ends developed
since the 1970s and the front-ends investigated are listed in [1], [2].

As shown in Fig. 1, a variety of architectures have been used to design the
front-ends, but among those architectures, the capacitive feedback front-end
[3] has been widely used due to its DC offset filtering, superior noise
performance, and design simplicity. Also, diverse circuit techniques have been
developed based on the capacitive feedback architecture to improve NEF and
PEF. Moreover, to overcome the theoretical limit of NEF and PEF in the
capacitive feedback front-end, the front-ends based on discrete-time
amplification [4], [5] are proposed, which is classified as _Other_ in Fig. 1
since the number of prototypes is not yet sufficient.

In this article, NEF and PEF of biopotential recording front-ends developed
since the 1970s are explored according to the architectures categorized in
Fig. 1. NEF and PEF used in this article are obtained by investigating the
prior front-ends listed in [1], [2]. Section II describes the NEF background
as well as the trends according to the architectures and technology nodes. The
background and trends of PEF are presented in Section III. Section IV presents
the performance mapping of technology nodes, NEF, and PEF for all front-end
architectures. Finally, Section V concludes this article by discussing other
FoMs that need to be considered in front-end design. Note that NEF and PEF are
used to quantify the performance of a front-end that measures voltage signals
rather than current signals, therefore, the front-ends considered in this
article mean tools measuring voltage signals generated from brain activity,
heart activity, muscle activity, etc.

##  II. NOISE EFFICIENCY FACTOR

The biopotential recording front-end, which measures voltage signals, has the
input-referred noise Vn,rms. Vn,rms is the integrated noise voltage over the
recording bandwidth BWfe while consuming the total bias current IDD and is
shown at the input port of a front-end. To quantify and compare the
performance of different front-ends, the NEF is calculated using Vn,rms, BWfe,
and IDD. The NEF is defined by comparing the input-referred noise voltage of a
front-end to that of a bipolar junction transistor (BJT), assuming that the
bias current and bandwidth of a BJT are equal to IDD and BWfe, respectively,
as described in [6]. The NEF proposed in [6] is expressed as
$\textit{V\textsubscript{n,rms}}{\sqrt{2\textit{I\textsubscript{DD}}/(\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}})}}$, where UT is the thermal voltage
$kT/q$, $k$ is the Boltzmann constant, and $T$ is the absolute temperature.

###  A. BJT Noise Calculation

In this article, when comparing the noise voltage of a front-end to that of a
BJT, the calculation is conducted using either a single-ended common-emitter
stage or a differential common-emitter stage. The input-referred noise voltage
of a BJT is calculated as follows. Assuming that the noise voltage of a BJT is
considered only using the collector shot noise $i\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{c}}$ while neglecting
the base shot noise, base resistance, and flicker noise, the input noise
voltage of a single-ended common-emitter stage is expressed as $i\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{c}}/g\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{m}}$, where gm is the
BJT transconductance expressed as
$\textit{I\textsubscript{C}}/\textit{U\textsubscript{T}}=q\textit{I\textsubscript{C}}/kT$.
Note that $i\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{c}}=2q\textit{I\textsubscript{C}}$,
where $q$ and IC are the electron charge and collector bias current,
respectively. Therefore, the input-referred noise voltage of a single-ended
common-emitter stage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-bjt}}$ can be
derived as $i\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{c}}/g\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{m}}=2q\textit{I\textsubscript{C}}/g\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{m}}=2\textit{g\textsubscript{m}}kT/g\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{m}}=2kT/\textit{g\textsubscript{m}}$
and lead to

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-bjt}}$
$\displaystyle=\frac{2kT}{\textit{g\textsubscript{m}}}$ (1)
$\displaystyle=\frac{2kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}$
(2)

Since the noise voltage squared of a differential pair is twice that of a
single-ended stage as described in [7], the input-referred noise voltage of a
differential common-emitter stage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-bjt}}$ is twice
$V\hbox to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-bjt}}$
and is written as

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-bjt}}$
$\displaystyle=\frac{4kT}{\textit{g\textsubscript{m}}}$ (3)
$\displaystyle=\frac{4kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}$
(4)

Considering that the noise bandwidth can be approximated as $\pi/2$ times the
recording bandwidth in a one-pole recording front-end as described in [7], the
total input-referred noise voltage of each stage over the recording bandwidth
can be expressed as

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-bjt,tot}}$
$\displaystyle=\int_{0}^{\infty}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-bjt}}\,df$ (5)
$\displaystyle=\frac{2kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}\cdot{\textit{BW\textsubscript{bjt}}}\cdot\frac{\pi}{2}$
(6)

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-bjt,tot}}$
$\displaystyle=\int_{0}^{\infty}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-bjt}}\,df$ (7)
$\displaystyle=\frac{4kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}\cdot{\textit{BW\textsubscript{bjt}}}\cdot\frac{\pi}{2}$
(8)

where BWbjt is the noise bandwidth of the BJT. The total input-referred noise
voltage of each BJT stage can be rewritten as

$\displaystyle V\textit{\textsubscript{n,single-
bjt,tot}}=\sqrt{\frac{2kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}\cdot{\textit{BW\textsubscript{bjt}}}\cdot\frac{\pi}{2}}\,\,\,\text{and}\,\,\,V\textit{\textsubscript{n,diff-
bjt,tot}}=\sqrt{\frac{4kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}\cdot{\textit{BW\textsubscript{bjt}}}\cdot\frac{\pi}{2}}$
(9)

Note that a front-end achieves Vn,rms over BWfe while consuming IDD. Assuming
$\textit{BW\textsubscript{fe}}=\textit{BW\textsubscript{bjt}}$ and
$\textit{I\textsubscript{DD}}=\textit{I\textsubscript{C}}$ (in other words,
the bandwidth and bias current are equalized across the front-end and BJT to
compare the noise performance fairly while applying the same design
parameters), the noise performance of a fabricated front-end can be compared
to the noise voltage of the BJT as follows:

$\displaystyle\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,single-
bjt,tot}}}=V\textit{\textsubscript{n,rms}}\sqrt{\frac{\textit{I\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot{\textit{BW\textsubscript{fe}}}}}\,\,\text{and}\,\,\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,diff-
bjt,tot}}}=V\textit{\textsubscript{n,rms}}\sqrt{\frac{\textit{I\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot
2kT\cdot{\textit{BW\textsubscript{fe}}}}}$ (10)

In the calculation of Vn,single-bjt,tot and Vn,diff-bjt,tot, the collector
shot noise is only considered while ignoring the base shot noise, base
resistance, and flicker noise. However, in reality, Vn,rms is measured while
including the thermal and flicker noise.
$\textit{V\textsubscript{n,rms}}/\textit{V\textsubscript{n,single-bjt,tot}}$
and $\textit{V\textsubscript{n,rms}}/\textit{V\textsubscript{n,diff-bjt,tot}}$
mean how much better the noise performance of a front-end is achieved when
compared to a single BJT and a differential BJT, respectively, in the
equalized bandwidth and bias current. The concept of calculating
$\textit{V\textsubscript{n,rms}}/\textit{V\textsubscript{n,single-bjt,tot}}$
and $\textit{V\textsubscript{n,rms}}/\textit{V\textsubscript{n,diff-bjt,tot}}$
is the same as the NEF definition in [6]. However, the noise calculation is
conducted according to the single and differential types in this article.
Defining $\textit{NEF\textsubscript{single-
bjt}}=\frac{\textit{V\textsubscript{n,rms}}}{\textit{V\textsubscript{n,single-
bjt,tot}}}$ and $\textit{NEF\textsubscript{diff-
bjt}}=\frac{\textit{V\textsubscript{n,rms}}}{\textit{V\textsubscript{n,diff-
bjt,tot}}}$, $\textit{NEF\textsubscript{single-
bjt}}=\sqrt{2}\textit{NEF\textsubscript{diff-bjt}}$. Also, compared to the NEF
definition of
$\textit{V\textsubscript{n,rms}}{\sqrt{2\textit{I\textsubscript{DD}}/(\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}})}}$, the results from Eq. (10) can be
also expressed as $\textit{NEF\textsubscript{single-bjt}}=\sqrt{2}\text{NEF}$
and $\textit{NEF\textsubscript{diff-bjt}}=\text{NEF}$.

###  B. NEF Trends

Over the last decades, biopotential recording front-ends have been developed
using various circuit techniques, architectures, and technology nodes for
improving noise performance while consuming low power. These efforts have led
to advances in the NEF. Fig. 2 shows the overall NEF trends according to the
front-end architectures. Each NEF is expressed by using a square symbol and
the symbol size indicates a technology node used. The top of Fig. 2 summarizes
the symbol sizes representing the technology nodes ranging from 6 $\mu$m to 22
nm. As complementary metal-oxide semiconductor (CMOS) technology nodes have
scaled down, the performance of digital circuits has also advanced by
benefiting from scaling. However, most NEFs have not advanced as much as the
digital circuits have benefited from scaling, as discussed in [1] and shown in
Fig. 2. To improve the NEF, a front-end needs to achieve a low Vn,rms while
consuming a low IDD given BWfe. However, in most CMOS-based biopotential
recording front-ends, the thermal and flicker noise trades with the bias
current and transistor area. Therefore, the NEF improvement is a challenging
task that requires optimized design techniques.

Figure 2: NEF according to front-end architectures and technology nodes.

As shown in the bottom of Fig. 2, diverse front-end architectures have
achieved different NEFs. In particular, as discussed in Fig. 1, the capacitive
feedback front-end (CFFE) is overwhelmingly employed among the architectures
and various circuit techniques for the CFFE have been developed to reduce the
NEF. Also, to overcome the theoretical limit of NEF in the CFFE, discrete-time
amplification-based front-ends [4], [5] are developed. However, since the
number of discrete-time amplification-based front-ends is not yet sufficient,
it is classified as _Other_ in Fig. 2. Among numerous front-ends, the CFFEs
have mostly achieved the NEF between 1 to 10 using a variety of technology
nodes. Compared to the front-ends which require an independent analog-to-
digital converter (ADC), a direct conversion front-end (DCFE) digitizes the
input signal directly while incorporating the function of analog-to-digital
conversion into its architecture. The DCFE is the second most used
architecture after the CFFE, as shown in Fig. 1, and achieves the NEF between
1 to 10, mostly using sub-0.35 $\mu$m nodes.

Although numerous biopotential recording front-ends have been developed since
the 1970s, the concept of NEF [6] was presented in the 1980s and there are
also many literatures that do not specify the NEF. Therefore, NEFs noted in
Fig. 2 do not reflect all front-ends shown in Fig. 1.

##  III. POWER EFFICIENCY FACTOR

###  A. Motivation

Revisiting the definition of NEF,
$\textit{V\textsubscript{n,rms}}{\sqrt{2\textit{I\textsubscript{DD}}/(\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}})}}$, the only parameter related to
power consumption is IDD while neglecting the supply voltage VDD. Therefore,
the NEF can provide a fair performance comparison between different front-ends
when the front-ends being compared employ the same VDD. In other words,
although the NEF can compare fairly the current-noise efficiency between the
front-ends, the power-noise efficiency between different front-ends cannot be
provided fairly using the NEF if the front-ends are developed using different
supply voltages. To overcome this limit, the PEF was developed in [8]. The PEF
is calculated by squaring the NEF and multiplying it by VDD, meaning
$\text{PEF}=\text{NEF}\textsuperscript{2}\textit{V\textsubscript{DD}}=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\frac{2\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot\textit{BW\textsubscript{fe}}}=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\frac{2\textit{P\textsubscript{tot}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot\textit{BW\textsubscript{fe}}}$, where Ptot is the total power
consumption of a front-end. The PEF contains
$\textit{P\textsubscript{tot}}=\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}$,
allowing us to compare the power-noise efficiency between different front-
ends.

Rethinking the definition of PEF as discussed in [8], the PEF is defined by
comparing $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\textit{P\textsubscript{tot}}$
to $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}\textit{P\textsubscript{bjt,tot}}$,
where $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}$ and
Pbjt,tot are the input-referred noise voltage and power consumption of the
BJT, respectively. As in the NEF, the input-referred noise voltage of the BJT
is calculated using the common-emitter stage. Then, the PEF can be re-
expressed as

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{P\textsubscript{tot}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}\cdot\textit{P\textsubscript{bjt,tot}}}$
$\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
(11) $\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{bjt}}}}{2\textit{I\textsubscript{C}}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
(12)

where IC and VDD,bjt are the collector bias current and supply voltage of the
BJT, respectively. Note that $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}$ is
calculated from the common-emitter stage using only the collector shot noise
while neglecting the base shot noise, base resistance, and flicker noise.
Therefore, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}$ of Eq.
(11) can be expressed as $\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{bjt}}}}{2\textit{I\textsubscript{C}}}$ as
presented in [6].

$V\hbox to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,bjt,tot}}$ is
calculated by dividing the collector shot noise by the BJT transconductance
and integrating it over the noise bandwidth
$\textit{BW\textsubscript{bjt}}\cdot\frac{\pi}{2}$. Also, the front-end
bandwidth BWfe is equalized to the BJT bandwidth BWbjt for obtaining a
normalized efficiency factor over the BJT, meaning
$\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{fe}}$. Assuming the
PEF is expressed using the normalized 1 V supply voltage of the BJT (VDD,bjt =
1 V) as discussed in [9], [10], Eq. (12) can be summarized as

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}}}{2}\cdot 1}$ $\displaystyle=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\frac{2\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}}}$ (13)
$\displaystyle=\text{NEF}\textsuperscript{2}\textit{V\textsubscript{DD}}$ (14)

As shown in the equations above, the PEF is explained as follows. The product
of the input-referred noise and power consumption is normalized with respect
to the common-emitter stage. Normalization is carried out assuming that the
BJT is driven using a 1 V supply voltage (VDD,bjt = 1 V). The bandwidth is
equalized across the front-end and common-emitter stage
($\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{fe}}$). Therefore,
using the following assumptions of VDD,bjt = 1 V and
$\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{fe}}$, Eq. (12) is
reduced to Eqs. (13) and (14). In reality, Eqs. (13) and (14) have been widely
employed as the FoM for fairly comparing the performance of diverse
biopotential recording front-ends, even if the front-ends achieve different
Vn,rms over BWfe while consuming the power of IDDVDD.

The procedure of Eqs. (11) and (12) can be applied to either a single-ended
common-emitter stage or a differential common-emitter stage by using the BJT
noise models in Eq. (9). Assuming that $\textit{V\textsubscript{DD,bjt}}=$ 1 V
and $\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{fe}}$, the
following equations provide the power efficiency factors with respect to a
single-ended common-emitter stage and a differential common-emitter stage:

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{P\textsubscript{tot}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-
bjt,tot}}\cdot\textit{P\textsubscript{single-bjt,tot}}}$
$\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
2kT\cdot{\textit{BW\textsubscript{bjt}}}}{2\textit{I\textsubscript{C}}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}\,\,\,\,\,\,\,\,\text{Single-
Ended Stage}$ (15) $\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
2kT\cdot\textit{BW\textsubscript{fe}}}{2}\cdot 1}$ (16) $\displaystyle=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\frac{\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot{\textit{BW\textsubscript{fe}}}}$
(17) $\displaystyle=NEF\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{single-
bjt}}\textit{V\textsubscript{DD}}$ (18)

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{P\textsubscript{tot}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-
bjt,tot}}\cdot\textit{P\textsubscript{diff-bjt,tot}}}$
$\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{bjt}}}}{2\textit{I\textsubscript{C}}}\cdot
2\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}\,\,\,\,\,\,\,\,\text{Differential
Stage}$ (19) $\displaystyle=\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot\textit{BW\textsubscript{fe}}}{1}\cdot 1}$ (20) $\displaystyle=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\frac{\textit{I\textsubscript{DD}}\textit{V\textsubscript{DD}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot
4kT\cdot{\textit{BW\textsubscript{fe}}}}$ (21)
$\displaystyle=\frac{1}{2}{NEF\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{diff-
bjt}}}\textit{V\textsubscript{DD}}$ (22)

where Psingle-bjt,tot and Pdiff-bjt,tot mean the power consumption in a
single-ended common-emitter stage and a differential common-emitter stage,
respectively. Since the bias current of a differential stage consumes two
times the current of a single stage, the bias current of Eq. (19) is twice
that of Eq. (15). When Eqs. (18) and (22) are defined as PEFsingle-bjt and
PEFdiff-bjt, respectively, PEFsingle-bjt and PEFdiff-bjt can be given as
follows

PEFsingle-bjt $\displaystyle=NEF\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{single-
bjt}}\textit{V\textsubscript{DD}}$ (23)
$\displaystyle=2\text{NEF}\textsuperscript{2}\textit{V\textsubscript{DD}}$
(24)

PEFdiff-bjt $\displaystyle=\frac{1}{2}{NEF\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{diff-
bjt}}\textit{V\textsubscript{DD}}}$ (25)
$\displaystyle=\frac{1}{2}\text{NEF}\textsuperscript{2}\textit{V\textsubscript{DD}}$
(26)

where $\textit{NEF\textsubscript{single-bjt}}=\sqrt{2}\text{NEF}$ and
$\textit{NEF\textsubscript{diff-bjt}}=\text{NEF}$. Then, the power efficiency
factors across the single and differential stages can be summarized as
$\textit{PEF\textsubscript{single-bjt}}=4\textit{PEF\textsubscript{diff-
bjt}}$.

###  B. PEF Trends

As discussed in equations from Eq. (11) to Eq. (14), the PEF is simply
calculated as NEF2VDD and has been widely employed as the FoM along with the
NEF. Fig. 3 presents the overall PEF trends over the last decades. As already
discussed in the NEF trends shown in Fig. 2, PEFs noted in Fig. 3 also do not
reflect all the front-ends shown in Fig. 1 due to the lack of information in
prior literature. Note that the concept of PEF [8] was developed in the 2010s,
which came out long after the NEF [6] was introduced. The top of Fig. 3
describes the symbol sizes according to the technology nodes ranging from 22
nm to 6 $\mu$m. The bottom of Fig. 3 summarizes the overall PEF trends
according to the front-end architectures shown in Fig. 1.

Compared to the NEF trends, the PEFs achieved using the CFFE are mostly
distributed from 1 to 100 (Fig. 3), while the NEFs achieved using the CFFE
mostly range between 1 to 10 (Fig. 2). In the design of biopotential recording
front-ends, lower values of both NEF and PEF indicate better performance in
current-noise efficiency and power-noise efficiency, respectively. Therefore,
many front-end designers have tried to obtain lower values of both NEF and
PEF.

Considering that the PEF is obtained by squaring the NEF and multiplying it by
a supply voltage, a higher PEF is achieved if the NEF is larger than 1, which
is not a preferable direction in the front-end design. On the other hand, even
if a supply voltage is somewhat higher than 1 V, a lower PEF can be achieved
if the NEF is less than 1. Also, for achieving a lower PEF, another way
instead of lowering the NEF is to drive the front-end using a sub-1 V supply
voltage.

However, lowering the NEF and supply voltage in a front-end design could be a
challenging task considering a reliable circuit operation and performance
degradation. For example, the chopper in the CFFE can reduce the input-
referred noise and eventually lower the NEF. However, the chopping frequency
reduces the input impedance of a front-end, which is related to the CMRR
degradation. Also, the DC offsets are modulated by the chopping frequency,
thereby requiring additional devices to suppress the modulated offsets and
eventually increasing the design area. Likewise, a design technique to improve
a specific performance may be associated with other performance degradation.

Figure 3: PEF according to front-end architectures and technology nodes.

##  IV. MAPPING OF TECHNOLOGY NODES, NEF, AND PEF

When using a biopotential recording front-end in vivo, weak voltage signals
must be processed while minimizing signal contamination, and the heat
generated in the circuits must be also minimized to prevent cell damage.
Therefore, a front-end must be implemented to have low noise while consuming
low power, which means that both NEF and PEF must be also achieved as lower
values. In this section, the overall performance summary including the
technology nodes, NEF, and PEF is presented for the biopotential recording
front-ends developed over the last decades. Then, the performance summary of
each front-end architecture is also presented.

###  A. Mapping of Overall Front-End Architectures

When revisiting the equation of
$\text{PEF}=\text{NEF}\textsuperscript{2}\textit{V\textsubscript{DD}}$, even
if the NEF is reduced thanks to circuit techniques, the PEF could be higher if
a higher VDD is used. It means that the power-noise efficiency does not
advance even if the current-noise efficiency improves. Also, even if the NEF
is somewhat degraded due to a high bias current or input noise, the PEF could
advance if a lower VDD is used. It means that the power-noise efficiency
advances even if the current-noise efficiency is degraded. In fact, the
intuitive way to reduce the power consumption of circuits is to use a lower
VDD. However, using a lower VDD could be limited when considering the bias
conditions of transistors, dynamic range, etc.

Ultimately, considering a front-end used in vivo, both NEF and PEF must be
reduced, which means that both current-noise efficiency and power-noise
efficiency must be improved. Therefore, to figure out how well the current-
noise efficiency and power-noise efficiency are balanced rather than being
biased to one side, $|\text{PEF}-\text{NEF}|$ is employed, which means the
difference between NEF and PEF. Note that when the absolute value sign is not
used in $|\text{PEF}-\text{NEF}|$, the positive value of
$\text{PEF}-\text{NEF}$ means the power-noise efficiency is higher than the
current-noise efficiency, and the negative value of $\text{PEF}-\text{NEF}$
means the current-noise efficiency is better than the power-noise efficiency.
But eventually, achieving a lower $|\text{PEF}-\text{NEF}|$ is the preferable
direction in a front-end design.

Fig. 4 presents the mapping of the front-end performance by using the
technology nodes, NEF, and PEF for all architectures shown in Fig. 1. The
x-axis indicates a numeric scale. The y-axis includes five categories of the
technology node, NEF, PEF, $|\text{PEF}-\text{NEF}|$, and VDD. Note that VDD
is obtained through the reverse calculation using
$\text{PEF}/\text{NEF}\textsuperscript{2}$. Each blue line indicates the
performance mapping with respect to a single front-end (Fig. 4). In other
words, five data points are connected according to the corresponding values
held by a front-end. Lowering NEF, PEF, and $|\text{PEF}-\text{NEF}|$ makes
the front-end suitable for use in systems where the power and noise must be
strictly regulated.

Figure 4: Performance mapping across the overall front-end architectures.

###  B. Mapping According to Architectures

Compared to Fig. 4 describing the mapping across the overall architectures
shown in Fig. 1, Fig. 5 presents the performance mappings depending on the
front-end architectures. Note that all blue lines shown in Fig. 4 change to
gray lines, and red lines are drawn to represent each architecture as shown in
Fig. 5. As shown in Figs. 1 and 5, among the architectures that constitute
biopotential recording front-ends, the CFFE has been overwhelmingly employed,
and the DCFE is the second most used architecture. In reality, the number of
third and fourth most used architectures shown in Fig. 1 does not reflect
completely the number of architectures shown in Fig. 5 due to the following
reason. Many research papers presenting the front-ends do not specify either
NEF or supply voltage, or neither. If the NEF and supply voltage are noted but
the PEF is not noted in prior research papers, the PEF is calculated using
NEF2VDD in this article.

In particular, the diverse circuit techniques for reducing the input-referred
noise while reducing the supply voltage have been developed based on the CFFE,
resulting in lower values in NEF, PEF, and $|\text{PEF}-\text{NEF}|$. Also,
while many CFFEs have been developed using a wide range of technology nodes,
most DCFEs are developed using scaled-down technology nodes than those of
CFFEs (Fig. 5).

Figure 5: Performance mapping for each front-end architecture.

###  C. Noise Analysis of MMRS

The multi-channel multi-stage recording system (MMRS) sharing a single ADC is
a widely used system architecture for an area-efficient design. Assuming that
the input signal is digitized after two amplification stages, Fig. 6(a) shows
the general architecture of the MMRS with noise sources. The input signal is
processed through a recording chain from the first amplification stage
$A\textsubscript{1}$ to the ADC. Even if the overall input-referred noise
voltage is dominated by $A\textsubscript{1}$ in a whole recording chain,
depending on the gain of the preceding stages, the input noise could be
slightly influenced by the subsequent stages, e.g., the second amplification
stage $A\textsubscript{2}$, buffer, and ADC. If $A\textsubscript{2}$ has
sufficient capability for driving the ADC, the buffer can be left out.
Considering all circuit blocks shown in Fig. 6(a), the overall input-referred
noise voltage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}$ with respect
to a single recording chain is obtained as

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}$
$\displaystyle=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}$
(27)

where $G\textsubscript{1}$ and $G\textsubscript{2}$ are voltage gains of
$A\textsubscript{1}$ and $A\textsubscript{2}$, respectively. The noise sources
shown in Fig. 6(a) indicate the input-referred noise voltage of each circuit
block as follows: (1) the first amplification stage $A\textsubscript{1}$,
$V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}$;
(2) the second amplification stage $A\textsubscript{2}$, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}$;
(3) the ADC driving buffer, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}$; and (4) the
ADC, $V\hbox to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}$.
Each noise source is divided by the gain of the preceding stages to obtain the
overall input-referred noise voltage in a recording chain. Therefore, assuming
that the buffer gain is set to unity, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}$ is divided by
$\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}$. Eq. (27) can be
approximated as $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}$
if $G\textsubscript{1}G\textsubscript{2}$ and $G\textsubscript{1}$ are
sufficiently high, e.g., $G\textsubscript{1}=100$ and $G\textsubscript{2}=10$.
Assuming that $A\textsubscript{1}$ and $A\textsubscript{2}$ are developed as
the CFFE, the way to lower the input noise is to increase each gain, and in
particular, increasing $G\textsubscript{1}$ can effectively reduce $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}$. However,
increasing $G\textsubscript{1}$ leads to a large design area of
$A\textsubscript{1}$, which encounters a trade-off between the noise and area.
Note that each circuit block shown in Fig. 6(a) draws the current as follows:
IDD,a1 from $A\textsubscript{1}$, IDD,a2 from $A\textsubscript{2}$, IDD,buf
from the buffer, and IDD,adc from the ADC.

Figure 6: Simplified circuit diagrams including the noise sources: (a) multi-
channel multi-stage recording system, (b) two-stage amplifier with different
supply voltages, and (c) direct conversion front-end that performs delta-sigma
operations.

Assuming a single recording chain in Fig. 6(a) achieves the bandwidth BWch
while consuming the total bias current IDD,ch
($=\textit{I\textsubscript{DD,a}}\textsubscript{1}+\textit{I\textsubscript{DD,a}}\textsubscript{2}+\textit{I\textsubscript{DD,buf}}+\textit{I\textsubscript{DD,adc}}$),
the input-referred noise voltage of a single chain can be compared to that of
a single-ended common-emitter stage as follows

$\displaystyle\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,single-
bjt,tot}}}$ $\displaystyle=\sqrt{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}}\Bigg{/}{\sqrt{\frac{2kT\cdot\textit{U\textsubscript{T}}}{\textit{I\textsubscript{C}}}\cdot{\textit{BW\textsubscript{bjt}}}\cdot\frac{\pi}{2}}}$
(28)

where $V\textit{\textsubscript{n,single-bjt,tot}}$ and
$V\textit{\textsubscript{n,rms}}$ are derived from Eqs. (9) and (27),
respectively. When equalizing the bandwidth and total bias current of the BJT
to those of a single recording chain,
$\textit{I\textsubscript{C}}=\textit{I\textsubscript{DD,ch}}$ and
$\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{ch}}$. Therefore, Eq.
(28) can be rewritten as

$\displaystyle\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,single-
bjt,tot}}}$ $\displaystyle=\sqrt{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\frac{\textit{I\textsubscript{DD,ch}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot\textit{BW\textsubscript{ch}}}}$
(29)

As calculated in Eqs. (28) and (29), the noise voltage of a single chain can
be also compared to that of a differential common-emitter stage by using Eq.
(9). After equalizing the bandwidth and total bias current across the single
chain and differential BJT, the following equation is obtained:

$\displaystyle\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,diff-
bjt,tot}}}$ $\displaystyle=\sqrt{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\frac{\textit{I\textsubscript{DD,ch}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{2kT}\cdot\textit{BW\textsubscript{ch}}}}$
(30)

The product of the noise voltage and power consumption of a single chain can
be compared to that of the BJT. All supply voltages used in a single chain are
equal to VDD,ch. Assuming that the BJT is driven using a 1-V supply voltage
($\textit{V\textsubscript{DD,bjt}}=$ 1 V) and
$\textit{BW\textsubscript{bjt}}=\textit{BW\textsubscript{ch}}$, the power-
noise efficiency between a single recording chain and a single-ended common-
emitter stage is given by

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{I\textsubscript{DD,ch}}\textit{V\textsubscript{DD,ch}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-
bjt,tot}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
$\displaystyle=\frac{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\textit{I\textsubscript{DD,ch}}\textit{V\textsubscript{DD,ch}}}{\frac{\pi\cdot\textit{U\textsubscript{T}}\cdot
2kT\cdot{\textit{BW\textsubscript{bjt}}}}{2\textit{I\textsubscript{C}}}\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
(31) $\displaystyle=\frac{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\textit{I\textsubscript{DD,ch}}\textit{V\textsubscript{DD,ch}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot{\textit{BW\textsubscript{ch}}}}$
(32)

If the circuit blocks in a single chain are driven using different supply
voltages to optimize the power consumption, the total power consumption of a
single chain must be expressed using the individual supply voltage of each
circuit block. Therefore, Eq. (32) can be rewritten as

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\text{Channel
Power}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-
bjt,tot}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
$\displaystyle=\frac{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\big{(}\textit{P\textsubscript{a}}\textsubscript{1}+\textit{P\textsubscript{a}}\textsubscript{2}+\textit{P\textsubscript{buf}}+\textit{P\textsubscript{adc}}\big{)}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot{\textit{BW\textsubscript{ch}}}}$
(33)

where
$\textit{P\textsubscript{a}}\textsubscript{1}=\textit{I\textsubscript{DD,a}}\textsubscript{1}\textit{V\textsubscript{DD,a}}\textsubscript{1}$,
$\textit{P\textsubscript{a}}\textsubscript{2}=\textit{I\textsubscript{DD,a}}\textsubscript{2}\textit{V\textsubscript{DD,a}}\textsubscript{2}$,
$\textit{P\textsubscript{buf}}=\textit{I\textsubscript{DD,buf}}\textit{V\textsubscript{DD,buf}}$,
and
$\textit{P\textsubscript{adc}}=\textit{I\textsubscript{DD,adc}}\textit{V\textsubscript{DD,adc}}$.
Also, by expanding Eq. (33) in a differential way while using Eq. (9) and
$\textit{V\textsubscript{DD,bjt}}=$ 1 V, the power-noise efficiency between a
single chain and a differential common-emitter stage can be obtained as

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\text{Channel
Power}}{V\hbox to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,diff-
bjt,tot}}\cdot 2\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
$\displaystyle=\frac{\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}\big{(}\textit{P\textsubscript{a}}\textsubscript{1}+\textit{P\textsubscript{a}}\textsubscript{2}+\textit{P\textsubscript{buf}}+\textit{P\textsubscript{adc}}\big{)}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{4kT}\cdot{\textit{BW\textsubscript{ch}}}}$
(34)

In the calculation of Eq. (34), the bias current of the differential BJT is
twice that of the single BJT shown in Eq. (31), therefore, the bias current of
$2\textit{I\textsubscript{C}}$ is used in the denominator of Eq. (34). As
shown in Eqs. (33) and (34), low noise and low power consumption are required
to achieve better power-noise efficiency. To accomplish this goal, the MMRS
shown in Fig. 6(a) can be designed as follows: (1) $G\textsubscript{1}$ and
$G\textsubscript{2}$ need to be high enough to ignore the noise contributed by
the subsequent stages; (2) for optimizing the trade-off between the noise and
power in $A\textsubscript{1}$, IDD,a1 needs to be greatly increased while
maintaining a low VDD,a1; and (3) the subsequent stages after
$A\textsubscript{1}$ are driven using lower bias currents and higher supply
voltages.

Most biopotential recording front-ends can be designed employing a two-stage
amplifier shown in Fig. 6(b), e.g., $A\textsubscript{1}$ and
$A\textsubscript{2}$ can be designed as a two-stage amplifier. For simplicity,
the two-stage amplifier shown in Fig. 6(b) is drawn as a single-ended
structure, even if the practical amplifier is designed differentially. If the
circuit blocks constituting the front-ends dominate the overall noise voltage,
those blocks can be designed while using individually different supply
voltages to optimize the noise and power consumption [10], (e.g., the low
VDD,m1 and high IDD,m1 are employed for the input stage $M\textsubscript{1}$,
and the high VDD,m2 and low IDD,m2 are employed for the output stage
$M\textsubscript{2}$ as shown in Fig. 6(b)). Generally, $M\textsubscript{1}$
carries a large IDD,m1 for reducing the thermal noise while having a large
area for the low flicker noise. On the other hand, $M\textsubscript{2}$ can be
designed to carry a small IDD,m2 since the noise of $M\textsubscript{2}$ can
be negligible when dividing it by a high gain of $M\textsubscript{1}$.

The equations above are obtained assuming that the buffer and ADC are assigned
to only a single channel, e.g, the buffer and ADC digitize only Vin1 by
sustaining the multiplexer (MUX) fixed to Vin1 in Fig. 6(a). This means that
IDD,buf and IDD,adc are set to the extent that only a single channel is
driven. On the other hand, if an ADC is designed to perform Nyquist-rate
operations, such as a successive approximation register ADC, a wider bandwidth
of the ADC and buffer is required to access all multiple channels.
Accordingly, IDD,buf and IDD,adc must increase to widen the bandwidth as the
number of channels increases. Therefore, in the buffer and ADC in Fig. 6(a),
the effective current consumption per single channel needs to be expressed
considering the number of total channels:

$\displaystyle\textit{I\textsubscript{DD,buf,eff}}=\frac{\textit{I\textsubscript{DD,buf}}}{N}\,\,\,\,\,\,\,\text{and}\,\,\,\,\,\,\,\textit{I\textsubscript{DD,adc,eff}}=\frac{\textit{I\textsubscript{DD,adc}}}{N}$
(35)

where IDD,buf and IDD,adc are the total bias current consumed by the buffer
and ADC, respectively, to access all channels. IDD,buf,eff and IDD,adc,eff
refer to the effective current consumption per single channel of the buffer
and ADC, respectively, considering the total number of channels $N$. Applying
the effective current consumption per single channel to Eqs. (29) and (33),
current-noise efficiency and power-noise efficiency with respect to a single-
ended common-emitter stage are modified as

$\displaystyle\frac{V\textit{\textsubscript{n,rms}}}{V\textit{\textsubscript{n,single-
bjt,tot}}}$ $\displaystyle=\sqrt{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}}$
$\displaystyle\,\,\,\,\,\,\,\,\,\times\sqrt{\frac{\textit{I\textsubscript{DD,a}}\textsubscript{1}+\textit{I\textsubscript{DD,a}}\textsubscript{2}+\frac{\textit{I\textsubscript{DD,buf}}}{N}+\frac{\textit{I\textsubscript{DD,adc}}}{N}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot\textit{BW\textsubscript{ch}}}}$
(36)

$\displaystyle\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,rms}}\cdot\textit{P\textsubscript{ch,eff}}}{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,single-
bjt,tot}}\cdot\textit{I\textsubscript{C}}\textit{V\textsubscript{DD,bjt}}}$
$\displaystyle=\Bigg{[}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{1}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,a}}\textsubscript{2}}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textsubscript{1}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,buf}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}+\frac{V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}}{\big{(}G\textsubscript{1}G\textsubscript{2}\big{)}^{2}}\Bigg{]}$
$\displaystyle\,\,\,\,\,\,\,\,\,\times\frac{\textit{P\textsubscript{ch,eff}}}{\pi\cdot\textit{U\textsubscript{T}}\cdot{kT}\cdot{\textit{BW\textsubscript{ch}}}}$
(37)

where $\textit{V\textsubscript{DD,bjt}}=$ 1 V and BWch is the overall
bandwidth from $A\textsubscript{1}$ to the ADC while consuming the effective
channel power Pch,eff. Also, using Eqs. (30) and (34), the effective current
consumption in Eq. (35) can be extended to a differential common-emitter
stage. Considering the total number of channels $N$ and the supply voltage of
each block, Pch,eff is expressed as

$\displaystyle\textit{P\textsubscript{ch,eff}}=\textit{I\textsubscript{DD,a}}\textsubscript{1}\textit{V\textsubscript{DD,a}}\textsubscript{1}+\textit{I\textsubscript{DD,a}}\textsubscript{2}\textit{V\textsubscript{DD,a}}\textsubscript{2}+\frac{\textit{I\textsubscript{DD,buf}}}{N}\textit{V\textsubscript{DD,buf}}+\frac{\textit{I\textsubscript{DD,adc}}}{N}\textit{V\textsubscript{DD,adc}}$
(38)

###  D. Noise Analysis of DCFE

Similar to the method for optimizing circuit design in terms of noise and
power consumption as discussed in Figs. 6(a) and (b), a direct conversion
front-end can be also designed using different supply voltages for analog and
digital domains as shown in Fig. 6(c). Generally, the digital circuits can be
driven using a low supply voltage VDVDD while the analog circuits are driven
using a relatively high supply voltage VAVDD to ensure the operating point and
dynamic range [11], [12]. Assuming that the gain of the analog circuits in
Fig. 6(c) is Ganalog, the overall noise voltage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,x}}$ at the quantizer
input node is expressed as

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,x}}$
$\displaystyle=G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}$ (39)

where $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}$ is the
input noise voltage of the analog circuits, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}$ is the output
noise voltage of the digital-to-analog converter (DAC), and $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}$ is the
quantization noise voltage in Fig. 6(c). After solving the noise transfer
function of Fig. 6(c) and applying it to $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,x}}$ appearing at the
quantizer input node, the output noise voltage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}$ is expressed
as

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}$
$\displaystyle=\Big{[}G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\Big{]}\bigg{(}\frac{1}{1+\textit{G\textsubscript{analog}}}\bigg{)}^{2}$
(40)

To conduct a fair noise comparison for different front-ends, an output noise
voltage needs to be divided by the conversion gain as conducted in Eq. (27).
Therefore, $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}$ is divided by
the signal transfer function of Fig. 6(c). Then, the input-referred noise
voltage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}$ of a
direct conversion front-end is obtained as follows

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}$
$\displaystyle=\Bigg{[}\Big{[}G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\Big{]}\bigg{(}\frac{1}{1+\textit{G\textsubscript{analog}}}\bigg{)}^{2}\Bigg{]}\Bigg{/}\bigg{(}\frac{\textit{G\textsubscript{analog}}}{1+\textit{G\textsubscript{analog}}}\bigg{)}^{2}$
(41) $\displaystyle=\Big{[}G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\Big{]}\bigg{(}{\frac{1}{\textit{G\textsubscript{analog}}}}\bigg{)}^{2}$
(42) $\displaystyle=V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\frac{1}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}}$ (43)

As seen in Eq. (43), the overall input-referred noise voltage of a DCFE can be
obtained by dividing the quantization noise by the gain of the analog circuits
and adding it to the input noise sources of the analog domain shown in Fig.
6(c). Assuming that $G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}$ is high
enough, the input noise voltage $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}$ can be
approximated as $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}$. Also, as
calculated in Eqs. (15) and (19), the power-noise efficiency of a DCFE can be
compared to different front-ends using the product of the noise voltage and
power consumption as follows

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}\cdot\textit{P\textsubscript{DCFE}}$
$\displaystyle=\bigg{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\frac{1}{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}}\bigg{)}\big{(}\textit{I\textsubscript{AVDD}}\textit{V\textsubscript{AVDD}}+\textit{I\textsubscript{DVDD}}\textit{V\textsubscript{DVDD}}\big{)}$
(44)

where PDCFE is the total power consumption of a DCFE shown in Fig. 6(c). IAVDD
and IDVDD are the overall bias currents consumed by the analog domain and
digital domain, respectively. Generally, in the analog domain, IAVDD can be
increased until the thermal noise level is reduced to a satisfactory level.
VAVDD is chosen considering the device operating point and required dynamic
range. In the digital domain, IDVDD is determined by a clock speed (or
operating frequency). VDVDD can be set relatively lower than VAVDD and reduced
to a level that guarantees reliable operations of the logic gates. Revisiting
Eq. (40), $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}$ can be
rearranged as follows

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}$
$\displaystyle=\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}\frac{G\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{analog}}}{\big{(}1+\textit{G\textsubscript{analog}}\big{)}^{2}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}\frac{1}{\big{(}1+\textit{G\textsubscript{analog}}\big{)}^{2}}$
(45)

Assuming that Ganalog is high enough in Eq. (45), the second term can be
negligible and the first term is approximated as $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}$. Eventually,
assuming Ganalog is sufficiently high, the following result is obtained from
Eqs. (43) and (45):

$\displaystyle V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}\approx
V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}\approx\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}$ (46)

This result can be also explained through the basic operation of a simple
delta-sigma ($\Delta\Sigma$) modulator. To obtain the transfer functions, Fig.
7 redraws Fig. 6(c) including the noise source Qn, input signal $X$, and
output signal $Y$. Qn refers to the overall noise voltage appearing at the
input node of the quantizer, which is the sum taking into account all noise
sources of the loop filter, quantizer, and DAC. Note that Fig. 7 illustrates a
conceptually simplified diagram of DCFE operating in the voltage domain,
although an actual DCFE is designed complexly using the elaborately designed
blocks such as the loop filter, DAC, and quantizer to achieve high
performance. However, this simplified diagram is helpful to understand the
noise properties at the input and output nodes of a DCFE.

In the feedback path in Fig. 7, the DAC copies $Y$ accurately to the negative
feedback node. Then, $X-Y$ is generated at the input node of the loop filter.
The loop filter is interchangeably used with the analog circuits as shown in
Fig. 7. Combining the signal and noise source, the output signal $Y$ can be
generated and organized as follows:

$\displaystyle Y$
$\displaystyle=\textit{G\textsubscript{analog}}\big{(}X-Y\big{)}+\textit{Q\textsubscript{n}}$
(47) $\displaystyle Y\big{(}1+\textit{G\textsubscript{analog}}\big{)}$
$\displaystyle=\textit{G\textsubscript{analog}}X+\textit{Q\textsubscript{n}}$
(48) $\displaystyle Y$
$\displaystyle=\frac{\textit{G\textsubscript{analog}}}{1+\textit{G\textsubscript{analog}}}X+\frac{1}{1+\textit{G\textsubscript{analog}}}\textit{Q\textsubscript{n}}$
(49)

where $\textit{G\textsubscript{analog}}/(1+\textit{G\textsubscript{analog}})$
is the signal transfer function and $1/(1+\textit{G\textsubscript{analog}})$
is the noise transfer function, which are used in Eqs. (40) and (41). These
equations are well-known and widely used to describe the operation of a
$\Delta\Sigma$ modulator. Interestingly, the output noise form of Eq. (45) is
the same as the output signal form of Eq. (49): (1) the sum of noise sources,
$V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}$, at the DCFE
input is converted by
$\textit{G\textsubscript{analog}}/(1+\textit{G\textsubscript{analog}})$, and
(2) the noise source $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,qtz}}$ at the
quantizer input is converted by $1/(1+\textit{G\textsubscript{analog}})$.

Figure 7: Basic operation of a DCFE including a noise source.

As shown in Eq. (49) and Fig. 7, the input signal $X$ is converted to the
output signal $Y$ by the gain of
$Y/X(=\textit{G\textsubscript{analog}}/(1+\textit{G\textsubscript{analog}}))$.
This means that $X$ is exactly copied to $Y$ if Ganalog is sufficiently high.
The amplitude of $Y$ is therefore equal to that of $X$. In terms of the noise
perspective between the input and output nodes, the amplitude of the output
noise is the same as the amplitude of the input noise if Ganalog is high
enough, resulting in $V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DCFE,in}}\approx
V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,Dout}}\approx\big{(}V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,analog}}+V\hbox
to0.0pt{\textsuperscript{2}\hss}\textit{\textsubscript{n,DAC}}\big{)}$.
Similar to the noise properties of MMRS, the input noise of a DCFE is also
dominated by the circuit blocks placed closest to the input signal if the gain
of the preceding stage is sufficiently high, e.g., Ganalog of DCFE and
$G\textsubscript{1}G\textsubscript{2}$ of MMRS. However, in practical front-
end design, Ganalog is a finite value rather than an infinite value.
Therefore, the quantization noise cannot be ignored in the input and output
noise voltages shown in Eqs. (43) and (45).

###  E. Other Design Parameters

Although the current-noise efficiency and power-noise efficiency are only
discussed in this article, there are still many other design parameters that
need to be considered in the front-end design. For example, (1) a wide dynamic
range of the front-end is essential to measure weak voltage signals and
artifacts having a large amplitude, (2) a high input impedance of the front-
end is required considering a high source impedance from the electrodes, (3) a
design area of the single front-end needs to decrease for miniaturization of
implantable devices, etc.

Fig. 8 summarizes the key design parameters that need to be considered in the
biopotential recording front-end design. The NEF describing the current-noise
efficiency of a front-end is developed using the input noise, bias current,
and bandwidth. The PEF is obtained by combining the supply voltage with the
parameters used to calculate the NEF. Most of the parameters shown in Fig. 8
encounter trade-offs, presenting challenges in the high-performance front-end
design.

For example, a low-noise front-end is essential to detect a weak voltage
signal and a certain amount of bias current is required, which is then related
to the increase in power consumption. As one way to reduce the power
consumption while maintaining low noise, the supply voltage is reduced to a
certain level that guarantees the operating point of transistors. However,
reducing the supply voltage could degrade the dynamic range. Also, to achieve
a low noise while consuming a small current, the chopper can be used. However,
the chopper could degrade the input impedance and require additional circuit
blocks to suppress signal distortion caused by the chopper. For these reasons,
improving the performance of a specific parameter could trade with other
performances, and a comprehensive design strategy is required considering
target performance and applications.

Figure 8: Key design parameters of the biopotential recording front-end.

##  V. CONCLUSION

In this article, NEF and PEF are discussed from the equation derivation to the
trend survey. Both current-noise efficiency and power-noise efficiency are
obtained with respect to a single-ended common-emitter stage and a
differential common-emitter stage. To provide a comprehensive performance
comparison of the front-ends, the performance mapping is developed using the
design parameters of the technology node, NEF, PEF, $|\text{PEF}-\text{NEF}|$,
and VDD. Using $|\text{PEF}-\text{NEF}|$ provides that how well a front-end
balances between current-noise efficiency and power-noise efficiency, in other
words, how biased a front-end is between current- and power-noise
efficiencies. Also, the performance mapping of each front-end architecture is
presented.

In modern biomedical engineering, especially in the field of biopotential
recording, multi-channel multi-stage recording systems have been widely
employed to handle a significant amount of bioelectric signals while
maximizing system operation efficiency. As semiconductor technology advances
and better front-end performance is required, the use of the DCFE has also
increased. The noise analysis is therefore conducted for the multi-channel
multi-stage recording system and DCFE. Finally, this article briefly addresses
the key design parameters to consider in the front-end design, even though
this article does not mention in detail beyond NEF and PEF.

## References

  * [1] T. Lee and M. Je, “Trend investigation of biopotential recording front-end channels for invasive and non-invasive applications,” _arXiv preprint arXiv:2305.13463_ , pp. 1–31, May 2023.
  * [2] T. Lee and M. Je, “Brief architectural survey of biopotential recording front-ends since the 1970s,” _arXiv preprint arXiv:2309.11612_ , pp. 1–5, Sept. 2023.
  * [3] R. R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neural recording applications,” _IEEE J. Solid-State Circuits_ , vol. 38, no. 6, pp. 958–965, Jun. 2003.
  * [4] T. Jang _et al._ , “A noise-efficient neural recording amplifier using discrete-time parametric amplification,” _IEEE Solid-State Circuits Lett._ , vol. 1, no. 11, pp. 203–206, Nov. 2018.
  * [5] G. Atzeni, A. Novello, G. Cristiano, J. Liao, and T. Jang, “A 0.45/0.2-NEF/PEF 12-nV/$\sqrt{Hz}$ highly configurable discrete-time low-noise amplifier,” _IEEE Solid-State Circuits Lett._ , vol. 3, pp. 486–489, Oct. 2020.
  * [6] M. S. J. Steyaert, W. M. C. Sansen, and C. Zhongyuan, “A micropower low-noise monolithic instrumentation amplifier for medical purposes,” _IEEE J. Solid-State Circuits_ , vol. SC-22, no. 6, pp. 1163–1168, Dec. 1987.
  * [7] B. Razavi, _Design of Analog CMOS Integrated Circuits_ , 2nd ed. (New York: McGraw-Hill, 2016).
  * [8] R. Muller, S. Gambini, and J. M. Rabaey, “A 0.013 mm2, 5 $\mu$W, DC-coupled neural signal acquisition IC with 0.5 V supply,” _IEEE J. Solid-State Circuits_ , vol. 47, no. 1, pp. 232–243, Jan. 2012.
  * [9] D. Han, Y. Zheng, R. Rajkumar, G. S. Dawe, and M. Je, “A 0.45 V 100-channel neural-recording IC with sub-$\mu$W/channel consumption in 0.18 $\mu$m CMOS,” _IEEE Trans. Biomed. Circuits Syst._ , vol. 7, no. 6, pp. 735–746, Dec. 2013.
  * [10] F. M. Yaul and A. P. Chandrakasan, “A noise-efficient 36 nV/$\sqrt{Hz}$ chopper amplifier using an inverter-based 0.2-V supply input stage,” _IEEE J. Solid-State Circuits_ , vol. 52, no. 11, pp. 3032–3042, Nov. 2017.
  * [11] M. R. Pazhouhandeh, M. Chang, T. A. Valiante, and R. Genov, “Track-and-zoom neural analog-to-digital converter with blind stimulation artifact rejection,” _IEEE J. Solid-State Circuits_ , vol. 55, no. 7, pp. 1984–1997, Jul. 2020.
  * [12] J. Huang and P. P. Mercier, “A 112-dB SFDR 89-dB SNDR VCO-based sensor front-end enabled by background-calibrated differential pulse code modulation,” _IEEE J. Solid-State Circuits_ , vol. 56, no. 4, pp. 1046–1057, Apr. 2021.

Taeju Lee received the B.S. degree in Electrical, Electronics and
Communication Engineering from Korea University of Technology and Education
(KOREATECH), Cheonan-si, Republic of Korea, in 2014, the M.S. degree in
Information and Communication Engineering from Daegu Gyeongbuk Institute of
Science and Technology (DGIST), Daegu, Republic of Korea, in 2016, and the
Ph.D. degree in Electrical Engineering from Korea Advanced Institute of
Science and Technology (KAIST), Daejeon, Republic of Korea, in 2021.

From 2021 to 2022, he was a Postdoctoral Researcher at KAIST, Daejeon,
Republic of Korea. Since 2022, he has been a Postdoctoral Research Scientist
at Columbia University, New York, NY, USA. His current research interests
include integrated circuits (ICs) used in neuromodulation technology,
ultrasound systems, and computing engines.