# Endurance Management in Neuromorphic Computing via Hardware-Software Co-
design

Shihao Song, Twisha Titirsha, and Anup Das  Electrical and Computer
Engineering, Drexel University, Philadelphia, PA
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# Improving Endurance of Neuromorphic Hardware via Hardware-Software Co-design

Shihao Song, Twisha Titirsha, and Anup Das  Electrical and Computer
Engineering, Drexel University, Philadelphia, PA
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# Improving Read Endurance of Neuromorphic Systems via Intelligent Synapse
Mapping

Shihao Song, Twisha Titirsha, and Anup Das  Electrical and Computer
Engineering, Drexel University, Philadelphia, PA
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# Improving Inference Lifetime of Neuromorphic Systems via Intelligent Synapse
Mapping

Shihao Song, Twisha Titirsha, and Anup Das  Electrical and Computer
Engineering, Drexel University, Philadelphia, PA
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###### Abstract

Non-Volatile Memories (NVMs) such as Resistive RAM (RRAM) are used in
neuromorphic systems to implement high-density and low-power analog synaptic
weights. Unfortunately, an RRAM cell can switch its state after reading its
content a certain number of times. Such behavior challenges the integrity and
program-once-read-many-times philosophy of implementing machine learning
inference on neuromorphic systems, impacting the Quality-of-Service (QoS).
Elevated temperatures and frequent usage can significantly shorten the number
of times an RRAM cell can be reliably read before it becomes absolutely
necessary to reprogram. We propose an architectural solution to extend the
read endurance of RRAM-based neuromorphic systems. We make two key
contributions. First, we formulate the read endurance of an RRAM cell as a
function of the programmed synaptic weight and its activation within a machine
learning workload. Second, we propose an intelligent workload mapping strategy
incorporating the endurance formulation to place the synapses of a machine
learning model onto the RRAM cells of the hardware. The objective is to extend
the inference lifetime, defined as the number of times the model can be used
to generate output (inference) before the trained weights need to be
reprogrammed on the RRAM cells of the system. We evaluate our architectural
solution with machine learning workloads on a cycle-accurate simulator of an
RRAM-based neuromorphic system. Our results demonstrate a significant increase
in inference lifetime with only a minimal performance impact.

###### Index Terms:

Neuromorphic Computing, Non-Volatile Memory (NVM), Endurance, RRAM, Spiking
Neural Network (SNN)

##  I Introduction

Neuromorphic systems are integrated circuits that mimic the neuro-biological
architecture of the central nervous system [1]. They employ variants of
integrate-and-fire (I&F) neurons as computational units and analog weights as
synaptic storage. I&F neurons use spikes to encode information, where each
spike is a voltage or current pulse, typically of an ms duration [2]. Due to
its event (spike)-driven operations, a neuromorphic system consumes less power
and therefore, well suited as the hardware for inference of trained machine
learning models deployed in power-constrained environments such as Embedded
Systems and Internet-of-Things (IoT).

Non-Volatile Memory (NVM) technologies such as Filamentary Oxide-based
Resistive RAM (RRAM), Phase-Change Memory (PCM), and Spin-based Magnetic RAM
(MRAM) enable low-voltage multilevel operations, making them suitable for
implementing analog synaptic weight storage in neuromorphic systems [3, 4, 5].
Of these emerging new memory technologies, hafnia (HfO2)-based RRAM has shown
a significant promise due to its CMOS compatibility at scaled nodes, allowing
the fabrication of high-density synaptic storage for neuromorphic systems. The
synaptic weights are programmed on RRAM cells as conductance. An RRAM cell can
be programmed to a high-resistance state (HRS) or one of the low-resistance
states (LRS). Unfortunately, RRAM cells have limited _read endurance_ , i.e.,
an RRAM cell can switch its state after performing a certain number of reads
[6]. To give an example, a single quasi-static read for 5000 ms or 5000 reads
with 1-ms read time can lead to an abrupt change from HRS to LRS state in an
RRAM cell [6]. To put in the context of neuromorphic computing, an RRAM cell
can reliably propagate 5000 1-ms spikes before it becomes absolutely necessary
to reprogram the state of the cell.

We now extrapolate this RRAM device behavior to the application level,
describing such extrapolation with the running example of VGG, a deep learning
model trained on CIFAR-10 dataset and performing inference on an RRAM-based
neuromorphic system. Figure 1 shows the histogram of average spikes per image
propagating through the synapses of VGG. We collected these statistics by
analyzing CIFAR-10 training and test datasets. We see that some synapses
propagate more spikes than others when inferring an image. These are called
the _critical synapses_ and they decide how many images can be reliably
inferred using the VGG model before it becomes necessary to reprogram the
trained synaptic weights on the RRAM cells of the hardware.

Figure 1: Spike distribution across the synapses of VGG.

To give an example, assume $n$ to be the maximum number of spikes per image on
the critical synapses of VGG ($n=6.42$ in Figure 1). Then, the RRAM cells need
to be reprogrammed once every $\frac{5000}{n}\approx 778$ images to ensure
correctness. The time to infer $778$ images is called the _inference
lifetime_. Formally,

$\footnotesize\text{Inference Lifetime}=\frac{\text{Read
Endurance}}{\text{spikes per image}}$ (1)

If the RRAM devices implementing VGG are not reprogrammed before the inference
lifetime expires, then the accuracy of VGG can drop significantly (accuracy in
the low 20% is reported in [6]).

Periodic reprogramming of synaptic weights on a neuromorphic system challenges
the program-once-read-many-times philosophy of machine learning inference
hardware, which can impose significant system overhead. To give an example,
imagine such systems are deployed at the edge nodes of an IoT infrastructure.
Frequent updates of these nodes with trained weights will 1) increase
communication between the edge and cloud, and 2) reduce the Quality-of-Service
(QoS) due to offlining of the edge nodes every time they are reprogrammed.

We observe that inside a neuromorphic system, the RRAM cells are organized
into crossbars. The parasitic IR drops in a crossbar create a difference in
the voltage needed to propagate spike through the RRAM cells in the crossbar
[7]. Such voltage differences create a variation of read endurance of the RRAM
cells, i.e., some RRAM cells are stronger than others, where the strength of
an RRAM cell is measured in terms of its read endurance, which is a function
of the voltage. Unfortunately, if the critical synapses (those that propagate
more spikes) are mapped on weaker RRAM cells (those that have low read
endurance), then the inference lifetime can decrease significantly, lowering
the QoS. We propose an intelligent synapse allocation strategy, which analyzes
spikes propagating through each synapse of a machine learning model during
inference and uses such information to map the model’s synaptic weights to the
RRAM cells considering the variation in their read endurance. The objective is
to maximize the inference lifetime of the hardware. Our architectural solution
is built on the following three key contributions.

  * •

First, we investigate the internal architecture of an RRAM-based neuromorphic
system and estimate the endurance variation through detailed circuit-level
simulations at different process and temperature corners.

  * •

Second, we analyze a trained machine learning model and estimate the spikes
propagating through its synapses.

  * •

Finally, we use a Hill-Climbing approach that uses Binary Non-Linear
Programming (BNLP) to map the synapses of a machine learning model to the RRAM
cells such that the critical synapses are always mapped to stronger RRAM
cells, thereby improving the inference lifetime.

We evaluate our architectural approach with different machine learning models
on NeuroXplorer [8], a cycle-accurate simulator of RRAM-based neuromorphic
system. Results show a significant improvement in inference lifetime with a
minimal impact on model performance.

##  II Background

A neuromorphic system is implemented as a tiled architecture (see Fig. 2a),
where the tiles are interconnected hierarchically using a shared interconnect
such as Network-on-Chip (Noc) [9] or Segmented Bus [10]. This is the
representative architecture of many recent systems such as TrueNorth [11],
Loihi [12], and DYNAPs [13]. In many recent systems, a tile is implemented
using a crossbar, which is illustrated in Figure 2b. An $M$x$M$ crossbar can
accommodate $M$ pre-synaptic neurons, mapped along the rows and $M$ post-
synaptic neurons, mapped along the columns. There are ${M}^{2}$ synaptic
cells, which store the weights. Figure 2c shows a 2x2 crossbar in three-
dimension, with the top electrodes forming the rows and bottom electrodes
forming the columns. A synaptic cell is placed at each intersection of top and
bottom electrodes.

(a) Tiled neuromorphic hardware. (b) Crossbar architecture. (c) A 3-D view of
a crossbar. (d) Parasitics of a crossbar.

Figure 2: Neuromorphic system architecture with crossbars.

Figure 2d shows the different parasitic components inside a crossbar. Such
components cause variable delays on the current paths inside the crossbar. For
simplicity, we have only shown the current on the shortest and the longest
paths in the crossbar, where the length of a current path is measured in terms
of the number of parasitic elements on the path. Therefore, spike propagation
delay through synapses on longer paths is higher than on shorter paths.
Although optimizing inference lifetime is our primary focus, we also evaluate
the impact of our architectural solution on spike propagation delay (see
Section V). Parasitic components in a crossbar also lead to voltage
variations, which impact read endurance of the synaptic cells. We analyze such
impact in Section III.

###  II-A Machine Learning Inference on Neuromorphic Systems

Each crossbar in a neuromorphic system can accommodate only a limited number
of neurons and synapses. To map large models, the model is first partitioned
into clusters of neurons and synapses, where each cluster can fit onto a
crossbar of the hardware [14, 15, 16, 17, 18, 19, 20]. Figure 3a shows the
architecture of VGG for CIFAR-10 classification. Figure 3b shows the first 10
clusters generated using SpiNeMap [14], a state-of-the-art approach to map
machine learning inference to neuromorphic systems. The figure illustrates the
connections between these clusters, with the number on edge representing the
average number of spikes communicated between the source and destination
clusters when processing an image during inference.

When partitioning a machine learning model into clusters, SpiNeMap aims to
minimize the inter-cluster spikes, which reduces the energy consumption on the
interconnect of the hardware. There are also other optimization objectives
proposed in literature. Examples include improving crossbar utilization [19],
reducing crossbar usage [15], reducing energy consumption [21, 22, 7, 23, 24,
25], and reducing circuit aging [26, 27, 28, 29, 30]. None of these approaches
address mapping of the synapses of a cluster to the synaptic cells of a
crossbar for the purpose of inference on neuromorphic systems. To understand
why such mapping matters, we now introduce the background on filamentary
oxide-based RRAM technology, which can be used to design the synaptic cells of
a crossbar.

(a) VGG Convolution Neural Network (CNN). (b) First 10 clusters of VGG (out of
95,452) clusters).

Figure 3: Trained VGG model and its clusters generated using SpiNeMap [14].

###  II-B Oxide-based Resistive RAM (RRAM) Technology

The resistance switching random access memory (RRAM) technology presents an
attractive option for implementing the synaptic cells of a crossbar due to its
demonstrated potential for low-power multilevel operation and high integration
density [4]. An RRAM cell is composed of an insulating film sandwiched between
conducting electrodes forming a metal-insulator-metal (MIM) structure (see
Figure 4). Recently, filament-based metal-oxide RRAM implemented with
transition-metal-oxides such as HfO2, ZrO2, and TiO2 has received considerable
attention due to their low-power and CMOS-compatible scaling.

Synaptic weights are represented as conductance of the insulating layer within
each RRAM cell. To program an RRAM cell, elevated voltages are applied at the
top and bottom electrodes, which re-arranges the atomic structure of the
insulating layer. Figure 4 shows the High-Resistance State (HRS) and the Low-
Resistance State (LRS) of an RRAM cell. An RRAM cell can also be programmed
into intermediate low-resistance states, allowing its multilevel operations.
In this work, we consider each RRAM cell to be programmed to one HRS and three
LRS states, implementing two bits per synapse.

Figure 4: Operation of an RRAM cell with the $\text{HfO}_{2}$ layer sandwiched
between the metals Ti (top electrode) and TiN (bottom electrode). The left
subfigure shows the formation of LRS states with the formation of conducting
filament (CF). This represents logic states 01, 10, and 11. The right
subfigure shows the depletion of CF on application of a negative voltage on
the TE. This represents the HRS state or logic 00.

(a) 65nm, 25∘C. (b) 45nm, 25∘C. (c) 32nm, 25∘C. (d) 16nm, 25∘C.

(e) 65nm, 50∘C. (f) 45nm, 50∘C. (g) 32nm, 50∘C. (h) 16nm, 50∘C.

Figure 5: Variation in RRAM voltages within an 128x128 crossbar for inference.
Such variations are reported for four technology nodes (65nm, 45nm, 32nm, and
16nm) and two temperature settings (25∘C and 50∘C).

##  III Variation of Read Endurance

Inside a neuromorphic system, the long bitlines and wordlines of a crossbar
are the major sources of parasitic (IR) voltage drops, introducing asymmetry
in the voltage applied across the different RRAM cells in the hardware [31,
32, 33]. To study this behavior, we simulate a 128x128 RRAM-based crossbar
circuit using the predictive technology model (PTM) [34] and RRAM-specific
parameters [35].

Figure 5 shows the variation of RRAM voltages in a 128x128 crossbar during
inference for four technology nodes (65 nm, 45 nm, 32 nm, and 16 nm) and two
temperature settings (25∘C and 50∘C). We make the following three key
observations. First, RRAM voltages at the bottom left corner of the crossbar
are higher than those at the top right corner. This is because the current
paths via the RRAM cells at the bottom left corner are shorter, i.e., they
have lower parasitic voltage drops than at the top right corner. Second, with
technology scaling, the voltage variation increases. The highest RRAM voltage
in the crossbar is 1.1 V at 16 nm and 25∘C (Figure 5d) compared to 0.57 V at
65 nm and 25∘C (Figure 5a). This difference is because the unit parasitic
resistance of the electrodes increases from $1\Omega$ at 65 nm to $3.8\Omega$
at 16 nm [34]. The value of the parasitic resistance is expected to increase
with technology scaling, with a value $\approx 25\Omega$ at 5 nm [36]. Third,
RRAM voltage increases with temperature (Figures 5e-5h vs. Figures 5a-5d).
This is because with increase in temperature, the leakage current through the
access transistor of each RRAM cell in the crossbar increases. Therefore, to
obtain a certain current margin at the readout unit of the crossbar, the input
voltage applied on the top electrodes needs to increase, which increases the
RRAM voltages.

###  III-A Voltage-Dependant Read Endurance of RRAM cells

We now provide a formulation of the read endurance of the RRAM cells in a
crossbar as a function of the input voltage.111Limited write endurance of RRAM
cells has been studied before in the context of neuromorphic computing [37,
38]. This is the first work that studies the read endurance problem and
proposes an intelligent solution. In RRAM technology, the transition from HRS
state is governed by a sudden decrease of the vertical filament gap on
application of stress voltage during spike propagation [6]. The rate of change
of the filament gap of the RRAM cell at the $(i,j)^{\text{th}}$ location in
the crossbar is

$\footnotesize\frac{dg_{i,j}}{dt}=-\vartheta_{0}\cdot
e^{-\frac{E_{a}}{kT}}sinh\left(\frac{\gamma_{i,j}\cdot
a_{0}}{L}\cdot\frac{qV_{i,j}}{kT}\right)\text{, where
}\gamma_{i,j}=\gamma_{0}-\beta\cdot\frac{g_{i,j}}{g_{0}}^{3}$ (2)

In the above equation, $t$ defines the state transition time, $g_{0}$ is the
initial filament gap of the RRAM cell, $V_{i,j}$ is the voltage applied to the
cell, $\gamma_{i,j}$ is the local field enhancement factor and is related to
the gap $g_{i,j}$, $a_{0}$ is the atomic hoping distance, and $\gamma_{0}$ is
a fitting constant.

The transition from one of the LRS states is governed by the lateral filament
growth [6]. The time for state transition in the $(i,j)^{\text{th}}$ RRAM cell
is given by

$\footnotesize t_{i,j}(LRS)=10^{-14.7\cdot V_{i,j}+6.7}\text{sec}$ (3)

Using Equations 2 and 3, the read endurance of the $(i,j)^{\text{th}}$ RRAM
cell can be derived as

$\footnotesize E_{i,j}(HRS/LRS)=\frac{t_{i,j}(HRS/LRS)}{1~{}ms\text{ (spike
duration)}}$ (4)

Figure 6 shows the endurance variation of a 128x128 crossbar at 45 nm node and
at 25∘C with each RRAM cell programmed to 1) HRS state (Figure 6a) and 2) one
of the LRS states (Figure 6b). We observe that endurance of an RRAM cell is
higher if the cell is programmed to an LRS state compared to when it is
programmed to the HRS state.

(a) Each RRAM cell in HRS state. (b) Each RRAM cell in LRS state.

Figure 6: Variation in RRAM endurance within an 128x128 crossbar at 45 nm node
and at 25∘C. Such variations are reported for the RRAM cells programmed in (a)
HRS and (b) one of the LRS states.

From the machine learning workload perspective, synapses can either be in the
HRS state or in one of the LRS states. Therefore, based on how the synapses of
a model are mapped inside a crossbar, the endurance map will assume
intermediate forms between Figures 6a and 6b. To simplify the problem
formulation, we define equivalence in terms of inference lifetime as follows.
Consider $A$ and $B$ to be two synaptic weights in a machine learning model
with spikes $S_{A}$ and $S_{B}$, respectively. Without loss of generality,
consider $A$ to be in HRS state and $B$ in LRS state. Let these weights are
programmed on the RRAM cells at the same $(i,j)^{\text{th}}$ location in two
different crossbars. Then, the inference lifetime due to $A$ is
$\frac{E_{i,j}(HRS)}{S_{A}}$ and that due to $B$ is
$\frac{E_{i,j}(LRS)}{S_{B}}$. Synaptic weights $A$ and $B$ are considered to
be equivalent in terms of the inference lifetime at the $(i,j)^{\text{th}}$
position in a crossbar if

$\footnotesize\frac{E_{i,j}(HRS)}{S_{A}}=\frac{E_{i,j}(LRS)}{S_{B}}$ (5)

We use Equation 5 for mapping and inference lifetime computation purposes.
Once the mapping is decided, RRAM cells are programmed to their actual state.

##  IV Problem Formulation

The mapping of a machine learning model to hardware is formulated in the
following three steps.

  1. 1.

Formulating inference lifetime of model clusters.

  2. 2.

Cluster mapping with unlimited hardware resources.

  3. 3.

Cluster mapping with limited hardware resources.

We now elaborate on these mapping steps.

###  IV-A Formulating Inference Lifetime of Model Clusters

We consider the mapping of a cluster $\mathbb{C}=(Pre,Post,Syn)$ of a machine
learning model onto a crossbar of the hardware. Here $Pre$ is the set of pre-
synaptic neuron, $Post$ is the set of post-synaptic neuron, and $Syn$ is the
set of synapses between the pre- and post-synaptic neurons of the cluster.
Each neuron $n_{i}\in Pre$ is characterized by a number $spk(n_{i})$,
indicating the average number of spikes generated by this neuron per image
during inference. Each synapse $s_{i,j}\in Syn$ connecting the pre-synaptic
neuron $n_{i}\in Pre$ and post-synaptic neuron $n_{j}\in Post$ is associated
with a number $wt(s_{i,j})$ representing its synaptic weight. The number of
spikes on the synapse $s_{i,j}$ is the same as the number of spikes generated
by its pre-synaptic neuron $n_{i}$, i.e., $spk(s_{i,j})=spk(n_{i})$.

Consider the mapping of this cluster $\mathbb{C}$ to a MxM crossbar
$\mathbb{H}=(In,Out)$ with a set $In$ of input ports to map pre-synaptic
neurons and a set $Out$ of output ports to map post-synaptic neurons. Here
$|In|=|Out|=M$.

Let $X_{i,k}$ be a binary variable representing the mapping of pre-synaptic
neuron $n_{i}\in Pre$ to the input port $i_{k}\in In$ and $Y_{j,l}$ be a
binary variable representing the mapping of post synaptic neuron $n_{j}\in
Post$ to the output port $o_{l}\in Out$.

The problem we are aiming to solve is this: find the binary variables
$X_{i,j}$ and $Y_{j,l}$ such that the inference lifetime is maximized when
mapping the cluster to a crossbar. Therefore, the objective function is the
inference lifetime. To maximize the objective function, we define the
following constraints.

  * •

Each pre-synaptic neuron can be mapped to exactly one input port of the
hardware, i.e., $\sum_{k=1}^{M}X_{i,k}=1~{}\forall i$.

  * •

Each post-synaptic neuron can be mapped to exactly one output port of the
hardware, i.e., $\sum_{l=1}^{M}Y_{j,l}=1~{}\forall j$

To formulate the objective function itself, we consider the synapse
$s_{i,j}\in Syn$, which connects the pre-synaptic neuron $n_{i}$ with the
post-synaptic neuron $n_{j}$. In terms of the variables $X_{i,k}$ and
$Y_{j,l}$, the synapse $s_{i,j}$ is mapped to the RRAM cell at
$(k,l)^{\text{th}}$ position in the crossbar. The inference lifetime of the
synapse can be computed by first considering the equivalence to HRS state
using Equation 5, and then dividing the HRS endurance of the RRAM cell with
the number of spikes on the synapse using Equation 1. This is given by

$\footnotesize f(i,j)=\text{Inference
Lifetime}(i,j)=\sum_{k=1}^{M}\sum_{l=1}^{M}X_{i,k}\cdot
Y_{j,l}\cdot\frac{E_{k,l}(HRS)}{spk_{eq}(s_{i,j})}$ (6)

The maximization problem is

$\footnotesize\max_{\begin{subarray}{c}1\leq i\leq|Pre|\\\ 1\leq
j\leq|Post|\end{subarray}}f(i,j)$ (7)

The use of binary (discrete) variables makes the optimization problem of
Equation 7 non-convex, while the product term in Equation 6 makes this non-
linear (NL). Therefore, the optimization problem we are aiming to solve is a
Non-Convex Binary Non-Linear Programming (BNLP) problem and there is no
guarantee of optimality [39]. We use the smoothing method proposed in the
Ph.D. dissertation [40] to solve this BNLP problem. The optimized inference
lifetime obtained from mapping the cluster $\mathbb{C}$ to the crossbar
$\mathbb{H}$ is

$\footnotesize\text{Inference Lifetime}(\mathbb{C},\mathbb{H})=f_{\text{opt}}$
(8)

In this study, we have ignored process variations across the crossbars of a
hardware. So, the inference lifetime of a cluster is the same, irrespective of
which crossbar this cluster is mapped to in the hardware. This allows us to
decouple the crossbar term from Equation 8. We use the variable
$\mathcal{L}_{i}$ to represent the inference lifetime of the cluster
$\mathbb{C}_{i}$.

###  IV-B Cluster Mapping with Unlimited Hardware Resources

If the hardware contains unlimited number of crossbars, then each crossbar can
map at most one cluster of a machine learning model. Therefore, the inference
lifetime for the model when it is mapped to the hardware is the minimum
inference lifetime of all the clusters of the hardware, i.e,

$\footnotesize\text{Inference
Lifetime}=\text{minimum}\\{\mathcal{L}_{i},~{}\forall i\in
1,2,\cdots,N_{C}\\},$ (9)

where $N_{C}$ is the number of clusters of the model.

###  IV-C Cluster Mapping with Limited Hardware Resources

If the number of crossbars in the hardware is limited, then each crossbar may
need to be shared across multiple clusters of a machine learning model. We now
formulate the cluster mapping problem as follows. Let the binary variable
$Z_{i,j}$ indicate the mapping of cluster $\mathbb{C}_{i}$ to crossbar
$\mathbb{H}_{j}$, i.e.,

$\footnotesize Z_{i,j}=\begin{cases}1&\text{ if cluster }\mathbb{C}_{i}\text{
is mapped to crossbar }\mathbb{H}_{j}\\\ 0&\text{otherwise}\end{cases}$ (10)

The problem we are aiming to solve is this: find the binary variables
$Z_{i,j}$ such the inference lifetime of the machine learning model on the
hardware is improved. We define the following constraint: each cluster must be
mapped to only one crossbar, i.e., $\sum_{j=1}^{N_{H}}Z_{i,j}=1~{}\forall i$,
where $N_{H}$ is the number of crossbars of the hardware with $N_{H}\leq
N_{C}$.

To explore the cluster-to-crossbar mapping search space for the maximum
inference lifetime, we use a Hill-Climbing-based local search [41]. Each
mapping solution is represented by $\mathbb{Z}\in\mathbb{R}^{N_{C}\times
N_{H}}$. Figure 7 shows the working of the search algorithm.

Figure 7: Flowchart for Hill-Climbing-based search.

For each solution $\mathbb{Z}$ generated by the algorithm, it computes the
inference lifetime of each crossbar as follows. If a crossbar has only one
cluster, the inference lifetime is computed by solving the proposed BNLP
problem formulation (Equation 7). If more than one cluster is mapped to the
crossbar, the clusters on this crossbar are merged. Merging a cluster involves
combining the clusters to form a larger cluster and is described
mathematically as follows. Merging of clusters
$\mathbb{C}_{a}=(Pre_{a},Post_{a},Syn_{a})$ and
$\mathbb{C}_{b}=(Pre_{b},Post_{b},Syn_{b})$ is

$\footnotesize\texttt{merge}(\mathbb{C}_{a},\mathbb{C}_{b})=\mathbb{C}_{a+b}=(Pre_{a+b},Post_{a+b},Syn_{a+b}),$
(11)

where $Pre_{a+b}=Pre_{a}\cup Pre_{b}$, $Post_{a+b}=Post_{a}\cup Post_{b}$, and
$Syn_{a+b}=Syn_{a}\cup Syn_{b}$. Once the clusters mapped to a crossbar are
merged, the inference lifetime of the merged cluster is computed using the
proposed BNLP formulation. Then the algorithm computes the overall inference
lifetime as the minimum of the inference lifetime of all crossbars of the
hardware. If this value is higher than the best solution obtained thus far,
the mapping is retained and the algorithm proceeds to find a better mapping
solution. Otherwise, the algorithm continues to explore for a few more
iterations to see if a better mapping solution can be generated. This general
formulation can be applied to the case where $N_{H}>N_{C}$, i.e., the number
of hardware crossbars is greater than model clusters.

###  IV-D Performance Impact

We now formally quantify the performance degradation due to our mapping
exploration (Sections IV-A, IV-B, and IV-B) using the previously-introduced
notations. Let $\mathbb{Z}_{\text{opt}}\in\\{0,1\\}^{N_{C}\times N_{H}}$ be
the optimum mapping (one with the highest inference lifetime obtained using
the Hill-Climbing approach of Figure 7) of the clusters of a machine learning
model to the crossbars of a neuromorphic hardware.

Within the optimum mapping, let
$\mathbb{M}_{\text{opt}_{p}}=[\mathbb{X}_{\text{opt}_{p}}~{}|~{}\mathbb{Y}_{\text{opt}_{p}}]~{}\forall
p\in 1,2,\cdots,N_{C}$ be the optimum mapping (one with the highest inference
lifetime obtained by solving the BNLP of Equation 7) of pre- and post-synaptic
neurons of the $p^{\text{th}}$ cluster to a crossbar. Here
$\mathbb{X}_{\text{opt}_{p}}\in\\{0,1\\}^{|Pre_{p}|\times|In|}$ and
$\mathbb{Y}_{\text{opt}_{p}}\in\\{0,1\\}^{|Post_{p}|\times|Out|}$.

Let $d_{k,l}$ represents the delay in spike propagation through the RRAM cell
at the $(k,l)^{\text{th}}$ location in a crossbar. Therefore, the spike
propagation delay through the synapse $s_{i,j}$ is

$\footnotesize\text{synapse\\_delay}_{i,j}=\sum_{k=1}^{M}\sum_{l=1}^{M}X_{i,k}\cdot
Y_{j,l}\cdot d_{k,l}$ (12)

Therefore, the average spike propagation delay of the cluster when mapped to a
crossbar is

$\footnotesize\text{cluster\\_delay}=\frac{\sum_{i=1}^{Pre}\sum_{j=1}^{Post}spk(s_{i,j})\cdot\text{synapse\\_delay}_{i,j}}{\sum_{i=1}^{Pre}\sum_{j=1}^{Post}spk(s_{i,j})}$
(13)

Equation 13 can be extrapolated to compute the spike propagation delay of the
entire machine learning model when mapped to the neuromorphic hardware as

$\footnotesize\text{hardware\\_delay}=\frac{\sum_{p=1}^{N_{C}}\sum_{i=1}^{Pre_{p}}\sum_{j=1}^{Post_{p}}spk(s_{i,j}^{p})\cdot\text{cluster\\_delay}_{p}}{\sum_{p=1}^{N_{C}}\sum_{i=1}^{Pre_{p}}\sum_{j=1}^{Post_{p}}spk(s_{i,j}^{p})}$
(14)

##  V Results and Discussion

We evaluate the proposed approach using NeuroXplorer [8], a cycle-accurate
neuromorphic system simulator that uses tile-based architecture (see Fig. 8).
We model the DYNAPs neuromorphic hardware [13] with hierarchical NoC-based
interconnect. Each tile has one $128\times 128$ crossbar. Table I reports the
relevant hardware parameters.

TABLE I: Major simulation parameters extracted from [13]. Neuron technology |  45nm
---|---
Synapse technology |  HfO2-based RRAM
Supply voltage |  1.0V
Figure 8: Evaluation framework based on NeuroXplorer [8].

We evaluate 10 machine learning programs which are representative of three
most commonly-used neural network classes: convolutional neural network (CNN),
multi-layer perceptron (MLP), and recurrent neural network (RNN). Table II
summarizes the topology, the number of neurons and synapses of these
applications, and their baseline accuracy on the DYNAPs neuromorphic hardware
using the SpiNeMap [14].

TABLE II: Applications used to evaluate the proposed approach. Class | Applications | Dataset | Synapses | Neurons | Topology | Accuracy
---|---|---|---|---|---|---
CNN | LeNet | MNIST | 282,936 | 20,602 | CNN | 85.1%
AlexNet | ImageNet | 38,730,222 | 230,443 | CNN | 69.8%
VGG | CIFAR-10 | 99,080,704 | 554,059 | CNN | 90.7 %
HeartClass [42, 43] | Physionet | 1,049,249 | 153,730 | CNN | 63.7%
MLP | MLPDigit | MNIST | 79,400 | 884 | FeedForward | 91.6%
EdgeDet | CARLsim | 114,057 | 6,120 | FeedForward | 100%
ImgSmooth | CARLsim | 9,025 | 4,096 | FeedForward | 100%
RNN | HeartEstm [44] | Physionet | 66,406 | 166 | Recurrent Reservoir | 100%
VisualPursuit [45] | [45] | 163,880 | 205 | Recurrent Reservoir | 47.3%
RNNDigit | MNIST | 11,442 | 567 | Recurrent Reservoir | 83.6%

###  V-A Inference Lifetime on Unlimited Hardware Resources

Figure 9 reports the inference lifetime for each application for the proposed
approach normalized to SpiNeMap. For reference, we have reported the absolute
inference lifetime in frames for each application using the proposed approach.
For image-based applications (LeNet, AlexNet, VGG, MLPDigit, EdgeDet,
ImgSmooth, and RNNDigit), a frame corresponds to an individual image. For
other time-series applications (HeartClass, HeartEstm, and VisualPursuit), a
frame corresponds to a window of 500ms. We make the following two
observations.

Figure 9: Inference lifetime normalized to SpiNeMap.

First, the inference lifetime obtained using the proposed approach is on
average 3.4x higher than SpiNeMap. This improvement is because the proposed
approach uses the novel BNLP formulation to decide how the synaptic weights of
a cluster need to be mapped to the RRAM cells of a crossbar to maximize the
inference lifetime. To do so, the proposed approach incorporates both RRAM
device and machine learning workload characteristics. The proposed formulation
ensures that critical synapses (those that propagate more spikes) are never
mapped to the weaker cells (those that have low read endurance). SpiNeMap on
the other hand, maps the synaptic weight of a cluster arbitrarily to the RRAM
cells of a crossbar.

Second, the inference lifetime improvement of the proposed approach is, in
general, lower for smaller applications such as MLPDigit, EdgeDet, and
ImgSmooth (average 1.9x), compared to larger applications such as LeNet,
AlexNet, and VGG (average 4x). This is because with larger applications (ones
with more clusters), the proposed approach has greater scope to improve the
inference lifetime by intelligently mapping the synaptic weights in all the
clusters.

Figure 10: Average RRAM voltage normalized to SpiNeMap.

To give further insight, Figure 10 plots the average voltage on the RRAM cells
within a crossbar when the clusters of each evaluated application are mapped
to them. For reference, we have reported the absolute voltage in V for the
proposed approach. We observe that the average voltage on the RRAM cells in
the proposed approach is 9% lower than SpiNeMap. This is because the proposed
approach uses the top right corners of a crossbar (see Figure 2d) to place the
synaptic weights. This is where the parasitic voltage drops are higher,
resulting in a lower voltage across the RRAM cells.

###  V-B Spike Delay

Unfortunately, the RRAM cells at the top right corner of each crossbar
introduce longer spike propagation delay than those at the bottom left corner.
To estimate the average increase in spike delay, Figure 11 plots the spike
propagation delay through the crossbar for each application, normalized to
SpiNeMap. For reference, we have reported the absolute delay in ms using the
proposed approach. We observe that the spike propagation delay using the
proposed approach is only an average 6% higher than SpiNeMap.

Figure 11: Crossbar spike propagation delay normalized to SpiNeMap.

###  V-C Inference Lifetime with Limited Hardware Resources

Figure 12 plots the inference lifetime obtained using the proposed approach
normalized to SpiNeMap as we increase the hardware size from 256 crossbars to
1024 crossbars. We make the following two observations.

Figure 12: Inference lifetime for three different hardware configurations.

First, the inference lifetime of the proposed approach increases with an
increase in the size of the hardware. With 256, 512, and 1024 crossbars in the
hardware, the inference lifetime of the proposed approach is higher than
SpiNeMap by an average of 1.64x, 2.45x, and 3.16x. With fewer crossbars in the
hardware, the number of clusters mapped to each hardware increases, increasing
the crossbar utilization. Therefore, the proposed approach has limited scope
to reorganize the synapses onto the RRAM cells, resulting in lower improvement
than the case where there are more crossbars in the hardware. Second, the
improvement of inference lifetime in smaller applications like MLPDigit,
EdgeDet, and ImgSmooth is not significant compared to larger applications like
LeNet, AlexNet, and VGG. From these results, we conclude that the proposed
approach has a greater opportunity to increase the inference lifetime for
crossbars with lower utilization.

###  V-D Exploration Time

Table III reports the exploration time of the proposed Hill-Climbing-based
mapping exploration for each of the evaluated applications. Column 2 reports
the number of clusters of these applications generated using SpiNeMap [14].
For these clusters, Columns 3, 4, and 5 report the exploration time for three
hardware configurations – 256 crossbars, 512 crossbars, and 1024 crossbars,
respectively. We make the following two observations. First, the exploration
time increases with increase in the number of crossbars due to the increase in
the size of the search space. Second, for applications such as ImgSmooth and
RNNDigit, there is no significant increase in the exploration time because the
number of clusters for these applications is less than the number of crossbars
in the hardware. Therefore, the application mapping time is essentially the
time in solving the BNLP problem.

TABLE III: Exploration time of the proposed approach. Applications | Clusters | 256 crossbars | 512 crossbars | 1024 crossbars
---|---|---|---|---
LeNet | 2,066 | 2,189 sec | 2,702 sec | 3, 183 sec
AlexNet | 30,105 | 40,667 sec | 61,434 sec | 101,924 sec
VGG | 95,452 | 70,180 sec | 144,090 sec | 389, 644 sec
HeartClass | 7,871 | 5,111 sec | 8,110 sec | 12, 145 sec
MLPDigit | 520 | 594 sec | 784 sec | 1,010 sec
EdgeDet | 437 | 405 sec | 612 sec | 824 sec
ImgSmooth | 41 | 52 sec | 52 sec | 52 sec
HeartEstm | 325 | 321 sec | 486 sec | 611 sec
VisualPursuit | 1,001 | 1,138 sec | 1,520 sec | 1,921 sec
RNNDigit | 90 | 114 sec | 114 sec | 114 sec

###  V-E Technology Scaling

Figure 13 plots the inference lifetime of the proposed approach normalized to
SpiNeMap for four technology nodes – 65nm, 45nm (default), 32nm, and 16nm. We
observe that the improvement of inference lifetime over SpiNeMap increases as
the technology scales down, even though the absolute inference lifetime is
lower at scaled nodes. This is because with technology scaling, the endurance
variation within each crossbar becomes more significant. Therefore, the
proposed approach, which incorporates such variation in the cluster mapping
and synapse placement process leads to higher inference lifetime compared to
SpiNeMap.

Figure 13: Impact of technology scaling on inference lifetime.

##  VI Conclusions

We present a novel Binary Non-Linear Programming (BNLP) formulation of the
inference lifetime of machine learning workloads when mapped on to the RRAM
cells of a neuromorphic system. Using such formulation, we show that the
parasitic IR drops in the system create a significant difference in read
endurance of the RRAM cells. We incorporate the BNLP formulation and endurance
variation inside a Hill-Climbing-based mapping exploration to find an optimum
mapping of the clusters of an inference model to the crossbars of a hardware,
improving its inference lifetime. Our formulation ensures that critical
synapses (those that propagate more spikes) are never mapped on to the weaker
cells (ones that have lower endurance). We evaluate our approach with 10
machine learning applications on a cycle-accurate simulator of state-of-the-
art neuromorphic hardware. Our results demonstrate an average 3.4x improvement
in inference lifetime with only 6% increase in spike propagation delay.

## Acknowledgment

This work is supported by the National Science Foundation Faculty Early Career
Development Award CCF-1942697.

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# Investigation of Cryogenic Current-Voltage Anomalies in SiGe HBTs:
Role of Base-Emitter Junction Inhomogeneities

Nachiket R. Naik  0000-0001-8271-643X Division of Engineering and Applied
Science, California Institute of Technology, Pasadena, California, 91125, USA
Bekari Gabritchidze  0000-0001-6392-0523 Cahill Radio Astronomy Lab,
California Institute of Technology, Pasadena, California, 91125, USA  Justin
H. Chen  0000-0001-9745-7055 Division of Engineering and Applied Science,
California Institute of Technology, Pasadena, California, 91125, USA  Kieran
A. Cleary  0000-0002-8214-8265 Cahill Radio Astronomy Lab, California
Institute of Technology, Pasadena, California, 91125, USA  Jacob Kooi
0000-0002-6610-0384 NASA Jet Propulsion Laboratory, California Institute of
Technology, Pasadena, California, 91109, USA  Austin J. Minnich
0000-0002-9671-9540<EMAIL_ADDRESS>Division of Engineering and Applied
Science, California Institute of Technology, Pasadena, California, 91125, USA

###### Abstract

The deviations of cryogenic collector current-voltage characteristics of SiGe
heterojunction bipolar transistors (HBTs) from ideal drift-diffusion theory
have been a topic of investigation for many years. Recent work indicates that
direct tunneling across the base contributes to the non-ideal current in
highly-scaled devices. However, cryogenic discrepancies have been observed
even in older-generation devices for which direct tunneling is negligible,
suggesting another mechanism may also contribute. Although similar non-ideal
current-voltage characteristics have been observed in Schottky junctions and
were attributed to spatial inhomogeneities in the base-emitter junction
potential, this explanation has not been considered for SiGe HBTs. Here, we
experimentally investigate this hypothesis by characterizing the collector
current ideality factor and built-in potential of a SiGe HBT versus
temperature using a cryogenic probe station. The temperature-dependence of the
ideality factor and the relation between the built-in potential as measured by
capacitance-voltage and current-voltage characteristics are in good
qualitative agreement with the predictions of a theory of electrical transport
across a junction with a Gaussian distribution of potential barrier heights.
These observations suggest that lateral inhomogeneities in the base-emitter
junction potential may contribute to the cryogenic non-idealities. This work
helps to identify the physical mechanisms limiting the cryogenic microwave
noise performance of SiGe HBTs.

Heterojunction bipolar transistors, SiGe, cryogenic microwave amplifiers,
device physics, barrier inhomogeneities, ideality factor, microwave noise.

##  I Introduction

Silicon-germanium heterojunction bipolar transistors (HBTs) are widely used in
microwave applications such as high-speed communications and radar systems
owing to their competitive microwave performance, low cost, and ease of
integration compared with III-V compound semiconductor devices [1].
Technological advances such as reduced emitter widths, decreased base
resistances and extrinsic capacitances, and advanced epitaxial techniques have
enabled microwave noise performance approaching that of III-V high electron
mobility transistors [2, 3]. As a result, cryogenic SiGe HBTs have recently
been considered for applications in quantum computing and radio astronomy [4,
5, 6].

The cryogenic microwave performance of SiGe HBTs has been investigated
following their initial development in the 1980s [7] as various performance
metrics such as transconductance and noise figure improve with cooling.
However, below $\sim$ 77 K, these improvements are observed to plateau with
decreasing temperature [8, 9, 10], corresponding to a temperature-dependent
collector current ideality factor $n(T)$ that greatly exceeds unity at
cryogenic temperatures [11, 12]. This behavior differs markedly from the
predictions of drift-diffusion theory for fabricated p-n junctions for which
$n$ is close to unity and independent of temperature, and the transconductance
increases inversely with temperature. [13, 14] Because the minimum noise
temperature is directly proportional to $n(T)$ in the low-frequency and low
base-resistance limit (see [4, Eq. 2]), identifying the physical origin of the
discrepancies is necessary to improve the cryogenic microwave noise
performance of SiGe HBTs.

The cryogenic non-ideal behavior has been attributed to various mechanisms
including quasiballistic transport [10, 9], direct tunneling [11], or trap-
assisted tunneling [15]. However, a theoretical study has reported that
quasiballistic electron transport cannot explain the observed collector
cryogenic non-idealities [16]. Recent works indicate that direct tunneling
across the base can account for the non-idealities in highly-scaled devices
[12, 11, 5, 17]. At the same time, non-idealities have been observed in
devices with base widths of $\sim$100 nm [9, 5] for which direct tunneling is
negligible. This observation suggests that, in addition to tunneling, another
mechanism may contribute to cryogenic non-ideal current-voltage
characteristics in SiGe HBTs.

In a different context, similar anomalies have been observed and extensively
investigated in Schottky diodes [18, 19, 20, 21], and they were ultimately
attributed to spatial inhomogeneities in the built-in potential $\Phi_{BI}$.
[22, 23, 24, 25] Although semiconductor junctions are often modeled as uniform
across the lateral area, in fact various imperfections exist which affect the
local electronic structure of the junction, a point which was recognized as
early as 1950. [26] Even at epitaxial interfaces, it was found that different
crystallographic orientations [27, 28, 29] or the presence of dislocations
[30, 31] can lead to potential barrier height variations on the order of
hundreds of mV. In Schottky junctions, these inhomogeneities have been
directly observed using ballistic electron emission microscopy. [32, 33]
Various theories and numerical analyses of the electrical characteristics of
inhomogeneous junctions have been reported and lead to compatible conclusions.
[24, 22, 23] For concreteness, the theory of Werner and Güttler assumes a
Gaussian distribution of barrier heights and makes several predictions
regarding the temperature-dependence of the ideality factor and the relation
between the built-in potential as measured by different methods. [23, 34, 35]
However, an experimental test of these predictions for SiGe HBTs has not yet
been reported.

Here, we perform this experimental investigation by characterizing the
collector current ideality factor and built-in potential of a SiGe HBT from
room to cryogenic temperatures. We find that the measured temperature-
dependence of the ideality factor and the relation between built-in potential
as determined by capacitance-voltage and current-voltage characteristics are
compatible with the theory predictions. This observation suggests that
inhomogeneities in the base-emitter junction potential could be a mechanism
affecting the cryogenic current-voltage characteristics in SiGe HBTs. We
discuss how the existence of barrier inhomogeneities could be further
confirmed. Our work advances efforts to improve the cryogenic electrical
characteristics and hence microwave noise performance of SiGe HBTs.

##  II  Theory and Methods

###  II.1 Overview

The theory of Werner and Güttler describes electrical transport across a
potential barrier with heights distributed according to a Gaussian
distribution of a specified mean and variance. [23] The variance of the
distribution is assumed to decrease with increasing junction bias due to the
pinch-off of low-barrier patches of dimension less than the depletion length,
a concept that was originally introduced in [24] and later developed in [22].
The theory makes several predictions regarding the trends of electrical
characteristics with temperature and other parameters in junctions exhibiting
voltage-independent ideality factors $n(T)$. In particular, $n(T)$, as
determined from the slope of $I-V$ characteristics, is predicted to vary with
temperature according to $n(T)^{-1}-1=-\rho_{2}+\rho_{3}/(2kT/q)$ where $k$ is
Boltzmann’s constant, $q$ is the electric charge, and $\rho_{2}$ and
$\rho_{3}$ are constants describing the variation of the mean and variance of
the potential barrier distribution with junction voltage, respectively (see
[23, Eq. 23]). A plot of $n(T)^{-1}-1$ versus $T^{-1}$ should therefore yield
a line over some range of temperatures.

In addition, the built-in potential $\Phi_{BI}$ can be measured in two ways.
From $C_{BE}-V_{BE}$ characteristics, $\Phi_{BI}(CV)$ can be obtained by
fitting the variation of depletion capacitance with junction voltage using
$C_{BE}(V_{BE})=C_{BE,0}(1-V_{BE}/\Phi_{BI})^{-m}$, where $C_{BE,0}$ is the
zero-bias junction capacitance and $m$ is an exponent that depends on the
doping profile at the junction. [14] Using $I_{C}-V_{BE}$ characteristics, the
potential barrier energy for transport, $E_{a}$, relative to its value at some
temperature, can be obtained by extrapolating the measured collector current
to zero bias using the collector current expression
$I_{C}=I_{S}(\exp({qV_{BE}/n(T)kT})-1)$ where $I_{S}=A\exp(-qE_{a}/kT)$ is the
transport saturation current and $A$ is a constant prefactor. [1, Sec. 4.2.1]
We have neglected the polynomial temperature-dependence of the prefactor as it
only makes a log-scale correction to the built-in potential which does not
alter our conclusions.

With the value of the transport barrier at 300 K specified as $\Phi_{BI}(CV)$,
the temperature-dependence of the apparent built-in potential associated with
charge transport $\Phi_{BI}(IV)$ can thus be obtained from the value of
$I_{S}$ at each temperature relative to that at the reference temperature. We
note that this charge injection approach to model the current-voltage
characteristics is relatively simple compared to generalized-integral charge-
control relation (GICCR) models employed for HBTs. [36] However, GICCR models
also exhibit discrepancies with experiment below 100 K, [37, Fig. 6.5(a)]
suggesting that the physical origin is not due to the simplicity of the charge
injection model.

The inhomogeneous junction theory predicts that the barrier measured in these
two ways should differ in magnitude and temperature dependence owing to the
fact that current depends on $V_{BE}$ exponentially while the capacitance
varies with $V_{BE}$ with a weaker polynomial dependence. The barrier as
determined through $C-V$ characteristics is therefore typically interpreted as
the mean barrier height, while that determined from $I-V$ characteristics is
often less than the mean value due to the larger contribution from low-barrier
regions. [38, 23] The theory gives a relation between these barrier heights.
[23, Eq. 14] Considering the form of $n(T)$ described above, this relation is
compatible with the empirical observation that $\Phi_{BI}(CV)\approx
n(T)\Phi_{BI}(IV)$ [39] (see also [23, Sec. V]).

These predictions can be tested using a cryogenic probe station to measure the
$I_{C}-V_{BE}$ and $C_{BE}-V_{BE}$ characteristics of a SiGe HBT. We note that
for the $C_{BE}-V_{BE}$ characteristics, although the mechanisms of current
transport in the forward active regime differ between Schottky junctions and
HBTs, the electrostatics of the depletion capacitance are identical between
the devices. [40, Chaps. 6 and 7] Therefore, the built-in potential can be
determined by the dependence of $C_{BE}$ on $V_{BE}$ for biases for which
$C_{BE}$ is dominated by the depletion capacitance. This procedure was applied
to determine the built-in potential of SiGe HBTs in another study. [12]

###  II.2 Experimental methods

We extracted $\Phi_{BI}$ from $C_{BE}-V_{BE}$ and $I_{C}-V_{BE}$
characteristics from 20 – 300 K on a SiGe HBT (SG13G2, IHP). The discrete
transistors were probed in a custom-built cryogenic probe station. [41, 42] We
employed Nickel/Tungsten probes (40A-GSG-100-DP, GGB Industries) which are
suitable for probing Al pads. $I_{C}-V_{BE}$ characteristics were performed at
a constant collector voltage $V_{CE}=1$ V to provide a collector current above
the minimum resolution of our measurement setup (10 nA). The current range
used for this fitting is limited to 0.2 mA, below the high-injection regime,
to exclude effects of series resistance, self-heating and the Early and
reverse Early effects. Inclusion of the reverse Early effect in the extraction
of the built-in potential was found to alter the value by only a few percent
as it enters the expression for the $\Phi_{BI}$ as a log-scale correction.
$\Phi_{BI}$ was extracted relative to its value determined by $C_{BE}-V_{BE}$
measurements at 300 K from the zero-bias intercept of a linear fit of
$\ln(I_{C})$ versus $V_{BE}$, and $n(T)$ was extracted from the slope of this
fit. Due to the difficulty of distinguishing periphery from area currents, we
assumed that the area current is dominant following other studies of cryogenic
SiGe HBTs. [11, 17, 12, 5, 10]

Following standard procedure, [12, 13] $C_{BE}-V_{BE}$ characteristics were
obtained using a vector network analyzer (VNA, Keysight E5061B). In reverse-
bias and low-forward bias regimes, the $Y$-parameters are given by
$Y_{11}=g_{BE}+j\omega(C_{BE}+C_{BC})$ and $Y_{12}=-j\omega C_{BC}$, where
$C_{BC}$ is the base-collector depletion capacitance. The base-emitter
capacitance can therefore be expressed as $C_{BE}=(\Im(Y_{11}+Y_{12}))/2\pi
f$. $V_{BE}$ was restricted to [$-0.5$ V, $+0.5$ V] to ensure that the
measured capacitance was dominated by the depletion capacitance. $V_{BC}=$ 0 V
was held constant to ensure $C_{BC}$ was constant while $V_{BE}$ was swept.
The $Y$ parameters were measured in $1-3$ GHz, and the extractions were
performed at 2.4 GHz. At these frequencies, it was observed that the imaginary
part of $Y_{11}$ was linear in frequency, indicating purely capacitive
behavior. Short-Open-Load-Through calibration was performed on a CS-5
calibration standard at each temperature, and the shunt parasitic capacitance
at the input of the device was de-embedded using an OPEN structure. The
intermediate-frequency bandwidth (1 kHz) and frequency points (every 0.2 GHz)
were selected to limit the total sweep time to less than 15 s to avoid drift.
At each bias, Y-parameters were swept across frequency and ensemble-averaged
10 times. $\Phi_{BI}$ was extracted from a sweep of $C_{BE}$ versus $V_{BE}$
by fitting the parameters $\Phi_{BI}$, $C_{BE,0}$ and $m$ using a trust region
reflective algorithm from the SciPy library. [43] $\Phi_{BI}$ was constrained
to [0.5 V, 1.2 V], $C_{BE,0}$ was constrained between the minimum and maximum
values of the sweep, and $m$ was constrained to [0, 1].

##  III  Results

Figure 1: (a) Measured $I_{C}$ versus $V_{BE}$ for various temperatures. The
characteristics become independent of temperature at cryogenic temperatures.
(b) $T_{eff}=n(T)T_{phys}$ vs $T_{phys}$ from measurements (symbols) and diode
theory (line), indicating the non-ideality of the base-emitter junction at
cryogenic temperatures.

Figure 2: (a) Measured $\Im(Y_{11}+Y_{12})/\omega$ (symbols) versus $f$ at 300
K for various $V_{BE}$ in steps of 0.1 V. The lines are guides to the eye. (b)
Measured (symbols) and fitted (solid lines) $C_{BE}$ versus $V_{BE}$ at 300 K,
80 K and 20 K. As a representative example, the fit for 300 K yields
$\Phi_{BI}=0.83$ V and $m=0.10$.

Figure 1 shows the collector current $I_{C}$ versus $V_{BE}$ at various
temperatures between 20 K and 300 K. Consistent with prior findings, [5, 10,
11] the measurements exhibit deviations with drift-diffusion theory at
cryogenic temperatures, with the current-voltage characteristic plateauing to
a temperature-independent curve below $\sim$60 K. We plot the extracted $n(T)$
as $T_{eff}=n(T)T_{phys}$ versus $T_{phys}$ in Figure 1. $T_{eff}$ is observed
to plateau to $\sim$100 K due to $n(T)>1$ at cryogenic temperatures, as has
been reported previously [10].

We next examine the RF characteristics. Figure 2 plots
$\Im(Y_{11}+Y_{12})/\omega$ versus $f$ for various $V_{BE}$ at 300 K, where
$\omega=2\pi f$. A narrowed frequency range from the $1-3$ GHz measurements is
plotted to aid in distinguishing the curves. The de-embedded base-emitter
capacitance $C_{BE}$ is directly obtained from this plot by averaging across
the frequency range. Figure 2 plots the resulting $C_{BE}$ versus $V_{BE}$ at
three representative temperatures across the overall voltage range along with
the fitted curves. The error bars, representing the 2$\sigma$ error in
$C_{BE}$, are obtained from the 10 $C_{BE}-V_{BE}$ sweeps performed at each
temperature.

These data are next analyzed to obtain $\Phi_{BI}$ from the $I_{C}-V_{BE}$ and
$C_{BE}-V_{BE}$ characteristics according to the procedures in Section II.2.
At 300 K, $\Phi_{BI}(CV)$ is found to be 0.83 V, in good agreement with [12].
This value is specified as the room temperature value for $\Phi_{BI}(IV)$ to
facilitate comparison at other temperatures. Figure 3 plots the $\Phi_{BI}$
from both measurements versus $T_{phys}$. For $\Phi_{BI}(CV)$, the error bars
represent the 2-$\sigma$ error in $\Phi_{BI}$, obtained by performing fits to
100 $C_{BE}-V_{BE}$ sweeps with errors randomly determined based on a normal
distribution defined by the uncertainty in the measured $C_{BE}$. The
extracted $\Phi_{BI}(CV)$ is observed to weakly increase with decreasing
temperature, consistent with observations for similar HBT devices [12] and
Schottky diodes [39]. In contrast, $\Phi_{BI}(IV)$ exhibits a qualitatively
stronger dependence on temperature than $\Phi_{BI}(CV)$ and differs markedly
in magnitude at cryogenic temperatures, as observed previously for Schottky
diodes [39, 13] (also compare to [34, Fig. 3]). The variation with temperature
of $\Phi_{BI}(IV)$ is significantly stronger than that of the emitter and base
band gaps, [14] suggesting another mechanism is responsible for the observed
temperature trend.

Figure 3: (a) Built-in potential $\Phi_{BI}$ versus physical temperature from
$C_{BE}-V_{BE}$ (black circles) and $I_{C}-V_{BE}$ (orange triangles)
measurements. Also plotted is $n(T)\Phi_{BI}(IV)$ (green squares) which is
predicted to agree with $\Phi_{BI}(CV)$. [23] Good agreement is observed. (b)
$n(T)^{-1}-1$ versus inverse physical temperature $T^{-1}$ for measured data
along with a linear fit to the data in 40-100 K following the prediction in
[23]. Data obtained from [10, Fig. 5.8] are also shown.

We now examine the agreement between the data and the predictions from the
inhomogeneous junction theory of [23]. First, qualitatively, $\Phi_{BI}(CV)$
and $\Phi_{BI}(IV)$ are predicted to differ, with $\Phi_{BI}(IV)$ expected to
exhibit a stronger temperature dependence and be smaller in magnitude than
$\Phi_{BI}(CV)$. This behavior is observed in Figure 3. More quantitatively,
for the predicted temperature-dependence of $n(T)$ from the theory, it is
expected that $\Phi_{BI}(CV)\approx n(T)\Phi_{BI}(IV)$ [23, Sec. V]. The
product $n(T)\Phi_{BI}(IV)$ is also plotted in Figure 3, demonstrating good
agreement with $\Phi_{BI}(CV)$.

Second, [23, Eq. 23] predicts that $n(T)^{-1}-1$ versus $T^{-1}$ should be a
straight line over some range of temperatures. Figure 3 plots this quantity
for the present device and other devices with data obtained from [10, Fig.
5.8]. For all the devices, the expected trend is observed over a temperature
range which is comparable in relative width to that in [23, Fig. 9]. For the
older-generation devices, the linear trend is observed from 18 – 100 K. For
the present device, a linear regime is found from 40 – 100 K, while a
deviation is noted at 20 K. These data are consistent with the absence of
tunneling in the older devices and a non-negligible direct tunneling current
in the present device. Other explanations for the deviation could include the
assumption of temperature-independent barrier properties in the inhomogeneous
barrier theory. However, overall the experimental trends are in good
qualitative agreement with the theoretical predictions.

Semi-quantitative information regarding the variation of the barrier height
variance with bias for the present device can be obtained from the linear fit
in Figure 3. If $\rho_{2}+\rho_{3}/(2kT/q)\ll 1$, the theory of [23] reduces
to the $T_{0}$ model for non-ideal junctions which has been extensively
studied in the Schottky junction literature. [19, 22, 23] In this case, the
slope of the linear fit in Figure 3 is simply $T_{0}$. Performing this fit for
the present data yields $T_{0}\approx 30$ K, a value which is generally
compatible with values for Schottky diodes compiled in [23]. Using [23, Eq.
33], this value can be recast in terms of the narrowing of the potential
barrier height distribution with increasing bias using
$\rho_{3}\approx-2kT_{0}/q$. We obtain a value $\rho_{3}=-5.2$ mV. The
magnitude of this value indicates that changes in standard deviation of the
potential barrier height distribution with base-emitter bias which are less
than a percent of the mean barrier height are sufficient to account for the
observed electrical anomalies.

##  IV  Discussion

The agreement of our data with the predictions of the inhomogeneous barrier
theory suggests that lateral inhomogeneities in the base-emitter junction
potential could contribute to the cryogenic electrical anomalies. Additional
evidence for the barrier inhomogeneity hypothesis could be obtained using
techniques such as ballistic emission electron microscopy which directly
measures the spatial profile of the built-in potential. [33] However, applying
this method to SiGe HBTs would require specialized samples to be prepared
which are compatible with the measurement technique.

The materials-scale origin of the inhomogeneities in HBTs could be Ge clusters
[44] or electrically active carbon defects [45]. Non-uniform Ge content over a
few nanometers in SiGe p-wells with Ge concentration $\geq$ 30% has been
reported to lead to the degradation of electrical properties like hole
mobility. [44] Trap states associated with C impurities have also been
detected in modern HBTs. [45] With Ge concentrations for modern HBTs being on
the order of 30% [11] and C doping on the order of $10^{20}$ cm-3, [1] these
defects lead to an inhomogeneous base-emitter junction potential. If the
presence of spatial inhomogeneities across the emitter area is verified, a
less aggressive Ge doping concentration and profile, especially in narrow-base
SiGe HBTs, could decrease the concentration of these imperfections and thereby
lead to a more uniform base-emitter junction potential. However, care would
need to be taken to avoid negatively impacting the high-frequency properties
of the device. Additionally, direct tunneling may pose a fundamental obstacle
to improving the cryogenic electrical ideality of highly-scaled devices.
Further study is needed to distinguish the various mechanisms and identify the
limits to cryogenic electrical ideality and hence microwave noise performance.

##  V  Conclusion

We have reported a characterization of the collector-current ideality factor
and built-in potential versus temperature of a SiGe HBT. The observed trends
with temperature and between measurement techniques agree with a theory of
electrical transport at a potential barrier with a Gaussian distribution of
barrier heights, suggesting that barrier inhomogeneities may contribute to
cryogenic electrical non-idealities in SiGe HBTs. This work advances efforts
to improve the cryogenic microwave noise performance of SiGe HBTs.

## Acknowledgments

The authors thank Akim Babenko, John Cressler, Nicolas Derrier, Xiaodi Jin,
Pekka Kangaslahti, Holger Rücker, Michael Schröter, and Sander Weinreb for
useful discussions. This work was supported by NSF Award Number 1911926 and by
JPL PDRDF Project Number 107978.

## Author Declarations

### Conflict of Interest

The authors have no conflicts to disclose.

## Data Availability

The data that support the findings of this study are available from the
corresponding author upon reasonable request.

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