# Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI
CMOS Process

Imran Bashir  Equal1.labs, Freemont, California, USA  Corresponding Authors:
<EMAIL_ADDRESS>ieee.org}<EMAIL_ADDRESS>ucd.ie},
Dirk Leipold  Equal1.labs, Freemont, California, USA  Elena Blokhina
Equal1.labs, NovaUCD, Belfield, Dublin, Ireland  University College Dublin,
Belfield, Dublin, Ireland  Corresponding Authors<EMAIL_ADDRESS>ieee.org}<EMAIL_ADDRESS>ucd.ie},  Mike Asker  Equal1.labs,
Freemont, California, USA  David Redmond  Equal1.labs, NovaUCD, Belfield,
Dublin, Ireland  Ali Esmailiyan  Equal1.labs, NovaUCD, Belfield, Dublin,
Ireland  Panagiotis Giounanlis  Equal1.labs, NovaUCD, Belfield, Dublin,
Ireland  Hans Haenlein  Equal1.labs, Freemont, California, USA  Xutong Wu
Equal1.labs, NovaUCD, Belfield, Dublin, Ireland  Andrii Sokolov  Equal1.labs,
NovaUCD, Belfield, Dublin, Ireland  University College Dublin, Belfield,
Dublin, Ireland  Andrew K. Mitchell  University College Dublin, Belfield,
Dublin, Ireland  Dennis Andrade-Miceli  Equal1.labs, NovaUCD, Belfield,
Dublin, Ireland  University College Dublin, Belfield, Dublin, Ireland  Robert
Bogdan Staszewski  Equal1.labs, Freemont, California, USA  Equal1.labs,
NovaUCD, Belfield, Dublin, Ireland

###### Abstract

The proliferation of quantum computing technologies has fueled the race to
build a practical quantum computer. The spectrum of the innovation is wide and
encompasses many aspects of this technology, such as the qubit, control and
detection mechanism, cryogenic electronics, and system integration. A few of
those emerging technologies are poised for successful monolithic integration
of cryogenic electronics with the quantum structure where the qubits reside.
In this work, we present a fully integrated Quantum Processor Unit in which
the quantum core is co-located with control and detection circuits on the same
die in a commercial 22-nm FD-SOI process from GlobalFoundries. The system
described in this work comprises a two dimensional (2D) 240 qubits array
integrated with 8 detectors and 32 injectors operating at 3 K and inside a
two-stage Gifford -McMahon cryo-cooler. The power consumption of each detector
and injector is 1 mW and 0.27 mW, respectively. The control sequence is
programmed into an on-chip pattern generator that acts as a command and
control block for all hardware in the Quantum Processor Unit. Using the
aforementioned apparatus, we performed a quantum resonant tunneling experiment
on two qubits inside the 2D qubit array. With supporting lab measurements, we
demonstrate the feasibility of the proposed architecture in scaling-up the
existing quantum core to thousands of qubits.

##  1 Introduction

Several quantum computing technologies are making inroads in the market today.
The most commercially prevalent is the superconducting transmon qubit where a
flux tunable critical current in a Josephson junction loop [1, 2] or
superconducting quantum interference device (SQUID) controls the Pauli
rotation about an axis on the Bloch sphere. The apparatus driving the transmon
qubit is expansive (Fig. 1 in ref. [3]). In order to reduce the thermal
excitation of the system, the transmon is placed in a dilution fridge
operating at a base temperature of 10 mK. In this state, the flux-tunable
transmon behaves like a quantum mechanical system where the driving signal
amplitude or phase controls the XY rotation. The drive signal is generated by
a rack mount arbitrary waveform generator (AWG) which is passed through
mixers, attenuators, and couplers. The transmon qubit also includes a DC
current port to tune the qubit resonance frequency and the current into that
port is sourced by bias DACs. Lastly, the transmon qubit has a read-out port
which is AC-coupled to a resonator. The qubit’s state is determined by
coupling an RF signal to the resonator and measuring the amplitude or phase
shift of the reflected signal. The RF signal is coupled to the qubit through
circulators and attenuators, while the reflected signal is amplified in
multiple stages before being sourced to a measurement system. All the rack-
mount control equipment such as AWGs, bias DACs, signal generators, and signal
analyzers are located at room temperature whereas the couplers, mixers,
attenuators, and circulators are strategically placed at multiple stages in
the dilution fridge. Specialized coax cables for RF signals are used at each
stage to minimize active and passive heating, especially at the base
temperature stage where the thermal load of the dilution fridge (such as
Bluefors XLD400 DR) is 19$\mu$W [4]. This apparatus works reasonably well for
small qubit counts (50-100) where the reported error rate is on the order of
0.1$\%$ [5] and the qubit relaxation time ($\rm T_{1}$) is 18.3$\mu$s [6].
However, a fault-tolerant system requires a significantly large number of
qubits which poses a challenge to the aforementioned approach when considering
the amount of equipment, cabling, active and passive components required to
facilitate control and read-out operation on such a quantum processor. Other
challenges to scaling this technology to millions of qubits include frequency
collision and crowding [7].

Figure 1: The quantum computer apparatus and top-level architecture. (a)
Complete functional view of the quantum computer with cabling. The breakdown
of the wiring on the flex cable is also shown. The 16 analog I/O wires are
routed to the eight (8) on-chip detectors and can be eliminated with on-chip
A/D. (b) Block level architecture of the Quantum Processor Unit. The 2D
quantum structure, shown as (transmission electron microscopy) TEM micrograph,
is co-located with control and read-out electronics on the same die. (c)
Graphical representation of the Cryocooler apparatus and the interface between
the IC and room temperature electronics.

On the other hand, semiconductor qubits offer a more efficient path to scaling
[8]. In this technology, an electron’s position or spin is manipulated while
they are confined in nanoscopic-scale quantum dots [9]. The number of qubits
is scaled by placing a large number of quantum dots in an array. Pauli
rotations are typically performed by driving a microwave signal and/or
appropriate DC biasing to a control node to manipulate the electron’s
tunneling or spin blockade process while the qubits are placed in a dilution
fridge with a base temperature of 20 mK. Read out can be done by sensing
charge, current, or phase (for a gate-dispersive read out [10]). The key
benefit of this approach is the advanced lithography process with which
quantum dots with diameters as low as 45 nm [11] have been fabricated.
However, the decoherence process of such qubits can be influenced by the
nanoscopic charge fluctuation from the 28Si/28SiO2 interface. That said, the
qubits manufactured using this process have achieved a spin relaxation time
($\rm T_{1}$) of 1.6 s, a spin dephasing time ($\rm T_{2}$) of 24 $\mu$s and
single qubit gate fidelity of 99 $\%$ [11]. Scaling the spin qubits count to
millions will pose a challenge to route a large number of drive channels to
the qubit array, especially when the control equipment resides at room
temperature. The same will be true for detection channels if a gate-dispersive
read-out method is used.

The obvious solution to cable management of a large number of wide-bandwidth
I/O channels for qubit operation is to simplify the interface by deploying the
control and detection hardware inside the cryocooler and closer to the qubit
substrate. This complex integration task requires intimate knowledge of the
cooling power and active and passive heat dissipation from circuits and
cabling at each stage in the cryocooler. The first stage of the dilution
fridge typically has a pulse tube cryocooler operating at 3 K with a thermal
load specification of 1.5 W. This would be an ideal environment for a
controller chip capable of driving a large number of excitation signals into a
qubit processor while the number of wires to and from the room temperature
electronics is reduced to a few control and trigger lines. Such controllers
have been reported for transmon qubits [6] and spin qubits [12, 13]. The same
concept has been applied to cryogenic detectors for spin qubits using gate-
dispersive read-out [14] and transimpedance amplifiers[15]. In another
published integration scenario, the qubit substrate and the controller IC is
bonded to a common substrate at an elevated temperature stage of 100 mK [16]
while the driving circuits generating the excitation signal used a switch
capacitor topology. The typical cooling power at this stage is 200 $\mu$W,
which is ten times higher than the 20 mK stage, however it is not large enough
to accommodate meaningful integration with large number of channels. In
another published work, the controller chip with single channel driver and
detector was integrated with a double quantum dot structure on the same die
[17] operating at 110 mK. That solution cannot be scaled to a large qubit
count due to the limited cooling power at the 110 mK stage.

This concludes the discussion on prior art and their unique characteristics.
The benefits of the approach suggested in this paper and their distinction
with the aforementioned references will be discussed in detail in the next
section.

##  2 Key Innovation Factors

The architecture that will be described in this paper is unique from the prior
art in several ways. Firstly, the cryogenic quantum control and read-out
system is integrated with a two-dimensional (2D) qubit array in a single chip
operating at 3 K as shown in Fig. 1(a). The result is a simplified and
seamless interface between the cryogenic electronics and the qubit array. Only
30 wires are routed over a “flex" cable to the apparatus at room temperature.
In addition to the flex cable, a single RF coax cable connects the IC to an
external signal generator to receive the system clock. The digitization of the
read-out signal is currently off-chip but can be straightforwardly relocated
on-chip, reducing the wire count to the room temperature apparatus to just 14.
The thermal load of entire apparatus shown in Fig. 1(a) is 21 mW (see
“Methods” section) which consumes only 1.5$\%$ of the 1.5 W cooling power at 3
K. The chip comprises an array of Quantum Processor Units (QPUs) as shown in
Fig. 1(b). Each QPU houses a unique Quantum Core or the 2D qubit array. The
qubit array is initialized by the reset transistors connected to the Quantum
Point Contact (QPC) at the edges of the qubit array. This node is also shared
with the detectors utilized during the read-out phase of the quantum
experiment. The excitation signals for the qubits are sourced from digitally
controlled injectors that are clocked by a high-speed pulse generator. The DC
biasing of the qubit array is sourced from the Quantum Reference Bias Circuit
(QRBC) coupled to the injectors [18]. Lastly, a pattern generator acts as a
command and control block for all the aforementioned hardware interfacing the
qubit array. The localized routing between the cryogenic electronics and the
qubit array results in a power efficient control and detection system.

The second unique feature is the nature of the position-based charge qubit.
The quantum dots in the qubit array shown in Fig. 1(b) are arranged over two
rows in a “double-V” pattern [19]. In each row, the quantum dots are isolated
by a barrier controlled by an imposer. The QPC acts as a reservoir from which
a single electron is tunneled to the first quantum dot. The qubits are
designed using “standard commercial” CMOS process without any application-
specific tailoring of the layer stack or materials. This means that the thin
film of Si above the oxide [19] is not a pure isotope. Additional nanoscopic
impurities will be present at the 28Si/28SiO2 interface. The quantum
information is encoded in electron’s position controlled by a series of
excitation signals applied at imposers to control the tunneling process of
that electron across multiple quantum dots. The excitation signal can be a
pulse [20] or resonant microwave signal [21]. In a pulse driven mode, the
width of the pulse controls the evolution of electron’s wave function between
the quantum dots while the DC biasing from the QRBC imposes a potential
distribution across the wells [22]. In other words, the electron’s position or
occupancy across quantum dots varies over the duration of the pulse at a rate
known as Rabi Frequency. In the microwave driven mode, the excitation
frequency must be resonant with Larmor frequency, which is determined by the
difference between the ground and excited energy levels, while no DC magnetic
field is applied to the qubit array. Once the quantum operation concludes, the
read-out phase begins. During the read-out phase, the final state of the qubit
is measured by sensing the charge present on the QPC node.

The third unique feature is the switched-capacitor topology of the cryogenic
electronics. The signals driving the imposers in the qubit array can be
synthesized with simple and power-efficient circuits labeled as injectors in
Fig. 1(b). No active DC biasing is used in that block and the resulting
transfer function is dependent primarily on the capacitors used in the design.
Modeling of such circuitry can be done with reasonable accuracy as there is no
dependency on transistor’s $V_{t}$ or active currents which will vary
significantly over temperature. The operating temperature is 100$\times$ lower
than room temperature and consequently the $\frac{kT}{C}$ is lower.
Furthermore, the experimental data (see Sec. 4) proves that the charge can be
stored on a capacitor for 100’s of $\mu$s due to the reduced leakage current
at 3 K.

The fourth distinction is the system apparatus shown in Fig. 1(c). There is no
bulky passive RF circuitry or magnets. The qubit array is designed in a flip-
chip package and soldered onto the DUT PCB such that the backside of the die
is flush with the cold finger at 3 K. The DUT PCB and flex cabling reside
inside a heat shield with a penetration at the top for a two-stage Gifford-
MacMahon (GM) cryocooler head. Helium-3 flows in the cryocooler through pipes
connected between the compressor and the cryocooler head. The entire apparatus
in Fig. 1(c), except for the compressor sits, inside a 6-ft server rack.

The aforementioned distinctions can also serve as headwinds in the qubit
performance. The first and foremost is the elevated temperature of the qubit
array as a direct consequence of the single-chip integration and the thermal
load specification of the cryocooler. Moreover, without a pure 28Si isotope,
the decoherence process of this “hot” qubit array is influenced by the
nanoscopic charge fluctuations caused by impurities. That said, characterizing
the performance of charge and spin qubits under non-ideal conditions is an
active area of research. Recently, Ramsey decay (T2) of 75 ns and 200 ns was
measured for a spin qubit at 3.5 K and 1 K respectively [23]. Once performance
trade-offs are understood and experimentally verified, the scientific
community is likely to converge on a “sweet spot" temperature setting that
addresses the challenges in scaling and integration with an acceptable qubit
fidelity. The architecture presented in this paper is a practical
demonstration of a reasonable compromise between these critical parameters.
The reduced decoherence times, as a result of this compromise, also imply that
the qubits must be ultrafast in terms of gate flip times. Such architectures
are well suited for hybrid classical-quantum algorithms that operate on low-
depth circuits.

Next, we will detail each block within the Quantum Processor Unit.

##  3 The Quantum Processor Unit (QPU)

###  3.1 Quantum Core

Figure 2: Details of Quantum Process Unit floor plan and the Quantum Core (a)
Quantum Process Unit floor plan. The injectors are placed above and below
while the detectors are placed on the left and right side of the 2D qubit
array. (b) Detailed drawing of Rows 5 and 6 in the 240 qubit array spanning.
The coupled quantum dots are colored blue. (c) TEM photograph of the 240 qubit
array. (d) Zoomed version of region ’A’ in (c) showing the detector source
follower and the reset transistor. (e) Layout design of the heat shield around
the quantum structure.

The quantum processor unit contains the 2D 240-qubit array and all control
electronics in a 250 $\mu$m$\crossproduct$500 $\mu$m cell as shown in the
floor plan in Fig. 2(a). 32 injectors and 8 detectors surround the quantum
structure. All circuitry is at a distance of 10 $\mu$m from the quantum core.
The area of the quantum structure is 4 $\mu$m$\crossproduct$2 $\mu$m, which is
much smaller than the injector and detector circuits, and therefore, the wires
from the quantum core have to fan-out to the surrounding circuits. The
injectors comprise digital back-end and analog front-end circuitry. The analog
front-end is an array of 16 capacitive DACs arranged in a tile [24]. The DAC
input code is stored in registers residing in the digital back-end along with
custom synthesized logic. The clocks for these CDACs are sourced from the
high-speed pulse generator, which is located in the lower half of the cell and
next to a 2 GHz CLK pad. For the detector electronics, the CDS outputs are
connected to a common row bus that is routed to the last stage of the detector
chain. The map of the 240-qubit array and its TEM photograph is shown in Fig.
2(b) and (c), respectively. The 2D array is split into 8 rows and each row has
30 quantum dots. The notation of each quantum dot is $\rm QD(x,y)$ where “x”
and “y” indicate the row number (range 1–8) and the position (range 1–30). The
solid line between the quantum dots indicates an imposer. The edge of each row
terminates into a quantum point contact ($\rm QPCX_{L,R}$) and the imposer
(colored pink) between the $\rm QPCX_{L,R}$ node and the first quantum dot is
controlled by CDACs labeled $\rm I_{Ux}$. The voltage from this CDAC controls
the barrier and facilitates the transfer of a single electron from the QPC
node to the first quantum dot. The remaining imposers control the tunneling of
electron between neighboring quantum dots and perform Pauli rotations. The 8
rows in the 2D array are staggered, and when the line representing the imposer
extends from one row to the next, it indicates that the imposers in those rows
are controlled by a common CDAC. The sharing of CDACs is more frequent towards
the middle of the array. The $\rm QPCX_{L,R}$ node is connected to reset and
the source follower transistor as shown in the layout drawing in Fig. 2(d).
Both of these devices are located close to the quantum structure in order to
minimize the capacitance on QPC, which impacts the change in voltage as a
result of single-electron transfer from this node. The reset transistor is a
combination of four (4) stacked devices. A clearance of 10 $\mu$m is used
around the quantum structure to facilitate routing which is done in low-level
metal layers. Additional thermal insulation comes from a metal shield placed
on an intermediate-level copper metal layer above the quantum structure. That
layer is tied to the substrate with contacts around the 2D qubit array as
shown in Fig. 2(e). The shield is tied to the straps running horizontally and
vertically on the thick copper layers, which connect with three ground pads
located near the quantum structure.

###  3.2 Quantum Reference Bias Generator

Figure 3: Quantum Reference Bias Circuit (QRBC). (a) Top level block diagram.
(b) Single VDAC stage. The charge is redistributed between $\rm C_{1}$ and
$\rm C_{2}$. (c) Two cascaded VDAC stages. (d) VDAC signal sequence for output
ramp up and down.

The quantum reference bias circuit is detailed in Fig. 3. The three critical
nodes targeted for the dc biasing are the reset switch MrstL drain RD, gate
RG, and imposer gates IU/Dx ($x=1,2,\cdots$). Their respective baseline
voltages are VRDPRE, VRGPRE, and VIPRE. All these biases are sourced from a
common reference VREF that is external to the IC and has a long-term stability
specification within $\pm$200 ppm. VREF is located on the control PCB outside
the cryocooler. Two voltage followers (VF) drive the reference input VREF to
the VDAC1 and VDAC2 blocks. The VDAC blocks are switched-capacitor arrays that
redistribute the charge between C1 and C2. Each VDAC comprises two cascaded
stages for coarse and fine-tuning. The digital $\Sigma\Delta$ block generates
pulses to discharge C1 (DC), charge C1 (CH), and transfer charge (SC) to C2
based on an 8-b input. At the start, the DC, CH, and SC signals are pulsed in
a sequence to ramp the output gradually towards the target. Once the output is
around the target voltage, the CH pulse activity decreases. At this point, the
resolution of the VDAC is approximately 300 $\mu$V given the capacitor ratio.
Then, the second stage can be activated for finer adjustments to hit the
target value. Next, the clock activity ceases, and the VDAC output is frozen
before the CDAC pre-charge (PC) switch is enabled just before the quantum
experiment commences. From this point onwards, any adjustment above or below
the pre-charge level applied to the qubit array can be dynamically shifted by
the CDACs based on their unique 8-bit digital control. VRDPRE is generated by
Vgs of a replica of the Mpre reset switch, MRpre, and it is further adjusted
by the 8-bit current DAC (IDAC) with a range from a few nA to 1 $\mu$A (max).
In order to generate a negative VRDPRE, IDAC VSS is set to $-$1 V while MRpre
drain is at 0 V.

Two environmental factors work as tailwinds in this design. One is the reduced
leakage current at cryogenic temperature (see Sec. 4). This implies that C1
and C2 can hold their charge long enough in cryogenic conditions for a quantum
experiment to conclude, which typically takes 100’s of ns. The other aiding
factor is the lower $kT/C$ noise at 3 K, which is 1/100th compared to the room
temperature. Therefore, the capacitor size can be scaled down resulting in a
miniaturized layout. The three internal voltage followers (VF) at the outputs
shown in Fig. 3 are only needed when driving external pads for testing
purposes and can be eliminated. All capacitors in the circuit are MOMCAPs
designed with a stack of 3–5 intermediate metal layers. The circuits are
designed with nominal $V_{\rm th}$ (RVT) transistors without any body biasing
applied while the main supply is 0.8 V. The bias voltages applied to the
quantum core have a maximum limit of 0.8 V-$V\rm{{}_{th}}$ and a minimum limit
of -1 V+$V\rm{{}_{dsat}}$, which is a sufficient range in order to conduct
quantum experiments on the QDA. The typical clock frequency of the
$\Sigma\Delta$ is 125 MHz and the switches in VDACs are sized appropriately to
charge and discharge capacitor C1 during the pulse duration of 8 ns. This
gives reasonable dynamic power dissipation given the specified clock
frequency. At the specified rate, VDAC outputs stabilize within 100 $\mu$s
after activation.

###  3.3 Injector

Figure 4: Injector functionality and noise characteristics (a) Block level
diagram of the injector circuit. (b) Time-domain waveform of the injector
output. The gray mesh region on the pedestal and step voltage represents
noise. (c) Injector noise analysis with supply and VDAC noise at inputs. The
noise is injected from the pre-charge and CDAC switch capacitor path and is
summed together at the final output. (d) Amplitude response of transfer
function of Pre-charge and CDAC path. (e) The VDAC and VDD noise spectra at
the injector output. The noise from pre-charge path dominates the cumulative
noise. (f) Noise model parameters and output noise summary.

The principal function of the injector [24] is to manipulate the reset device
before and during the quantum experiment, control the barrier at the single-
electron injection device, and to excite the imposers to control the evolution
of electron’s wave function in the intermediate quantum dots. The block
diagram shown in Fig. 4(a) illustrates the injector function. First, the
imposer node labeled $\rm I_{Ux}$ or $\rm I_{Dx}$ is pre-charged to a bias
voltage $\rm V_{biasX}$ which is sourced from VDAC output inside the Quantum
Reference Bias generator. This sets the pedestal of the voltage pulse shown in
Fig. 4(b). Next, the digital code $\rm b_{X}$ activates the switch capacitor
array, and a charge transfer takes place between $\rm C_{u1}$ and $\rm
C_{u3}$. This elevates the injector output by $\Delta\rm V$, which is
digitally controlled. The 11-stage RC filter has a pole beyond 100 GHz and
filters any ultra-fast transients on the imposer node.

The transfer function analysis shown in Fig. 4(c) considers the noise
contribution from two paths: the pre-charge path and the switch capacitor
array of the CDAC path. $S_{\rm VDD}$ and $S_{\rm VDAC}$ are the PSD of noise
voltage on the $V_{\rm DD}$ supply and VDAC output, respectively. The transfer
functions $H_{\rm RCPC}$ and $H_{\rm RCCDAC}$ model the RC filter formed by
the switch resistance and output node capacitance. $H_{\rm SHPC}$ and $H_{\rm
SHCDAC}$ model the aliasing of input noise due to the sample and hold
operation[25] and is impacted by the timing parameters $\tau_{\rm p}$,
$\rm\tau_{PC}$, and $\tau_{\rm clk}$. The formulas for these two transfer
functions are derived in the “Methods” section. $\rm C_{div}$ is a scaling
factor due to capacitive divider formed by $\rm C_{u1}$ and $\rm C_{u3}$. The
noise spectra in the pre-charge and CDAC paths are integrated over frequency
and the resulting noise power is added to $\frac{kT}{C}$ noise ($v_{\rm kTPC}$
and $v_{\rm kTCDAC}$) to compute the total noise at the injector output.
Figure 4(d) compares the amplitude response in the “pre-charge” and the CDAC
paths. The gain of the CDAC path is attenuated by $\rm C_{div}$ and,
therefore, the VDAC noise at the injector output dominates the supply noise as
shown in Fig. 4(e). Based on the circuit parameters defined in Fig. 4(f), the
cumulative noise at the injector output is 27.4 $\mu$V-rms.

###  3.4 Detector

Figure 5: Detector chain noise sources and transfer function. (a) Block level
diagram of detector chain. (b) $\rm C_{gd}$ neutralization using bootstrap
device M4. (c) Frequency domain model of the detector chain. (d) $\rm H_{CDS}$
transfer function. (e) Spectra of noise sources used in the model. (f) Noise
contribution from all sources at the detector output. (g) Summary of noise
analysis.

The detector chain, shown in Fig. 5(a) [24], comprises the following stages:
source follower, pre-amplifier, CDS (correlated double sampler), output buffer
(OBUF), interface circuit with LPF, and ADC. The interface circuit and the ADC
are off-chip components. The detector has to interface with a high-impedance
node labeled QPC which is connected to the quantum structure and a reset
device. A detector input impedance, which is substantially higher than the
sourcing node (i.e. QPC) ensures a low loss transmission of the signal from
the source node into the detector. For this reason, the source follower
transistor $\rm M_{3}$ in Fig. 5(b) is designed with minimum dimensions.
However, any parasitic capacitance such as $C_{\rm gd}$ arising from $\rm
M_{3}$ can limit the input impedance of the detector. To address this issue, a
bootstrapping device in the form of a source follower [26] $\rm M_{4}$ is
added to the circuit as shown in Fig. 5(b). This device creates a positive
feedback at node A and forces the voltage at node A and X to move in tandem as
a result of the perturbation caused by movement of charge from QPC during a
quantum experiment. As a result, the current through $C_{\rm gd}$ and hence
the impact of this capacitance is minimized.

Next, the transfer function of the detector chain will be analyzed. Figure
5(c) shows the transfer function from the QPC node till the ADC input. The
source follower $\rm H_{SF}$, the pre-amplifier $\rm H_{PRE}$, and the output
buffer $\rm H_{OBUF}$ transfer functions are assumed to be constant over
frequency with a gain of 0.9, 2.2, and 5.4, respectively. $H_{\rm RC}$ is the
RC response due to switch resistance and sample capacitor ($C_{\rm sx}$) in
the CDS, which has a pole around 70-MHz. $H_{\rm CDS}$ is the CDS transfer
function which also accounts for aliasing of input noise due to the sample-
and-hold operation and is impacted by three parameters shown in the timing
diagram of Fig. 5(c): $\tau_{\rm SH}$, $\lambda$, and $T$. The derivation of
this transfer function is based on [25, 27] and will be described in detailed
in the “Methods” section. Figure 5(d) shows the $H_{\rm CDS}$ amplitude
response with $\tau_{\rm S0,S1}$, $\lambda$, and $T$ set to 80 ns, 100 ns, and
1 $\mu$s, respectively. $H_{\rm INT}$ models the ADC interface designed using
a THS4509 op-amp and a low-pass filter. The resistor values for $R_{f}$ and
$R_{g}$ are chosen such that the gain of the interface is 2. $R_{i}$ sets the
load line for the OBUF circuit, which is operating in class-A.

The spectra of noise sources in the detector are shown in Fig. 5(e). The pre-
amplifier and the source follower noise is modeled as a white noise source in
order to simplify the analysis of noise shaping due to $H_{\rm CDS}$ (see
“Methods” section). The contribution of each noise source at the output is
computed by multiplying the PSD of noise voltage by its respective transfer
function. The results of that exercise are summarized in Fig. 5(f) and (g).
The noise at close-in frequencies is dominated by the pre-amplifier and source
follower due to the aliasing operation in $H_{\rm CDS}$. The composite
integrated noise at the detector output is 17 mV-rms, which is in line with
the measurement reported in [24]. It is important to note that the information
from the quantum experiment that is stored in the capacitors $C_{\rm sx}$ is
band-limited by the RC network modeled by $H_{\rm RC}$.

###  3.5 Pattern Generator (PATGEN)

Figure 6: Pattern Generator, its data path, and four examples of resource
allocation of pattern memory. (a) Data path flow from PATGEN output to the
Quantum Core. The control signals from the pattern drive the Pulse Generator
to synthesize precisely timed signals into the Quantum Core. (b) Signal timing
of Example Script 1 in which an X Pauli rotation is performed using a pulsed
excitation [20]. (c) Signal timing of Example Script 4 in which an X Pauli
rotation is performed using resonant driving [21]. (d) Summary table of four
quantum experiment test scripts and their resource allocation.

The pattern generator (PATGEN), shown in Fig. 6(a), acts as a command and
control block in the Quantum Processor Unit and is integrated with the
extensive electronics and the qubit array. The PATGEN comprises a memory core,
an interface unit, and decoding logic. The interface unit handles the
signaling between the 4-wire SPI and the PATGEN. The 32-kbit memory core has a
depth of 512 while the data output bus is 64-bit wide. The memory core can
store 512 vectors and a vector corresponds to a timing event caused by an
instruction in the programming script. This will be explained in detail
shortly. Inside the QCELL block, the 2 GHz clock is divided to generate CKDIV.
The desired pattern is loaded into the memory core and channeled onto the
64-bit data bus while the timing of the pattern is based on CKDIV clock. The
digital decoding block deciphers the incoming data and routes the information
to two output ports: the control bus for the high-speed pulse generator [28]
and the control and data bus for the Quantum Core. The 16 bit data bus for the
quantum core contains the 8-bit CDAC amplitude word and some control signals.
The remaining 48-bit control lines are clock signals for the 32 CDACs and
control signals (CDS switches) for the eight (8) detectors. The clock and
control signals are generated by the pulse generator and that process is
described next.

The first stage of the pulse generator is a Phase Generator designed using a
16-stage Johnson counter that generates multiple signals with a phase
separation of 500 ps for a 2 GHz clock. The clock frequency also sets the
timing resolution of the pulse generator. Two signals from the Johnson counter
are chosen for a programmable AND/OR operation, which either narrows or
expands a pulse in the Pulse Select block. Up to 8 of these blocks run in
parallel while each leaf cell has its unique set of SEL1, SEL2, and AND/OR
selection codes in order to generate multiple signals with varying pulse-
widths at the same time. This is a useful feature when there is a need to
switch between two different timing profiles seamlessly. Finally, one output
is selected to be passed to the Mode Select block which either propagates the
input to the output or passes it to a SR (set/reset) latch. The latter option
allows the pulse duration to be extended over longer time scales.

After describing the hardware implementation, it is important to discuss the
programming and resource allocation per quantum operation or, more
specifically, an X Pauli rotation. The nature of the Pauli rotation exhibited
by the charge qubit is a function of energy levels and well potential over the
qubit array in addition to the waveform applied to the imposer [29]. The
pattern shown in Fig. 6(b) and its corresponding program script in Fig. 6(d)
(Example Script 1) is an example of a pulse-driven X rotation. This example
has 17 vectors or instructions and each is annotated by a colored font. The
number proceeding the instruction links that instruction with the Pulse Select
block number. For instance, the $\rm Set0$ and $\rm Set1$ commands are
generated by Pulse Select Leaf Cell no. 1 and 2 out of the eight leaf cells.
$\rm Pulse0$ generates a rising and falling edge based on the 16 phases of the
Johnson counter output. This is very useful in quantum experiments where fine
timing resolution is required. The $\rm Loop$ command at Vector 17 allows the
sequence to be repeated 1000 times (2nd parameter) while the 3rd parameter (1
in this case) indicates the Vector number to start the loop from. The total
memory allocation for this script is 1088 bits (17$\crossproduct$64b) and the
quantum operation is only isolated to quantum dots $\rm QD(5,1)$ and $\rm
QD(5,2)$ in Row 5 of the qubit array (coupled to DET0) as shown in Fig. 2(b)
and (c).

Figure 7: IC Measurements. (a) Total IC leakage current over temperature. (b)
Noise at Quantum Reference Bias Circuit (QRBC) output connected to the
imposer. (c) Heat map of RF clock jitter over signal generator frequency and
power. (d) QRBC output over long time span. The output droop is negligible
over 100 $\mu$s and 5 mV over 600 $\mu$s. (e) Detector output noise measured
at 3K. Standard deviation is 17.5 mV. (f) Summary of power of the entire
control and detection circuits including the digital blocks such as the pulse
generator and the PATGEN. The total power budget is 2.5 mW per qubit.

In the next step, the benefit of the parallel bus operation of the pattern
generator is realized in Example Script 2 (Fig. 6(d) third column) where
multiple node names are added to the same Vector. The same X rotation script
now operates on four quantum dots over two rows and two detectors (DET0 and
DET3); however, the memory utilization remains unchanged. Example Script 3 is
a more area efficient rendering of the aforementioned script where the memory
utilization is down to 896 bits. Example Script 4 in the last column column in
Fig. 6(d) performs a X Rotation using a resonant driving method [21] which is
facilitated by the nested loops. The nested loop is at Vector 11 and loops two
times starting from the position of Vector 9. This useful technique results in
a memory allocation of 1024 bits, which is not too far from Example Script 3.
In summary, the key feature in this design is a memory efficient instruction
set operating on the pattern generator to create signals on the 64-bit bus
which enables highly versatile operation on a large qubit array, such as the
one presented in this work.

##  4 Measurement Results

The measurements presented in this section are divided into classical
electronic measurements and quantum experiment measurements. Fig. 7
underscores the benefits arising from the low-temperature environment that
acts as tailwind in cryogenic control circuit design. One of these is the low
leakage current as demonstrated in Fig. 7(a) where the total leakage current
of the entire IC goes down as the DUT temperature is reduced to 6 K. The low
leakage allows the capacitor to hold its charge over a long period of time as
shown in the time-domain quantum reference bias circuit (QRBC) output in Fig.
7(d). The QRBC output stabilizes in 50 $\mu$s and it remains so for nearly 100
$\mu$s during the hold phase. The long-term droop in the QRBC output is only 5
mV in 600 $\mu$s. The QRBC output driving the imposer is measured over
thousands of trials, and the output distribution is plotted in Fig. 7(b). The
standard deviation of this distribution is 110 $\mu$V which is lower than the
$\frac{kT}{q}$ limit of 267 $\mu$V at 3 K. Fig. 7(c) demonstrates the
robustness of the high-speed pulse generator, which relies on an off-chip coax
cable and frequency tuning elements [30]. The clock signal path should be low
loss over a wide bandwidth, which enhances the operating range and resolution
of the pulse generator. Low level of mismatch implies that the DUT can operate
at low output power from the signal generator, reducing the amount of active
heat dissipation. The heatmap shown in Fig. 7(c) indicates a large range of
frequencies and signal powers at the DUT input where the clock jitter is
around 1.5 ps. This performance is achieved at the highest frequency of 2.5
GHz at $-$10 dBm delivered into the DUT. Fig. 7(e) is the detector noise
measurement which is in line with the theoretical calculations detailed in
Sec. 3.4. The total power consumption of all the blocks required to operate on
one qubit is summarized in Fig. 7(f).

Figure 8: Experimental demonstration of Coulomb blockade at the SEID device on
two rows of the 2D qubit array in Fig. 2(b). (a) Graphical representation of
the condition required for quantum resonant tunneling. (b) Detector average
voltage heat map as a function of reset transistor bias $\rm V_{RD}$ and $\rm
V_{RG}$. The region of interest is highlighted as the red circle where the
detector output shows bi-modal signature. (c) The bi-model detector output on
DET3 located on 6th row in Fig. 2(b). (d) The bi-model detector output on DET0
located on 5th row in Fig. 2(b). The figure inlet shows the auto-correlation
function and the response highlights a key characteristic of quantum resonant
tunneling process [31, 32, 33]. (e) $\rm P|0\text{\small>}$ and $\rm
P|1\text{\small>}$ probability as a control function of injector step voltage
similar to the gate modulation of probability in ref. [31, 32, 33].

Fig. 8 details the quantum measurements performed on quantum dots located on
rows 5 and 6 (coupled to DET0 and DET3) respectively of the 2D qubit array in
Fig. 2(b). A sequence similar to the one shown in Fig. 6(b) is applied. The
QPC node can be initialized by first scanning voltages on the reset transistor
gate ($\rm R_{G}$) and drain ($\rm R_{D}$). The imposer connected to the
single-electron injection device (SEID) is pulsed with a set amplitude during
this scan. The detector output is stored over many iterations and the average
value is plotted as a heat map in Fig. 8(b). In this plot, the region
highlighted by the red circle is of particular interest where the detector
output shows a bi-model behavior. At this bias point, the conditions for
quantum resonant tunneling depicted in Fig. 8(a) are met. The detector output
distribution shows two distinct peaks when the barrier with potential energy
$\rm U_{B}$ is low while the Fermi energy level $\rm E_{f}$ at QPC aligns with
a discrete energy level in the adjacent quantum dot $\rm E_{N}$. The outcome
of each experiment is one of two possibilities. Either the electron tunnels to
the adjacent quantum dot resulting in a loss of charge at QPC sensed by the
detector resulting in a output voltage $\rm V_{\mu}$. The probability of this
event is $\rm P|1\text{\small>}$. In the other event, the electron does not
tunnel resulting in a detector output at 0 V. The probability of this event is
$\rm P|0\text{\small>}$. Figures 8(c) and (d) show the histograms of detectors
DET3 and DET0 respectively when the reset transistor is biased properly and
the events associated with the two states, namely $\rm|0\text{\small>}$ and
$\rm|1\text{\small>}$, are clearly visible with a separation of 300 mV between
them at the detector output. The quantum resonant tunneling process is
moderately correlated when the lag is short as shown in Fig. 5 in ref. [31].
This unique characteristic is also observed by performing auto-correlation on
the time series data of the detector samples and the result is shown in Fig.
8(d) inlet. $\rm P|1\text{\small>}$ increases with increasing step amplitude
of the SEID injector (or CDAC code) while $\rm P|0\text{\small>}$ retrogrades
as shown in Fig. 8(e). This is yet another characteristic of quantum resonant
tunneling also shown in Fig. 3 of ref. [31] and Fig. 9 of ref. [32]. The
x-axis in this chart has been translated from CDAC code a step voltage (based
on Fig.8(a) in ref. [24]). Therefore, we infer that in this state, the
electron injection process is precisely controlled by a digitally controlled
circuit parameter allowing us to manipulate the quantum information in two
quantum dots (Row 5 and 6) in the 2D qubit array.

Figure 9: Comparison with prior art.

##  5 Conclusions

We have presented a monolithic integration of a quantum resonant tunneling
gate with a quantum controller and read-out system. The entire apparatus
operates on a low power budget of 2.5 mW per qubit. This figure of merit will
improve further with on-chip digitization of detector output and reduce the
cabling to room temperature electronics down to 13 wires. The monolithic
integration is performed in “standard commercial” CMOS technology. The power
efficient architecture of cryogenic electronics is enabled by switch capacitor
implementation which is able to hold charge well over the time period required
for a quantum experiment. The measurement results demonstrate a precise
control of coulomb blockade and the electron injection process in two rows of
the 240 qubit array. The total thermal load (calculated in “Methods” section)
with current apparatus is 1.5$\%$ of the available cooling power at 3 K and
still remains well below the 1.5 W limit when the 2D qubit array is scaled to
2400 qubits.

## Methods

### Experimental Data Processing

This section details important calculations associated with Fig. 8(c,d,e). The
difference in $\rm V_{DET}$ between $\rm|0\text{\small>}$ and
$\rm|1\text{\small>}$ of 300 mV can be translated to voltage fluctuation of
3.75 mV based on a simulated gain of the detector chain of 80 V/V [24]. This
is a factor of 12x higher than $\frac{kT}{q}$ limit of 300 $\mu$V and gives us
a reasonable SNR at the detector input. However, the fluctuation of the signal
at the QPC node due to resonant tunneling process is wide-band and can’t be
processed by the detector. Consequently, there are counts appearing in the
middle zone i.e. $\rm V_{DET}$ values between -290 mV and -10 mV in Fig.
8(c,d). Those events have been removed when analyzing probabilities shown in
Fig. 8(e). The total counts for $\rm P|0\text{\small>}$ is determined by
adding events in three bins in Fig. 8(c,d): -300 mV bin and two adjacent bins.
Similar process is applied to compute total counts for $\rm P|0\text{\small>}$
around 0 mV bin. The probability is simply the ratio of the event counts and
the total sample space (10k). The probabilities are plotted for a range of
injector step voltages in Fig. 8(e).

Next, we estimate the difference in energy level $\rm\Delta E$ which is given
by $\rm\frac{e^{2}}{C_{dot}}$ where $\rm e$ is the charge of an electron. In
Fig. 8(e), $\rm P|1\text{\small>}$ fully transitions from 0$\%$ to 95$\%$ when
the step voltage of the injector is increased from 33 mV to 78 mV. This 45 mV
difference corresponds to a $\Delta V_{t}$ of 4.5 mV at the tunnel junction
due to capacitive division from $\rm C_{ox}$ and $\rm C_{t}$ (see Fig. 8(a)).
From this parameter, we calculate $\rm\Delta E$ to be 4.5 meV and $\rm
C_{dot}$ to be 35 aF. $\rm\Delta E$ is 10x above the $\rm kT$ noise of 0.27meV
at 3 K and $\rm C_{dot}$ value seems reasonable for a quantum dot of size 80
nm$\crossproduct$80 nm.

### Heat Load Calculations

Figure 10: Thermal load calculations. The calculations include active and
passive loads from cabling connected to DUT including the RF coax carrying the
chip clock. Some parameters in the table are taken from [30, 34].

.

The heat load calculations, shown in Fig. 5, include active and passive loads
due to cabling between the DUT PCB and the room-temperature electronics.
Radiative loads are neglected in this analysis. The passive loads are
calculated for 35 wires (30 from Fig. 1(a) plus five ground wires) on the flex
cable and one RF coax wire. The thermal conductivity of copper $\rm\
\rho_{f}(T)$ varies significantly from 3K to 60K [34] and therefore, the
analysis calculates the area under the curve over that temperature range to
compute the heat transfer due to the flex cable. The equation for the passive
thermal load is [4]:

$P_{p}=n_{w}\int_{3K}^{60K}dT\cdot\frac{\rho_{f}(T)\cdot
A_{f}}{L_{f}}+\rho_{c}\cdot\Delta T\ $ (1)

where $\rm A_{f}$ and $\rm L_{f}$ is the cross-section area and length of the
conductor on the flex cable respectively, and $\rm n_{w}$ is the number of
wires. The RF coax cable is the Lake Shore Cryotronics Type C cable [35] and
its thermal conductivity $\rm\rho_{c}$ is defined in different units than
$\rm\rho_{f}$. The heat transfer from the RF coax is calculated by multiplying
by the temperature difference between the cryocooler stages with $\rho_{c}$.
For active load, the square of the average supply current is multiplied by the
calculated wire resistance. The heat dissipation from the RF signal is due to
the cable loss of 2 dB [30] and the 50 $\Omega$ termination at the 3K stage.
The total thermal load is 21 mW which is 1.5$\%$ of the 1.5 W specification.
If the 2D qubit array is scaled by a factor of 10 resulting in a 2400 qubit
array, the number of detectors will scale to 160. The total thermal load
(passive and active) in this case is 150 mW which is still well below the
cryocooler specification. Moreover, on-chip digitization of the detector data
will reduce the cabling and consequently the thermal load significantly.

### Transfer Function for Noise Analysis at the Injector Output

The transfer function $\rm H_{SHPC}$ in Fig. 4(c) aliases the noise at the
switch input and the extent of aliasing is controlled by the duration of pre-
charge operation $\rm\tau_{PC}$ and the cycle rate $\rm\tau_{p}$. This
equation for $\rm H_{SHPC}$ is determined by modeling the track and hold
operation exclusively and assuming the input noise is white over a finite
bandwidth [25]. During track mode, when the sample switch is closed, the
output noise tracks the input. This time duration for this mode,
$\rm\tau_{PC}$, is normalized to the switching period:

$\tau_{PCn}=\frac{\tau_{PC}}{\tau_{p}};\\\ \tau_{SHn,PC}=1-\tau_{PCn};\\\
f_{s}=\frac{1}{\tau_{p}}$ (2)

where $\rm\tau_{SHn,PC}$ is the normalized hold period when the pre-charge
switch is open. The input noise from the VDAC is assumed to be white with
density $\rm S_{VDAC}$ over a bandwidth $\rm BW_{n}$ of 500 MHz used in this
analysis. The equation for the transfer function has the same form as Eq.6 in
ref. [25]:

$H_{SHPC}(f)=2\tau_{SHn,PC}^{2}\left(\frac{BW_{n}}{f_{s}}\right)sinc^{2}\left(\frac{\tau_{SHn,PC}f}{f_{s}}\right)+(1-\tau_{SHn,PC})$
(3)

Similarly, the transfer function $\rm H_{SHCDAC}$ models the aliasing of the
digital supply noise $\rm S_{VDD}$ to the injector output.

$H_{SHCDAC}(f)=2\tau_{SHn,clk}^{2}\left(\frac{BW_{n}}{f_{s}}\right)sinc^{2}\left(\frac{\tau_{SHn,clk}f}{f_{s}}\right)+(1-\tau_{SHn})$
(4)

where $\rm\tau_{SHn,clk}$ is the normalized hold period ($\rm\tau_{clk}$=0)
for the CDAC path in Fig. 4(c).

### Detector CDS Transfer Function

The CDS transfer function in the detector shown in Fig. 5(c) can be analyzed
from Eq. 5 in ref. [27].

$H_{CDS}(f)=4sinc^{2}(\pi
fT)\cdot\sum_{n=-\infty}^{\infty}S_{in}\left(f-n/T\right)sin^{2}\left[\pi\lambda\left(f-n/T\right)\right]$
(5)

The “sinc” term in Eq. 5 is due to the sample and hold operation similar to
ref. [25]. The summation term of the input spectrum is the aliasing fu nction.
This analysis can be simplified if the input noise spectrum is assumed to be
white over the band of interest which is 100 MHz in the numerical model. With
that assumption, the summation term in Eq. 5 can be reduced to an analytical
expression based on Eq. 3. The replacement term is 2$\frac{BW_{n}}{fs}$ which
essentially is the number of sidebands that are aliased into the bandwidth of
interest (see Eq.2 in ref. [25]). A simple approach is to structure Eq. 5 as
Eq.6 in ref. [25] and add the
$sin^{2}\left[\pi\lambda\left(f-n/T\right)\right]$ to account for the
difference in two discrete Fourier transforms. Using this approach and the
timing parameters shown in Fig. 5(c), the CDS transfer function is plotted in
Fig. 5(d).

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## Author contributions statement

All authors reviewed the manuscript.