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# Approximate Computing Survey, Part II: Application-Specific & Architectural
Approximation Techniques and Applications

Vasileios Leon  National Technical University of AthensAthens 15780Greece ,
Muhammad Abdullah Hanif  New York University Abu DhabiAbu Dhabi 129188UAE ,
Giorgos Armeniakos  National Technical University of AthensAthens 15780Greece
,  Xun Jiao  Villanova UniversityVillanova, Pennsylvania 19085USA ,  Muhammad
Shafique  New York University Abu DhabiAbu Dhabi 129188UAE ,  Kiamal Pekmestzi
National Technical University of AthensAthens 15780Greece and  Dimitrios
Soudris  National Technical University of AthensAthens 15780Greece

(2023; 18 July 2023)

###### Abstract.

The challenging deployment of compute-intensive applications from domains such
Artificial Intelligence (AI) and Digital Signal Processing (DSP), forces the
community of computing systems to explore new design approaches. _Approximate
Computing_ appears as an emerging solution, allowing to tune the quality of
results in the design of a system in order to improve the energy efficiency
and/or performance. This radical paradigm shift has attracted interest from
both academia and industry, resulting in significant research on approximation
techniques and methodologies at different design layers (from system down to
integrated circuits). Motivated by the wide appeal of Approximate Computing
over the last 10 years, we conduct a two-part survey to cover key aspects
(e.g., terminology and applications) and review the state-of-the art
approximation techniques from all layers of the traditional computing stack.
In Part II of our survey, we classify and present the technical details of
application-specific and architectural approximation techniques, which both
target the design of resource-efficient processors/accelerators & systems.
Moreover, we present a detailed analysis of the application spectrum of
Approximate Computing and discuss open challenges and future directions.

Inexact Computing, Approximation Method, Approximate Programming,
Approximation Framework, Approximate Processor, Approximate Memory,
Approximate Circuit, Approximate Arithmetic, Error Resilience, Accuracy,
Review, Classification

††copyright: acmcopyright††journalyear: 2023††journal: CSUR††doi:
10.1145/XXXXXXX.XXXXXX††ccs: General and reference Surveys and overviews††ccs:
Software and its engineering Software notations and tools††ccs: Hardware
Integrated circuits††ccs: Computer systems organization Architectures

##  1\. Introduction

The recent technological advancements in processing, storage, communication
and sensing have transformed the landscape of computing systems. With the
emergence of Internet of Things (IoT), a huge amount of data is generated,
imposing technical challenges in the resource-constrained embedded systems
that are placed at the edge of the network. The ever-growing number of global
IoT connections, which grew by 18% in 2022 and is expected to be 29.7 billion
in 2027 (IoT Analytics, 2023), is only deteriorating this situation. At the
same time, the already-stressed cloud data centers are drawing worldwide
concerns due to their enormous electricity demands. Indicatively, it is
estimated that the energy consumption of data centers in Europe was increased
by 43% from 2010 to 2020 (Bertoldi et al., 2017), while according to (Cao et
al., 2022), data centers may generate up to 8% of the global carbon emissions
in 2030.

The above issues become even more critical when considering the massive growth
of demanding applications from domains such as Digital Signal Processing
(DSP), Artificial Intelligence (AI), and Machine Learning (ML). More
specifically, the emergence of compute- and memory-intensive DSP and AI/ML
applications marks a new era for computing, where traditional design
approaches and conventional processors are unable to meet the performance
requirements (Mittal and Vetter, 2015; Georgis et al., 2019). Therefore, it is
obvious that the proliferation of data and workloads, the increase in the
complexity of applications, and the urgent need for power efficiency and fast
processing, all together, force the industry of computing systems to examine
alternative design solutions and computing schemes.

In this transition, _Approximate Computing (AxC)_ is already considered a
novel design paradigm that improves the energy efficiency and performance of
computing systems (Venkataramani et al., 2020). Over the past decade, AxC has
been established as a vigorous approach to leverage the inherent ability of
numerous applications to produce results of _acceptable_ quality, despite some
_inaccuracies_ in computations (Armeniakos et al., 2022a). The motivation
behind AxC is further analyzed in our work in (Leon et al., 2023). Driven by
its potential to address the energy and performance demands in a favorable
manner, AxC is increasingly gaining significant attention over the last years.
A representative example of this trend is depicted in Figure 1. This figure
illustrates the growing number of works that apply any kind of approximation
(e.g., software, hardware, architectural), published in four major design
automation conferences. Furthermore, AxC has attracted significant interest
from the industry. Companies such as Google (Jouppi et al., 2017), IBM
(Agrawal et al., 2021), and Samsung (Park et al., 2021) exploit the AI/ML
error resilience and design accelerators for compressed networks with reduced
precision and less computations, improving the energy efficiency and
performance in exchange for negligible or zero accuracy loss.

Considering the need to go beyond single optimizations or efficient processor
design, which solely do not suffice (Damsgaard et al., 2023), prior research
has focused on approximation techniques at different design abstraction layers
(Venkataramani et al., 2020), involving algorithmic- or compiler-level
approximations (_software_) (Akhlaghi et al., 2018; Alvarez et al., 2005),
circuit-level approximations (_hardware_) (Jiang et al., 2016; Chen and Hu,
2013) and systematic design of approximate processors (_architectural_) (Cho
et al., 2012; Esmaeilzadeh et al., 2012b). Despite their share objective of
achieving energy/area gains and latency reduction, these fundamental
techniques are orthogonal and can complement each other. As combining AxC
techniques is expected to be highly beneficial (several works report energy
gains over 90% (Damsgaard et al., 2023)), a further adoption and understanding
of cross-layer development (i.e., hardware/software co-design), including
tools & frameworks tailored to specific applications, are highly required to
maximize these benefits. In this context, motivated by the attractive
outcomes, novel methods, and future potential of AxC, we conduct a two-part
survey that covers all its key aspects.

Figure 1. Number of publications that apply any type of approximation. Four
design automation conferences over the past eight years have been considered.

##  2\. Approximate Computing Survey

Scope and Contribution: As also discussed in Part I (Leon et al., 2023) of our
survey, we examine the entire AxC computing stack, reviewing software,
hardware, and architectural approximation techniques, contrary to other AxC
surveys that focus on a single area (either design layer, technique or
application). Table 1 compares surveys studying multiple areas of AxC, like
our work. As shown, our two-part survey includes all the areas examined in the
previous works, while it reviews all of them in depth (e.g., AI/ML has not
received significant attention) and it is up-to-date.

Regarding the contribution of our survey, it provides to the readers a
complete view on AxC, while it allows them to emphasize on specific areas
(e.g., architectural techniques or application domains), as they are all
presented in detail. Furthermore, this survey can be considered as a tutorial
on the state-of-the-art approximation techniques, as we do not only classify
them, but we report in brief their technical details. Overall, the key
contributions of our two-part survey are: 1) the introduction of the AxC
paradigm by discussing its background and application domains, 2) the review
of a plethora of state-of-the-art approximation techniques, their coarse- and
fine-grained classification, and the presentation of their technical details,
3) the study of application domains where approximations are tolerated and the
analysis of representative techniques and results per domain, and 4) the
discussion of open challenges in the design of approximate systems, as they
emerge from the comprehensive literature review.

Table 1. Qualitative comparison of Approximate Computing surveys on the entire
computing stack.

AxC Survey |  Year Coverage |  Pages # |  References # |  SW Tech. |  HW Tech. |  Arch. Approx. |  AI/ML |  Memories |  | Frameworks
---
& Tools

Metrics |  Benchmarks |  | CPU/FPGA/
---
GPU/ASIC

Terminology |  Challenges
(Han and Orshansky, 2013) | 2013 | 6 | 65 | ✓ | ✓ | $\approx$ | $\approx$ | ✗ | ✗ | ✓ | ✗ | $\approx$ | ✗ | ✗
(Mittal, 2016) | 2015 |  331 | 84 | ✓ | $\approx$ | ✓ | $\approx$ | ✓ | ✓ | ✓ | ✓ | ✓ | ✗ | ✓
(Xu et al., 2016) | 2015 | 15 | 59 | ✓ | ✓ | ✓ | ✗ | $\approx$ | ✗ | ✗ | ✗ | $\approx$ | ✗ | ✗
(Venkataramani et al., 2015b) | 2015 | 6 | 54 | ✓ | ✓ | ✓ | ✗ | ✗ | ✓ | ✗ | ✗ | $\approx$ | ✗ | ✗
(Shafique et al., 2016) | 2016 | 6 | 47 | ✓ | ✓ | ✓ | ✗ | ✗ | $\approx$ | ✗ | ✗ | $\approx$ | ✗ | ✗
(Moreau et al., 2018) | 2017 | 4 | 40 | ✓ | ✓ | ✗ | $\approx$ | $\approx$ | ✗ | ✗ | ✗ | $\approx$ | ✗ | ✗
(Aponte-Moreno et al., 2018) | 2017 | 6 | 72 | ✓ | ✓ | ✓ | $\approx$ | $\approx$ | $\approx$ | ✗ | ✓ | $\approx$ | ✗ | ✓
(Stanley-Marbell et al., 2020) | 2020 |  391 | 235 | $\approx$ | ✓ | ✓ | ✗ | ✓ | $\approx$ | ✗ | ✗ | $\approx$ | ✗ | ✓
Our work | Pt. 1 | 2023 |  341 | 221 | ✓ | ✓ |  |  |  | ✓ |  |  | ✓ | ✓ |
Pt. 2 | 2023 |  351 | 296 | ✓ | ✓ | ✓ | ✓ | ✓ |  | ✓ | ✓ | ✓ |  | ✓

  * 1

Single-column pages

Organization: Figure 2 presents the content of each part of our survey:

Part I::

It is presented in (Leon et al., 2023), and it introduces the AxC paradigm
(terminology and principles) and reviews software & hardware approximation
techniques.

Part II::

It is presented in the current paper, and it reviews application-specific &
architectural approximation techniques and introduces the AxC applications
(domains, quality metrics, benchmarks).

The remainder of the article (Part II of survey) is organized as follows.
Section 3 reports software-, hardware- and cross-layer application-specific
approximation techniques. Section 4 focuses on the architecture level and
classifies approximate processors and storage. Section 5 studies the
applications of AxC, while Section 6 discusses challenges and future
directions. Finally, Section 7 draws the conclusions.

Figure 2. Organization of our two-part survey on Approximate Computing.

##  3\. Application-Specific Approximation Techniques

In this section, we classify and introduce application-specific approximation
techniques. We mainly discuss techniques that are proposed for improving the
performance and efficiency of Deep Learning (DL) and AI applications. The
techniques presented in the literature can be broadly categorized into
software-level, hardware-level and cross-layer approximation techniques (see
Figure 3 and Table 2).

Figure 3. Classification of application-specific approximation techniques for DL and AI applications in three main classes: _Software-Level_ , _Hardware-Level_ , and _Cross-Layer & End-to-End_. Table 2. Classification of application-specific approximation techniques. | Application-Specific
---
Approximation Class
Technique/Approach
Software-Level Approximation |  Computation Skipping / Pruning (Han et al., 2015b, a; Yu et al., 2017; Li et al., 2016; Yvinec et al., 2021, 2022; He et al., 2017; Hu et al., 2016; Tan and Motani, 2020; Sui et al., 2021; He et al., 2022; Lebedev and Lempitsky, 2016; Wen et al., 2016; Wang et al., 2020b; Chen et al., 2021)
Precision Scaling (Rastegari et al., 2016; Hubara et al., 2016; Zhou et al.,
2016; Jain et al., 2019; Han et al., 2015a; Wang et al., 2019)
Input-Adaptive Approximation (Ganapathy et al., 2020; Panda et al., 2017a, b;
Tann et al., 2016; Venkataramani et al., 2015a, c; Lou et al., 2021; Plastiras
et al., 2018)
Input Scaling (Tan and Le, 2019; Ghosh et al., 2020)
Hardware-Level Approximation |  Functional Approximation & Approx. Datapaths (Venkataramani et al., 2014; Mrazek et al., 2016, 2019, 2020; Sonnino et al., 2023; Spantidi et al., 2021; Saadat et al., 2018; Kim et al., 2018a; Hanif et al., 2019; Leon et al., 2022; Lentaris et al., 2020)
Approximation-based Novel Data Representation Formats (Jain et al., 2019,
2018; Hanif et al., 2022; Guo et al., 2022)
Voltage Scaling (Zhang et al., 2018; Shin et al., 2019; Ji et al., 2020;
Pandey et al., 2019; Kim et al., 2018b; Koppula et al., 2019)
Data Approximation (Koppula et al., 2019; Kim et al., 2018b)
Cross-Layer & End-to-End Approximation |  Approximation at Various Layers of Computing Stack (Armeniakos et al., 2023a, b; Raha and Raghunathan, 2017, 2018; Ghosh et al., 2020; Hashemi et al., 2018b; Gong et al., 2019; Hanif and Shafique, 2022; Fan et al., 2019; Venkataramani et al., 2020)
Full-System Perspective (Raha and Raghunathan, 2017, 2018; Ghosh et al., 2020;
Hashemi et al., 2018b)
Approximation of Multiple Subsystems in a Synergistic Manner (Raha and
Raghunathan, 2017, 2018; Ghosh et al., 2020; Hashemi et al., 2018b)

###  3.1. Software-Level Approximations

Various types of software-level approximation techniques have been proposed in
the literature to reduce the computational complexity and memory footprint of
AI and DL workloads. These techniques can broadly be divided into four groups:
(i) _computation skipping / pruning_ (Han et al., 2015b, a; Yu et al., 2017;
Li et al., 2016; Yvinec et al., 2021, 2022; He et al., 2017; Hu et al., 2016;
Tan and Motani, 2020; Sui et al., 2021; He et al., 2022; Lebedev and
Lempitsky, 2016; Wen et al., 2016; Wang et al., 2020b; Chen et al., 2021),
(ii) _precision scaling_ (Rastegari et al., 2016; Hubara et al., 2016; Zhou et
al., 2016; Jain et al., 2019; Han et al., 2015a; Wang et al., 2019), (iii)
_input-adaptive approximation_ (Ganapathy et al., 2020; Panda et al., 2017a,
b; Tann et al., 2016; Venkataramani et al., 2015a, c; Lou et al., 2021; Kyrkou
et al., 2018; Plastiras et al., 2018), and (iv) _input scaling_ (Tan and Le,
2019; Ghosh et al., 2020).

####  3.1.1. Pruning

Computation skipping is one of the most effective software-level techniques
for approximating DNNs. Various techniques have been proposed under the
umbrella of DNN pruning that exploits computation skipping for optimizing the
DNN inference process. In general, DNN pruning refers to the process of
removing non-essential (or less important) weights from a DNN to reduce its
computational complexity, memory footprint as well as energy consumption
during the inference process. These techniques are generally divided into two
main categories: (1) unstructured pruning and (2) structured pruning.

Unstructured pruning (a.k.a. fine-grained pruning) refers to techniques that
analyze the importance/saliency of each individual weight and remove it if its
importance is below a predefined threshold. These techniques are usually
designed to be iterative, where in each iteration only a small percentage of
less significant weights are removed and then the network is retrained for a
few epochs to regain close to the baseline accuracy. For example, Han et al.
(Han et al., 2015b) propose a three-step method to prune DNNs. First, they
train a DNN to learn the importance of connections. Then, they remove non-
essential (less important) connections from the DNN. Finally, they fine-tune
the remaining weights to regain the lost accuracy. The authors further propose
that learning the right connections is an iterative process. Therefore, the
process of pruning followed by fine tuning should be repeated multiple times
(with a small pruning ratio) to achieve higher compression ratios. Deep
Compression (Han et al., 2015a) combines a similar method with weight sharing
and Huffman coding to achieve ultra-high compression ratios.

Although unstructured pruning significantly reduces the number of parameters
and the memory footprint of DNNs, it does not guarantee energy or latency
benefits in all cases. This is mainly because; (1) the weights of a pruned
network are usually stored in a compressed format, such as the Compressed
Sparse Row (CSR) format, to achieve high compression ratios and, therefore,
have to be uncompressed before corresponding computations, which results in
significant overheads, and (2) the underlying hardware (in most use cases) is
not designed to take advantage of unstructured sparsity in DNNs, which results
in under utilization of the hardware. Therefore, specialized hardware
accelerators, such as EIE (Han et al., 2016) and SCNN (Parashar et al., 2017),
are required to efficiently process data using unstructured sparse DNNs.
Similarly, Yu et al. (Yu et al., 2017) highlight that it is essential to align
the pruning method to the underlying hardware architecture to achieve
efficiency gains. A mismatch between the type of sparsity in the network and
the sparsity the hardware can support efficiently usually leads to significant
overheads. Based on this observation, the authors propose two novel pruning
methods, i.e., SIMD-aware weight pruning and node pruning. SIMD-aware weight
pruning maintains weights in aligned fixed-size groups to fully utilize the
available SIMD units in the underlying hardware, while node pruning removes
less significant nodes from the network without affecting the dense format of
weight matrices.

Various other techniques have also been proposed in the literature to achieve
structured sparsity in DNNs. These methods generally include weight-dependent
pruning techniques (Li et al., 2016; Yvinec et al., 2021, 2022), activation-
based techniques (He et al., 2017; Hu et al., 2016; Tan and Motani, 2020; Sui
et al., 2021; He et al., 2022), and regularization-based techniques (Lebedev
and Lempitsky, 2016; Wen et al., 2016; Wang et al., 2020b; Chen et al., 2021).
The weight-dependent techniques evaluate the importance of filters solely
based on the weights of the filters, while activation-based techniques use
activation maps to identify critical filters in the network. Similarly,
regularization-based techniques encourage sparsity during training by adding
regularization terms in the loss function or by exploiting batch normalization
parameters.

####  3.1.2. Precision Scaling

It refers to the techniques of mapping values from a high-precision range to a
lower-precision range with lesser number of quantization levels. The number of
quantization levels in a range defines the number of bits required to
represent each data value. Hence, by using a lower-precision format, such as
4-bit or 8-bit fixed-point or floating-point format instead of the standard
32-bit floating-point format, the memory footprint as well as the
computational requirements of DNNs can be significantly reduced.

Various techniques have been proposed to achieve precision scaling of DNNs
without affecting their application-level accuracy. The most commonly used
technique is 8-bit range linear post-training quantization, where floating-
point weights and activations are converted to 8-bit fixed-point format. The
range linear quantization is further divided into two types: (1) asymmetric
quantization (Jacob et al., 2018) and (2) symmetric quantization
(Krishnamoorthi, 2018). In asymmetric quantization, the minimum and maximum
observed values in the input range are mapped to the minimum and maximum
values in the output (integer/fixed-point) range, respectively. However, in
symmetric quantization, the maximum absolute observed value in the input range
is used to define both minimum and maximum values of the input range.
Significant efforts have been made to push the limits of DNN precision scaling
to ultra-low precision levels. Works like XNOR-Net (Rastegari et al., 2016),
Binarized Neural Network (BNN) (Hubara et al., 2016) and DoReFa-Net (Zhou et
al., 2016) explore the potential of aggressive quantization, up to 1-bit
precision. However, as aggressive quantization leads to significant accuracy
loss, these techniques usually employ quantization-aware training to achieve
reasonable accuracy, as in such cases training also acts as an error-healing
process.

Non-linear (or non-uniform) quantization techniques have also been explored in
the literature (Jain et al., 2019; Han et al., 2015a). These techniques are
inspired by the non-uniform probability distribution of DNN data structures
and propose to distribute the quantization levels accordingly. Apart from the
above-mentioned techniques, mixed-precision techniques are also commonly used,
where different precision formats can be used for different layers and
filters/channels of a DNN (Wang et al., 2019). We note that mixed-precision
quantization is only effective when the underlying hardware is capable of
supporting different precision formats.

####  3.1.3. Input-Adaptive Approximation

Besides pruning and precision scaling, input-adaptive approximations are also
commonly used to approximate DNN workloads. In general, input-adaptive
approximations refer to the techniques that dynamically adapt the level of
approximation based on the characteristics of the input data. Various methods
have been proposed in the literature to realize input-adaptive approximations.
These methods mainly include (1) early-exit classifiers, (2) dynamic network
architectures, and (3) selective attention mechanisms. Works such as (Panda et
al., 2017a; Venkataramani et al., 2015c) that fall under early-exit
classifiers argue that most of the inputs can be classified with very low
effort. Towards this, the authors in (Panda et al., 2017a) propose Conditional
Deep Learning (CDL), where the outputs of convolutional layers are used to
estimate the difficulty of input samples (with the help of linear classifiers)
and conditionally activate the deeper layers of the DNN. Similarly, (Panda et
al., 2017b) propose a hierarchical classification framework by exploiting
semantic decomposition. Towards dynamic network architectures, (Ganapathy et
al., 2020) presents an approach that adapts the structure of a DNN based on
the difficulty of the input sample. Along similar lines, (Tann et al., 2016)
presents a method for building runtime configurable DNNs and a score margin-
based mechanism for dynamically adjusting the DNN capability. Unlike the above
techniques that involve network structure or size modification, selective
attention mechanisms focus on reducing computational requirements by
processing only the important/relevant regions of the input while ignoring all
less relevant parts. A prominent work in this direction includes selective
tile processing (Plastiras et al., 2018), where a low cost attention mechanism
is used to identify the tiles that require processing.

####  3.1.4. Input Scaling

Given that neighboring pixels in images are not always statistically
independent and contain a significant amount of redundant information, input
scaling can be exploited to reduce the computational requirements of DNN
inference. Towards this, Tan et al. in (Tan and Le, 2019) propose a compound
scaling method that uniformly scales network width, depth, and input
resolution to design a complete class of EfficientNets. Moreover, techniques
like AxIS (Ghosh et al., 2020) employ input scaling as an approximation knob
in their cross-layer approximations to achieve ultra-high efficiency gains.

###  3.2. Hardware-Level Approximations

Venkataramani et al. in (Venkataramani et al., 2014) highlight that DNNs are
mostly used for error-resilient applications, and hence, hardware
approximations can be used to effectively trade quality for efficiency of the
DNN inference process. Towards this, they propose a method to transform a
given Neural Network (NN) to an Approximate Neural Network (AxNN)
(Venkataramani et al., 2014). The method mainly employs backpropagation to
estimate the importance of each neuron and then selectively approximates less
significant neurons through precision scaling of weights and activations to
achieve better energy-accuracy trade-offs. The method also employs
approximation-aware retraining to regain a significant portion of the accuracy
lost due to approximations.

As a single DNN inference can take from some million to billions of MAC
operations, the use of approximate MAC units in DNN accelerators (instead of
accurate ones) can have a significant impact on the overall energy consumption
of DNN inference systems. In general, approximate MAC units refer to the
simplified variants of the accurate counterparts that offer approximately the
same functionality but at a lower energy or performance cost. Various
significant efforts have been made toward designing approximate MAC units.
Most of these works focus on approximating the multiplication part in the MAC
operations, as multipliers are in general more complex and resource hungry
than adders. Marazek et al. in (Mrazek et al., 2016) employ the Cartesian
Genetic Programming (CGP) approach to approximate accurate multiplier designs.
The methodology employs approximation-aware retraining of the given NN in the
methodology to reach the best possible approximate multiplier design for the
given application. However, approximation-aware retraining is not possible in
all scenarios, e.g., due to limited computational resources or due to the lack
of availability of training data. Therefore, to address this limitation,
ALWANN (Mrazek et al., 2019) proposes a layer-wise approximation technique to
select an appropriate approximate multiplier from a given library (e.g.,
EvoApprox (Mrazek et al., 2017)) for each individual layer of the given DNN
without involving any training. The authors also present a computationally
inexpensive method to fine-tune the DNN weights after the approximate module
selection process to reduce the accuracy loss due to approximations. In the
same context, the Max-DNN framework (Leon et al., 2022) relies on ALWANN’s
functionalities to provide fine-grained approximation of the multiplications
at different DNN layers. In (Mrazek et al., 2020), the authors present a
methodology to generate libraries of more specific approximate circuits and
show that such techniques can produce better results than techniques like
ALWANN (Mrazek et al., 2019). Other prominent approximate multiplier designs
for DNN acceleration include Digital Approximate In-SRAM Multiplier (DAISM)
(Sonnino et al., 2023), positive/negative approximate multipliers (Spantidi et
al., 2021) and approximate log-multipliers (Saadat et al., 2018; Kim et al.,
2018a). Moreover, towards mitigating the impact of approximation errors, CANN
(Hanif et al., 2019) presents the concept of curable approximations for DNN
accelerators, where approximation errors can be internally compensated with
some additional functionality. To facilitate the design and exploration of
approximate modules for efficient DNN inference, fast simulation techniques
and frameworks are also being developed and studied (Gong et al., 2023; De la
Parra et al., 2020; Taheri et al., 2023). Finally, the use of approximate
multipliers provides resource saving and increased throughput in FPGA-based
DNN accelerators (Lentaris et al., 2020), while the same benefits are also
delivered in classic DSP kernels (Leon et al., 2021b).

Another set of techniques that include works such as BiScaled-DNNs (Jain et
al., 2019), CoNLoCNN (Hanif et al., 2022), Compensated-DNNs (Jain et al.,
2018) and ANT (Guo et al., 2022) targets novel data representation formats to
significantly reduce the hardware complexity and energy requirements of DNN
inference systems. BiScaled-DNNs (Jain et al., 2019) argues that DNN data
structures are long-tailed and, therefore, can effectively be quantized using
two different scale factors (namely, scale-fine and scale-wide). Scale-fine
enables the system to precisely capture small numbers using more fractional
bits, while scale-wide allows the system to cover the entire range of large
numbers but at a coarser granularity. CoNLoCNN (Hanif et al., 2022) employs a
modified version of power-of-two quantization to replace multiplication with
shift operations. Compensated-DNNs (Jain et al., 2018) propose the concept of
dynamic compensation to mitigate the impact of quantization errors caused due
to aggressive quantization. On the other hand, ANT (Guo et al., 2022) argues
that most of the existing quantization techniques use fixed-point or floating-
point data representation formats, which offer limited benefits, as both are
effective for specific data distributions, and thus, require reasonably large
number of bits to maintain the DNN accuracy. Therefore, (Guo et al., 2022)
proposes a novel adaptive numerical data type that combines the benefits of
float and integer data formats and, thereby, it allows the system to adapt
based on the importance of each value in a tensor.

Apart from functional approximation of arithmetic modules in DNN accelerators,
voltage-scaling can also be employed to improve the energy efficiency of DNNs.
ThunderVolt (Zhang et al., 2018) presents TE-Drop, a timing error recovery
technique for DNN accelerators. It employs Razor flip-flops to detect timing
errors in the MAC units and then avoids re-execution penalty by dropping the
MAC operation subsequent to the erroneous MAC. (Shin et al., 2019) presents a
similar approach but employs Razor flip-flops in between the multiplier and
the adder of each MAC unit. As dropping MAC operations can result in
significant performance degradation, the authors in (Ji et al., 2020) present
a Compensation MAC (CMAC) unit that compensates for the dropped multiplication
using an additional adder in the MAC subsequent to the erroneous MAC. Along
similar lines, GreenTPU (Pandey et al., 2019) presents a Timing Error Control
Unit (TECU) to keep track of the timing error causing input patterns and boost
the operating voltage of the subsequent MACs in the processing array. Apart
from exploiting voltage scaling for improving energy efficiency of
computational units, works such as MATIC (Kim et al., 2018b) explore the
potential of aggressive voltage scaling of on-chip weight memories to improve
the energy efficiency of DNN accelerators. Similarly, EDEN (Koppula et al.,
2019) presents a framework for using approximate DRAM with reduced voltage and
reduced latency to improve the energy and performance efficiency of DNN
inference systems. These techniques mainly employ memory adaptive training to
achieve ultra-high efficiency gains and without any significant loss in the
DNN accuracy.

###  3.3. Cross-Layer and End-to-End Approximations

The adoption of approximations in real-world systems has been mostly limited
to either the software or hardware level and to only one subsystem (usually
the computational one). To uncover the true potential of Approximate
Computing, a full-system approach is essential where approximations are
applied at multiple abstraction levels and to multiple subsystems (e.g., the
memory, sensor, and communication subsystems) together with the computational
subsystem. Various studies have shown the potential of systematic joint
approximation of subsystems to achieve ultra-high efficiency gains. Earlier
works highlight the potential of combining software- and hardware-level
approximations. For example, in (Panda et al., 2016), the authors highlight
different algorithmic and circuit-level approximation techniques for
significantly reducing the energy consumption of DNN inference systems. For
algorithmic approximations, they mainly discuss scalable effort computing
techniques (Venkataramani et al., 2015c; Panda et al., 2017a), in which less
complex inputs are processed using smaller networks, and more complex inputs
are passed through a larger number of processing layers to generate an
accurate output. For circuit/hardware-level approximations, they mainly
highlight voltage scaling of on-chip SRAM and functional approximation of
multipliers to reduce the energy consumption of DNNs.

In (Raha and Raghunathan, 2017), Raha et al. present a full-system perspective
for approximating smart camera systems designed for computer vision and image
processing applications. They present a systematic methodology for judiciously
approximating sensor, memory, and computation subsystems. For sensor
approximation, they consider pixel subsampling (or downscaling image
resolution), as it not only reduces the energy consumption of the sensor but
also reduces the entire system’s energy consumption by reducing the input size
(or data) and the number of computations required for processing the input.
For approximating memory, they focus on increasing the refresh interval of
DRAM, as sub-optimal refresh intervals result in a significant reduction in
refresh energy consumption while still offering space to store critical data
in non-erroneous DRAM pages. For computation approximation, they consider loop
perforation and early loop termination techniques. To systematically tune all
the subsystem approximation knobs, they first find the optimal image
resolution for the given quality constraint and then using gradient descent
over the individual quality vs. energy curves find the optimal operating
points for DRAM and computation skipping. In (Raha and Raghunathan, 2018), the
methodology is extended to cover the communication subsystem as well. The work
shows that for compute-intensive systems the methodology offers
3.5$\times$–5.5$\times$ energy benefits, while for communication-intensive
systems, e.g., where the input is sent to a server for processing, the
methodology offers 1.8$\times$–3.7$\times$ energy benefits at the cost of less
than 1% application-level quality loss. In (Ghosh et al., 2020), Ghosh et al.
design a similar methodology for DNN-based inference system and demonstrate
that their methodology can lead to 1.6$\times$–1.7$\times$ energy benefits for
the on-device inference scenario and 1.4$\times$–3.4$\times$ energy benefits
for the on-cloud inference scenario at the cost of less than 1% accuracy loss.

A similar end-to-end approach is presented in (Hashemi et al., 2018b) for
approximating an iris scanning system. The authors employ approximations both
at the software and hardware levels to build an accurate system using
approximate pipeline. They identify eight different approximation knobs and
then employ a reinforcement learning-based methodology for design space
exploration on the approximate pipeline to achieve optimal trade-off between
accuracy and runtime/energy consumption. Their method can lead to 48$\times$
improvement in runtime while maintaining 100% accuracy.

Apart from the above methods, various other techniques have also been proposed
that combine DNN compression/approximation algorithms with hardware-level
approximations to achieve significant efficiency gains. Gong et al. (Gong et
al., 2019) present a framework that combines dynamic layered CNN structure,
kernel shrinking and layer-by-layer quantization at the algorithm level and
uses an approximate computing-based reconfigurable architecture at the
hardware level. Similarly, (Hanif and Shafique, 2022) presents a cross-layer
framework that combines network pruning and quantization with hardware-level
functional approximations of arithmetic units. Along similar lines, (Fan et
al., 2019) integrates activation pruning and voltage scaling with hardware-
level functional approximation. To overcome the accuracy loss incurred due to
hardware approximations, the authors propose to incorporate approximations in
the training process, which results in an increase of about 5.32% in accuracy.
The authors report around 52.5% improvement in the energy efficiency of the
system on average.

As the spectrum of AI-based products and services is expanding at a rapid
pace, there is an increased demand for computing systems that can efficiently
handle various types of DNN workloads. Towards this, (Venkataramani et al.,
2020) presents an AI system design, RaPID, that integrates different
approximation techniques developed at different layers of the computing stack.
At the algorithm level, it employs precision scaling and gradient compression
to reduce the compute, memory, and data-transfer costs. At the hardware level,
it employs a reconfigurable approximate AI core that supports different levels
of approximations. Finally, it incorporates an approximation-aware compiler to
map approximate algorithms on approximate hardware. The system is designed to
support various types of DNNs and both DNN inference and training workloads.

Of particular relevance, the need for further hardware efficiency across
multiple abstraction levels also exists in resource-limited scenarios, suited
to low-power ML, such as flexible and printed applications (Mubarik et al.,
2020; Armeniakos et al., 2022b). Printed classifiers are significantly less
costly than conventional CMOS technologies, paving the way for high circuit
customizations, also known as Bespoke implementations (Cherupalli et al.,
2017). Recent examples introduced Approximate Computing in printed ML
classifiers tailored to Bespoke architectures (Armeniakos et al., 2023a, b).
(Armeniakos et al., 2023b) proposes an automated framework that applies a
model-to-circuit cross approximation and generates close-to-accuracy-optimal
approximate ML circuits, allowing the deployment of complex classifiers on
battery-powered devices ($<30$mW). On the other hand, through a hardware-
friendly retraining (at algorithmic level), (Armeniakos et al., 2023a)
replaces coefficients with more area-efficient ones, while an approximate
neuron (at hardware-level) boosts the area/power efficiency by discarding the
least significant information among the least significant summands.

##  4\. Architectural Approximation Techniques

Architectures that offer the flexibility to willingly trade-off among resource
usage, storage and correctness in processor designs have the potential to
achieve both higher performance and improved energy efficiency compared to
error-free baselines. This section elaborates how these gains can be
accomplished through the adoption of _approximate processors_ and _approximate
data storage_ , where certain computational and/or storage tasks can be loaded
to specialized/approximate computing units, resulting in faster processing at
the expense of reduced accuracy (Amant et al., 2014; Mahajan et al., 2016;
Esmaeilzadeh et al., 2012b; Yazdanbakhsh et al., 2015b; Moreau et al., 2015).
Such approximations are typically implemented at a higher level of abstraction
and involve reorganizing the system’s functional blocks or optimizing the use
of memory, rather than making modifications to the system’s physical
components (like in hardware approximation techniques).

###  4.1. Approximate Processors

Early research in the design of approximate processors includes a complete
system and toolchain, proposed in (Amant et al., 2014). The design spans from
circuits to a compiler, which integrates an area- and energy-efficient analog
neural accelerator tailored to approximate general-purpose code. This solution
includes a compiler workflow that configures both the topology and weights of
the neural network, while a customized training algorithm reduces errors
derived from analog range limitations. In a similar approach (Esmaeilzadeh et
al., 2012b), digital Neural Processing Units (NPUs) are tightly integrated
with the processor pipeline, resulting in low-power approximations for
specific sections of general-purpose code. Finally, approximate neural network
processing along with high data-level parallelism has been explored for GPUs
(Yazdanbakhsh et al., 2015b) and FPGAs (Moreau et al., 2015), as well.

Relax (de Kruijf et al., 2010) is an architectural framework that comprises
three key components - ISA extension, hardware support and software support.
The ISA extension allows the registration of a fault handler for a code
region, enabling software applications to incorporate try/catch behavior. The
hardware support for Relax simplifies hardware design and enhances energy
efficiency by relaxing reliability constraints and providing fault detection
mechanisms, while the software support offers a language-level recovery
construct in C/C++, with relax blocks marking regions susceptible to hardware
faults. Similarly, ERSA (Cho et al., 2012) is a system architecture that
targets applications with inherent error resilience, and ensures high degrees
of resilience at low cost. It achieves high error resilience to high-order bit
errors and control flow errors using asymmetric reliability (and the concept
of “configurable reliability” for general-purpose applications) in many-core
architectures, error-resilient algorithms, and intelligent software
optimizations.

Prior research studies on the design of approximate processors also include
the voltage over-scaling paradigm as a potential energy-saving method with
adjustable approximation level (Afzali-Kusha and Pedram, 2023). The authors in
(Esmaeilzadeh et al., 2012a) propose an ISA extension provided with
approximate operations and storage, as well as a microarchitecture design,
called Truffle, which effectively supports these extensions. This work
utilizes dual-voltage operation to save power and allows the programmers to
specify which parts of a program can be computed approximately at a lower
energy cost. Similar manipulations in operational (timing) errors to decrease
power consumption of processor architectures from voltage/reliability trade-
offs, have been studied and can be found in (Sartori and Kumar, 2011; Kahng et
al., 2010).

Among previous architectures, RISC-V has been established as an increasingly
growing competitor and alternative of CPUs with funded projects and support
from star companies (e.g., Intel, Microsoft, ST Microelectronics (Source,
2023)). The availability of open-source RISC-V tools and libraries provides
developers with greater flexibility in designing and optimizing approximate
computing systems. More specifically, the authors in (Ndour et al., 2019)
extend prior works in variable bit-width approximate arithmetic operators with
configurable data memory units as well, while (Kim et al., 2021) leverages the
inherent “value similarity” characteristic of ML workloads and by using
lightweight micro-architectural ISA extensions skips entire instruction
sequences. Accordingly, it substitutes the results with previously executed
computations, improving both performance and energy efficiency. Furthermore,
(Felzmann et al., 2020) utilizes multiple hardware-level approximations and
minimizes quality degradation of several applications by adopting a hardware
controller, which adjusts the degree of approximation by selecting various
approximate units. Lastly, RISC-V processors targeting DNN applications have
also been explored in (Ottavi et al., 2020; Cococcioni et al., 2022). In
(Ottavi et al., 2020), the authors exploit the efficacy of SIMD instructions
and propose mixed-precision Quantized Neural Network (QNN) execution that
enables functional units down to 2 bits, opposed to commercial cores (e.g.,
ARM Cortex M55) that cannot natively support smaller than 8-bit SIMD
instructions. On the other hand, (Cococcioni et al., 2022) extends the base
RISC-V ISA to enable low bit-width operations tailored to DNN tasks, but this
time by adopting a posit processing unit that can be integrated in a full
RISC-V core with minimal overheads.

###  4.2. Approximate Data Storage

In this survey, we consider the two main types of memories: the non-volatile
and the volatile memories. In our review, the works on approximate non-
volatile data storage target Phase-Change Memories (PCMs) (Sampson et al.,
2014; Fang et al., 2012; Teimoori et al., 2018), flash memories (Salajegheh et
al., 2011; Tseng et al., 2013; Liu et al., 2012), and Spin Transfer Torque
(SST) RAMs (Sampaio et al., 2015; Ranjan et al., 2015; Zeinali et al., 2018;
Teimoori et al., 2018). Regarding the volatile memories, we review static RAMs
(SRAMs) (Kumar et al., 2009; Chang et al., 2011; Frustaci et al., 2016;
Reviriego et al., 2022), dynamic RAMs (DRAMs) (Reviriego et al., 2022; Liu et
al., 2011; Jung et al., 2015), and caches (Miguel et al., 2015, 2016; Li et
al., 2019). We note that the literature also includes approximation techniques
that are applied and evaluated in different types of memory (Ranjan et al.,
2020).

####  4.2.1. Approximate Non-Volatile Memories

Sampson et al. (Sampson et al., 2014) introduce two mechanisms to approximate
PCMs, which can be used for persistent storage (e.g., for databases or
filesystems) or as main memory. The first mechanism reduces the number of
programming pulses for writing the multi-level cells (i.e., cells storing
multiple bits of information), while the second one stores approximate data in
blocks with exhausted error correction resources. SoftPCM (Fang et al., 2012)
integrates a method to reduce the write traffic towards improved energy
efficiency and lifetime. More specifically, a circuit compares the new data
with stored data, and the writing operation is not performed if the difference
is below a threshold.

The authors of (Salajegheh et al., 2011) provide approximate storage in
embedded flash memories by lowering the voltage below its nominal value. To
deal with unpredictable behaviors and large error rates, they employ three
software-based methods, i.e., “in-place writes”, “multiple-place writes”, and
“RS-Berger codes”. The first method repeatedly writes the data to the same
memory address, while the second one writes the data in more than one
addresses. The last method is an error detection & correction code that
recovers the originally stored data. In the same context, Tseng et al. (Tseng
et al., 2013) characterize various multi-level cell flash memories when the
supply voltage drops during read, program and erase operations. Based on the
characterization results, they propose a dynamic scaling mechanism that
adjusts the voltage supply of flash according to the executed operation.
Retention relaxation (Liu et al., 2012) is another interesting technique
applied in multi-level cell flash memories. In particular, the write operation
for data with short lifetime (e.g., data from proxy and MapReduce workloads)
is accelerated based on modeling the relationship between raw bit error rates
and retention time.

The literature also includes works on approximate SST RAMs, which are non-
volatile alternative of SRAMs for on-chip scratchpad or cache memory. Sampaio
et al. (Sampaio et al., 2015) propose an approximate STT-RAM cache
architecture that reduces the reliability overhead under a given error bound.
The application’s critical data are protected using a latency-aware double
error correction module, while approximation-aware read and write policies
provide approximate storage. Moreover, the architecture is equipped with a
unit for monitoring the quality of the application’s output. To provide an
approximate scratchpad memory, Ranjan et al. (Ranjan et al., 2015) design a
quality configurable SST-RAM, in which read and write operations are executed
at varying accuracy levels. Approximate reads are performed by either lowering
the current used to sense the stored value or lowering the sensing duration
and increasing the current. Similarly, approximate writes are performed by
lowering the current and/or sensing duration. Furthermore, the authors of
(Zeinali et al., 2018) propose a scheme for progressively scaling the cells of
STT-RAM arrays based on a scaling factor. In this approach, the most
significant bits of the data words are implemented to provide lower bit error
rates from the least-significant ones. In (Teimoori et al., 2018), the authors
propose AdAM, which provides adaptive approximation management across the
entire non-volatile memory hierarchy. In more detail, they model a system with
STT-RAM scratchpad and PCM main memory and apply various approximation knobs
(e.g., read/write pulse magnitude/duration) to exchange data accuracy for
improved STT-RAM access delay and PCM lifetime.

####  4.2.2. Approximate Volatile Memories

Regarding SRAM memories, significant research efforts have focused on lowering
the supply voltage. In this context, Kumar et al. (Kumar et al., 2009) apply
system-level design techniques to reduce the SRAM leakage power. Their
framework is constrained by a data-reliability factor, while they use a
statistical/probabilistic setup to model soft errors and process variations.
In (Chang et al., 2011), the authors propose a hybrid memory array for video
processors. Their policy is to store the high-order bits of luminance pixels,
i.e., those that are more sensitive to human vision, in robust 8T SRAM bit-
cells, while the low-order bits are stored in 6T bit-cells. This approach
allows to lower the supply voltage without significantly affecting the high-
order bits. Frustaci et al. (Frustaci et al., 2016) evaluate a wide range of
approximation techniques (bit dropping, selective write assist, selective
error correcting code, voltage scaling) for dynamic management of the
energy–quality trade-off in SRAMs. Their analysis is based on measurements on
a 28-nm SRAM testchip, and it also includes combinations of the examined
techniques and different array/word sizes.

The authors of (Reviriego et al., 2022) use approximate SRAM and DRAM memories
to implement sketches for similarity estimation. In more detail, based on
theoretical analysis and simulation, they examine the error rates in
unprotected and parity-protected memories and tune their voltage supply.
Moreover, the work in (Liu et al., 2011) applies lower refresh rates in the
DRAM portions storing the non-critical data. Similarly, Jung et al. (Jung et
al., 2015) define reliable and unreliable memory regions, however, in their
strategy they completely disable the DRAM’s auto-refresh feature.

Besides SRAMs and DRAMs, the literature also includes research works on
approximate caches. In (Miguel et al., 2015), the authors propose the
Doppelganger cache based on the approximate similarity among the cache values.
In particular, they associate the tags of multiple similar blocks with a
single data array entry, and hence, they reduce the cache memory footprint. In
the same context, the authors of (Miguel et al., 2016) propose the Bunker
cache based on the spatio-value similarity, where approximately similar data
exhibit spatial regularity in memory. Their approach is to map similar data to
the same cache location with respect only to their memory address. Finally,
ASCache (Li et al., 2019) is an approximate SSD cache that allows bit errors
within a tolerable threshold, while avoiding unnecessary cache misses and
guaranteeing end-to-end data integrity.

##  5\. Application Domains of Approximate Computing

In this section, we introduce the error-tolerant application domains that have
been systematically examined for Approximate Computing. At first, we classify
per domain the works presented in Part I (Leon et al., 2023) and Part II of
our survey (Table 3), and discuss approximation opportunities and
representative techniques for each domain. Next, we analyze the case studies
of each domain, and we report benchmark suites and error / Quality-of-Service
(QoS) metrics that are widely used.

###  5.1. The Application Spectrum of Approximate Computing

Table 3. Classification of state-of-the-art Approximate Computing works per application domain. Application Domain |  References
---|---
Image Processing |  (Adams et al., 2020; Akbari et al., 2017, 2018; Alvarez et al., 2005; Boston et al., 2015; Castro-Godínez et al., 2020; Chen et al., 2015, 2016, 2018; Ebrahimi-Azandaryani et al., 2020; Esposito et al., 2018; Frustaci et al., 2020; Gupta et al., 2013; Hashemi et al., 2015, 2016; Hoffmann et al., 2009; Imani et al., 2019; Jiang et al., 2019; Jiao et al., 2020a; Kahng and Kang, 2012; Kurdahi et al., 2010; Lee et al., 2017; Leon et al., 2021a, 2018a, 2018b; Li et al., 2018; Liu et al., 2011, 2018a, 2017, 2018b, 2019; Miguel et al., 2014; Misailovic et al., 2014, 2010; Mishra et al., 2014; Momeni et al., 2015; Park et al., 2015, 2014; Pashaeifar et al., 2018; Pilipović et al., 2021; Raha et al., 2015; Rahimi et al., 2013; Ranjan et al., 2014; Saadat et al., 2020, 2019; Sabetzadeh et al., 2019; Samadi et al., 2014, 2013; Sampson et al., 2015; Schlachter et al., 2017; Shi et al., 2013, 2014; Sidiroglou-Douskos et al., 2011; Strollo et al., 2020; Tan et al., 2015; Tziantzioulis et al., 2018; Vahdat et al., 2019, 2017; Vassiliadis et al., 2015, 2016; Venkatachalam et al., 2019; Waris et al., 2020; Yazdanbakhsh et al., 2015a; Ye et al., 2013; Zendegani et al., 2017, 2016; Zervakis et al., 2019; Ullah et al., 2018; Chen et al., 2019; Vasicek and Sekanina, 2015; Fernando et al., 2019; Joshi et al., 2019; Chen et al., 2017; Mitra et al., 2017; Fang et al., 2012; Sampaio et al., 2015; Chang et al., 2011; Esmaeilzadeh et al., 2012b; Yazdanbakhsh et al., 2015b; Moreau et al., 2015; de Kruijf et al., 2010; Esmaeilzadeh et al., 2012a; Ndour et al., 2019; Felzmann et al., 2020; Miguel et al., 2015, 2016; Li et al., 2019; Waris et al., 2021; Zhu et al., 2022; Jiao et al., 2020b; Ma et al., 2022, 2021)
Signal Processing |  (Alvarez et al., 2005; Baek and Chilimbi, 2010; Baharvand and Miremadi, 2020; Boston et al., 2015; Chen and Hu, 2013; Chiang et al., 2014; Esposito et al., 2018; Guo and Rubio-González, 2018; Gupta et al., 2013; Hashemi et al., 2018a; Jiang et al., 2016; Kang et al., 2020; Karakoy et al., 2019; Lee et al., 2017; Leon et al., 2018a, b; Linderman et al., 2010; Liu and Zhang, 2017; Liu et al., 2010, 2019; Manikantta Reddy et al., 2020; Nepal et al., 2014; Park et al., 2015; Pashaeifar et al., 2018; Ragavan et al., 2016; Rahimi et al., 2013; Ramasubramanian et al., 2013; Ranjan et al., 2014; Rubio-González et al., 2016, 2013; Samadi et al., 2014; Sampson et al., 2011; Shi et al., 2013; Stitt and Campbell, 2020; Venkatachalam et al., 2019; Venkataramani et al., 2012; Yazdanbakhsh et al., 2015a, a; Yesil et al., 2018; Zervakis et al., 2018, 2019; Sampson et al., 2014; Venkataramani et al., 2013; Nepal et al., 2019; Esmaeilzadeh et al., 2012b; Moreau et al., 2015; Esmaeilzadeh et al., 2012a; Kahng et al., 2010; Leon et al., 2021b)
Computer Vision |  (Achour and Rinard, 2015; Baharvand and Miremadi, 2020; Hoffmann et al., 2009; Karakoy et al., 2019; Li et al., 2018; Miguel et al., 2014; Misailovic et al., 2010; Mishra et al., 2014; Mohapatra et al., 2011; Nepal et al., 2014; Schkufza et al., 2014; Sidiroglou-Douskos et al., 2011; Sorber et al., 2007; Tan et al., 2015; Mitra et al., 2017; de Kruijf et al., 2010)
Computer Graphics |  (Baek and Chilimbi, 2010; Baharvand and Miremadi, 2020; Campanoni et al., 2015; Keramidas et al., 2015; Liu et al., 2011, 2019; Misailovic et al., 2013; Park et al., 2015, 2014; Sampson et al., 2011, 2014; de Kruijf et al., 2010; Esmaeilzadeh et al., 2012a)
Big Data Analysis |  (Agarwal et al., 2013; Anderson and Cafarella, 2016; Goiri et al., 2015; Hu et al., 2019; Kandula et al., 2016; Krishnan et al., 2016; Laptev et al., 2012; Park et al., 2019; Quoc et al., 2017a, b; Wen et al., 2018; Zhang et al., 2016; Joshi et al., 2019; Tseng et al., 2013; Liu et al., 2012)
Databases |  (Agarwal et al., 2013; Baek and Chilimbi, 2010; Byna et al., 2010; Kandula et al., 2016; Sidiroglou-Douskos et al., 2011; Zhang et al., 2016; Tseng et al., 2013)
Data Mining |  (Achour and Rinard, 2015; Ansel et al., 2011; Baharvand and Miremadi, 2020; Brumar et al., 2017; Byna et al., 2010; Hoffmann et al., 2009; Kislal and Kandemir, 2018; Leon et al., 2021a; Li et al., 2018; Liu et al., 2018b, 2019; Meng et al., 2009; Mengt et al., 2010; Mohapatra et al., 2011; Raha et al., 2015; Ranjan et al., 2014; Renganarayana et al., 2012; Samadi et al., 2013; Sampson et al., 2015; Shi et al., 2015; Sidiroglou-Douskos et al., 2011; Sreeram and Pande, 2010; Tan et al., 2015; Tian et al., 2015; Yazdanbakhsh et al., 2015a; Chakradhar and Raghunathan, 2010; Chippa et al., 2014; Ranjan et al., 2015; Reviriego et al., 2022; Amant et al., 2014; Esmaeilzadeh et al., 2012b; Moreau et al., 2015; de Kruijf et al., 2010; Cho et al., 2012; Sartori and Kumar, 2011; Miguel et al., 2015, 2016; Ranjan et al., 2020)
Machine Learning |  (Armeniakos et al., 2023a, b; Baek and Chilimbi, 2010; Bornholt et al., 2014; Hashemi et al., 2015; Kanduri et al., 2018; Kim et al., 2013; Kislal and Kandemir, 2018; Mishra et al., 2014; Mohapatra et al., 2011; Nepal et al., 2014; Park et al., 2019; Raha et al., 2015; Ranjan et al., 2014; Samadi et al., 2014, 2013; Tolpin et al., 2016; Yazdanbakhsh et al., 2015a; Zhang et al., 2015; Nepal et al., 2019; Chippa et al., 2014; Ranjan et al., 2015; Amant et al., 2014; Esmaeilzadeh et al., 2012b; Moreau et al., 2015; Cho et al., 2012; Sartori and Kumar, 2011; Kim et al., 2021; Miguel et al., 2015, 2016; Ranjan et al., 2020)
Artificial Neural Networks |  (Akhlaghi et al., 2018; Ansari et al., 2021; Campanoni et al., 2015; Leon et al., 2021a; Lin et al., 2017; Pandey et al., 2019; Pilipović et al., 2021; Saadat et al., 2019; Vahdat et al., 2019; Wang et al., 2020a, 2017; Yazdanbakhsh et al., 2015a; Zhang et al., 2018, 2015; Vasicek et al., 2019; Ranjan et al., 2015; Cho et al., 2012; Afzali-Kusha and Pedram, 2023; Sartori and Kumar, 2011; Cococcioni et al., 2022; Ottavi et al., 2020; Ranjan et al., 2020; Han et al., 2015b, a; Yu et al., 2017; Li et al., 2016; Yvinec et al., 2021, 2022; He et al., 2017; Hu et al., 2016; Tan and Motani, 2020; Sui et al., 2021; He et al., 2022; Lebedev and Lempitsky, 2016; Wen et al., 2016; Wang et al., 2020b; Chen et al., 2021; Rastegari et al., 2016; Hubara et al., 2016; Zhou et al., 2016; Jain et al., 2019; Han et al., 2015a; Wang et al., 2019; Ganapathy et al., 2020; Panda et al., 2017a, b; Tann et al., 2016; Venkataramani et al., 2015a, c; Lou et al., 2021; Plastiras et al., 2018; Tan and Le, 2019; Ghosh et al., 2020; Venkataramani et al., 2014; Mrazek et al., 2016, 2019, 2020; Sonnino et al., 2023; Spantidi et al., 2021; Saadat et al., 2018; Kim et al., 2018a; Hanif et al., 2019; Jain et al., 2019, 2018; Hanif et al., 2022; Guo et al., 2022; Shin et al., 2019; Ji et al., 2020; Kim et al., 2018b; Koppula et al., 2019, 2019; Kim et al., 2018b; Raha and Raghunathan, 2017, 2018; Ghosh et al., 2020; Hashemi et al., 2018b; Gong et al., 2019; Hanif and Shafique, 2022; Fan et al., 2019; Venkataramani et al., 2020; Leon et al., 2022; Lentaris et al., 2020)
Scientific Computing |  (Ansel et al., 2011; Boston et al., 2015; Brumar et al., 2017; Carbin et al., 2013; Chiang et al., 2017, 2014; Darulova and Kuncak, 2017; Guo and Rubio-González, 2018; Jiang et al., 2019; Kang et al., 2020; Karakoy et al., 2019; Laguna et al., 2019; Lam and Hollingsworth, 2018; Lam et al., 2013; Leon et al., 2021a; Menon et al., 2018; Misailovic et al., 2014, 2013; Park et al., 2015, 2014; Rahimi et al., 2013; Rinard, 2006; Rubio-González et al., 2016, 2013; Sampson et al., 2011; Schkufza et al., 2014; Yesil et al., 2018; Sampson et al., 2014; Fernando et al., 2019; Joshi et al., 2019; Yazdanbakhsh et al., 2015b; Esmaeilzadeh et al., 2012a; Sartori and Kumar, 2011; Miguel et al., 2015)
Financial Analysis |  (Achour and Rinard, 2015; Baek and Chilimbi, 2010; Baharvand and Miremadi, 2020; Brumar et al., 2017; Hoffmann et al., 2009; Li et al., 2018; Linderman et al., 2010; Liu et al., 2019; Miguel et al., 2014; Misailovic et al., 2014; Samadi et al., 2014; Sampson et al., 2015; Shi et al., 2015; Sidiroglou-Douskos et al., 2011; Tziantzioulis et al., 2018; Vassiliadis et al., 2016; Yesil et al., 2018; Zhang and Sanchez, 2018; Fernando et al., 2019; Joshi et al., 2019; Yazdanbakhsh et al., 2015b; Moreau et al., 2015; Miguel et al., 2015)
Physics Simulations |  (Achour and Rinard, 2015; Ansel et al., 2011; Brunie et al., 2020; Campanoni et al., 2015; Li et al., 2018; Liu et al., 2019; Menon et al., 2018; Miguel et al., 2014; Misailovic et al., 2013, 2012; Rinard, 2006, 2007; Samadi et al., 2014; Sampson et al., 2015; Vassiliadis et al., 2016; Yesil et al., 2018; Zhang and Sanchez, 2018; Mitra et al., 2017; de Kruijf et al., 2010; Sartori and Kumar, 2011; Miguel et al., 2015)

Image Processing: This vital process is useful in various emerging
applications from fields such as multimedia, bio-informatics and robotics,
which often require processing of tremendous amount of data with diverse
standards and formats (Alvarez et al., 2005). Fortunately, image processing
workloads exhibit tolerance against errors, as most systems can accept minor
perturbations or distortion within a quality degradation limit. Thus,
Approximate Computing has received increasing attention here to mitigate the
high computation cost and to enhance the efficiency of the deployed systems by
reasonable trade-offs based on constraints of the specific application.

A noticeable amount of Approximate Computing schemes and methodologies have
focused on the filters inside the image processing function, which are applied
to the input image to perform specific processing tasks, such as edge
detection or morphological processing (Esposito et al., 2018). Most of them
require intensive matrix computations and convolutions. Therefore, a several
works propose novel approximate functional units to replace the exact ones.
For example, RAP-CLA proposes approximate carry look ahead adders to achieve
higher Peak Signal-to-Noise Ratio (PSNR) in smoothing and sharpening
applications compared with baselines (Akbari et al., 2018). Designs of inexact
multipliers with truncation are proposed to achieve graceful quality
degradation in video compression (Frustaci et al., 2020). Additionally, image
processing often involves floating-point DSP computations, with particularly
resource-demanding mantissa bit operations, which can be approximated with
negligible quality loss (Leon et al., 2021a). Programming-level approximation
techniques also show promising results in image processing applications.
Chisel provides system-level support of optimizing approximate configurations
and shows higher energy savings as to image processing benchmarks such as
scale, DCT and IDCT (Misailovic et al., 2014). Furthermore, there are
language-specific frameworks designed for Java applications such as 3D tracers
and edge detection (Park et al., 2015).

Signal Processing: In edge computing and IoT systems, various signal
processing methodologies and algorithms are applied to process raw signal from
sensors, which are often associated to noise (Sampson et al., 2014). Recently,
signal processing algorithms are migrating from cloud-based platforms with
high computation capabilities, such as servers and desktops, to the edge and
low power-devices (i.e., embedded systems) that are often resource-constrained
and cost-sensitive. Real-time requirements are common in signal processing
systems, thus Approximate Computing schemes are proposed to suffice critical
performance requirements (Baharvand and Miremadi, 2020). Memory storage can
also benefit from Approximate Computing. For example, the work in (Sampson et
al., 2014) uses reduced precision operations (e.g., memory write) to extend
the storage lifetime.

Filters in signal processing systems usually consumes considerable amount of
energy. Finite Impulse Response (FIR) filters with voltage scaling strategies
and reduced precision redundancy can achieve considerable energy saving with
negligible degradation of Signal-to-Noise Ratio (SNR) (Chen and Hu, 2013).
Hardware-level approximate designs such as reverse carry propagate adders are
also implemented in FIRS filters to replace exact functional units (Pashaeifar
et al., 2018). Moreover, FIR filters are optimized at the architecture level,
for example, the PANDORA framework eliminates loop-carried dependencies,
achieving up to 81$\times$ speed-up with acceptable errors (Stitt and
Campbell, 2020). In addition to filters, signal transformations (e.g., the
discrete Fourier transform) are also target of approximation, as their main
computations come from trigonometric functions, which require massive amount
of floating-point computations, while at the same time they can tolerate
errors (Baek and Chilimbi, 2010).

Computer Vision: Computer vision is critical in many emerging applications
such as augmented/virtual reality, autonomous driving and robotics. These
applications often require intensive computation efforts on large volume of
data. One core component of a computer vision system is the computation kernel
known as meta-functions, which are dedicated to execute one specific
algorithm. As those meta-functions are typically inherently error resilient,
voltage scaling techniques are applied to obtain attractive quality–energy
trade-offs (Mohapatra et al., 2011). Another application, ray tracing, which
is also a common computer vision task, requires intensive arithmetic with
floating-point numbers, whose precision can be formulated as a stochastic
optimization problem for acceleration (Schkufza et al., 2014). Some computer
vision applications are deployed onto perpetual systems, i.e., embedded
systems that are not connected to power but rely on harvesting energy from the
environment. Such systems often have strict power constraints when executing
demanding machine vision algorithms. Therefore, specialized languages and
runtimes are proposed to maximize QoS on such platforms for tasks such as
tracking and remote sensing (Sorber et al., 2007).

From the software aspect, various computer vision applications including
motion estimation and body tracing also exhibit tolerance against code
perforations, inspiring opportunities of slightly compromising accuracy for
increasing the performance by two to three times (Hoffmann et al., 2009).
However, although the accuracy and quality degradation from approximation are
negligible at most times, computer vision systems may still output critically
inaccurate or erroneous results. The language Topaz enables outlier task
detection and re-execution, which can collaborate with existing approximate
solutions to ensure that tasks such as subject pose tracking produce
acceptable results (Achour and Rinard, 2015).

Computer Graphics: Modern digital photography and filming as well as 3D
modelling, rendering and simulation depend on extensive support from computer
graphics algorithms. These workloads demand a significant amount of
computations due to the visual contents that are increasingly complex.
Although computationally intensive, computer graphics show opportunities for
Approximate Computing by having a strong data locality, which indicates that
there are high redundancies that can be harvested to mitigate the computation
costs (Keramidas et al., 2015). By using cache to memorize outcomes of
instructions, computer graphics applications such as OpenGL games can have
reduced number of instructions and witness acceleration (Keramidas et al.,
2015). Additionally, by leveraging the tolerance against potentially non-
deterministic parallel execution of sequential computer graphics programs
(e.g., volume rendering), notable speed-ups can be delivered (Misailovic et
al., 2013). Another direction of enhancing the parallel computing performance
of OpenGL application via Approximate Computing is to relax the program
semantics, where code can briefly bypass strict semantic adherence to achieve
energy saving with acceptable output quality loss (Campanoni et al., 2015).

Big Data Analysis: The data query is the first and foremost task in the big
data analysis domain. Targeting improved performance, an approximate query
engine BlinkDB is proposed in (Agarwal et al., 2013). BlinkDB uses a set of
stratified samples for the aim of optimization and deploys a dynamic sampling
strategy to select an appropriately sized sample, which permits users to trade
accuracy for response time. Other works are mainly based on Big data
frameworks such as Hadoop and Spark. The authors in (Goiri et al., 2015)
propose ApproxHadoop, which is a framework to run approximation-enabled
MapReduce programs. ApproxHadoop leverages statistical theories to optimize
the MapReduce programs when approximating with data sampling and task
dropping. On the other hand, the authors in (Hu et al., 2019) present a data
sampling framework to enable approximate computing with estimated error bounds
in Spark, called ApproxSpark. In ApproxSpark a tree-based framework is
proposed to compute the approximate aggregate values and corresponding error
bounds, which can dynamically balance the trade-off among the sampling rates,
execution time, and accuracy loss.

Databases: Considering the Approximate Computing in database access, (Kandula
et al., 2016) introduces a novel data query system that injects samplers in
the run-time and without requiring former existing samples. This system allows
multiple join inputs and approximates the answer according to complex outputs.
In the meantime, inspired by parallel computing, (Sidiroglou-Douskos et al.,
2011) utilizes the nature of approximation to improve the performance and
decrease the error according to the accuracy demands.

Data Mining: During the data mining process, redundant computations, e.g.,
calling functions with the same parameters or using iterative input and output
data, increase the execution time and lead to low performance. (Brumar et al.,
2017) targets this redundant computing and proposes an approximate approach
named ATM. ATM employs both dynamic redundancy and approximation for a task-
level computing that utilizes the previous task for the future. In practice,
ATM also introduces an adaptive algorithm in the run-time that dynamically
balances the trade-off between accuracy and performance. Moreover, (Baharvand
and Miremadi, 2020) uses the core-level redundancy, which is a combination of
accurate and approximate versions of a task on different cores to increase the
reliability. On the other hand, (Kislal and Kandemir, 2018) presents a
skipping strategy aiming to improve the memory performance in data mining,
especially the recursive partitioning method such as decision tree and random
forest. (Liu et al., 2019) employs different approximate logarithmic
multipliers and unique operators to reduce power consumption and improve the
performance during the data mining process.

Machine Learning: With the development of cloud computing, an increasing
number of machine learning systems have become dominant in many sophisticated
and crucial software architectures. The machine learning models can be either
supervised or unsupervised, learn features from the training data and deploy
inference on unseen query data. Nowadays, most machine learning models are
data-driven, meaning that the key to their success is the input data. However,
in the cloud computing environment, the large scale data will make the machine
learning process tardiness and energy-consuming. To reduce resource
consumption, recent work propose approaches in different domains. (Baek and
Chilimbi, 2010) presents an energy-efficient Approximate Computing framework
that dynamically makes approximation decisions based on a predefined accuracy
level. In the meantime, (Hashemi et al., 2015) exploits the error resilience
in the machine learning system to trade off accuracy for computational
resources. Moreover, (Kanduri et al., 2018) employs a run-time resource
management approach based on functionally approximate kernels that exploit
accuracy-performance trade-offs within error resilient applications. This
approach makes performance-aware decisions on power management under varied
situations.

Artificial Neural Networks: Considering the number of arithmetic operations in
Artificial Neural Networks (ANNs), the conventional architectures perform over
millions of computations on each input data, leading to a high rate of timing
and energy consumption. Therefore, as explained in Section 3, approximation
techniques at different design layers aim to provide sufficient performance
and power efficiency. The approximation of ANNs imposes several challenges.
One of the them is to avoid retraining for reducing the accuracy loss (Mrazek
et al., 2019), while the approximation localization (Leon et al., 2022) is
also a key factor towards improved resources gains. Finally, cross-layer and
end-to-end approaches (Panda et al., 2016) further increase the resource
savings by exploiting the error resilience of each layer/sub-system.

Scientific Computing: Due to the rapid development of the computing industry
in recent decades, scientific computing has become much more powerful and
precise. Natural science research has been greatly enhanced by the
availability of new materials and methodologies as well as the development of
new hardware. A wide variety of scientific computing applications are employed
in various areas, such as meteorology, astrophysics, and molecular biology.
Though the specific tasks in scientific computing may vary, the underlying
mathematical functions used are similar. As an example, most mathematical
simulation models include linear equations, nonlinear equations, eigenvalue
problems, FFT analysis, and ODEs. Nevertheless, the growth in computational
power cannot completely meet the computing demands of scientific computing.
Therefore, the scientific computing community aims to develop more efficient,
robust, and fast frameworks for scientific computations to meet these demands.

As the mathematical models for scientific computing become increasingly
complex and the advanced sensors collect vast amounts of data, the computing
resources become the bottleneck. Scientific computing entails a considerable
amount of continuous computation, while typically, its targeted result is
always approximate. Generally, increased computation precision will provide a
more accurate result, but it will also consume more resources. Scientists
usually employ double-precision computations to achieve a precise result,
which is expensive. Many studies have examined the trade-off between precision
and performance. One of the ideas is to get a balance between them by tuning
the floating-point precision into mixed precision. The implementation in (Lam
et al., 2013) uses binary instrumentation and modification to build mixed-
precision configurations, whereas (Brunie et al., 2020) uses dynamic program
information and temporal locality to customize floating-point precision for
scientific computing. Two of these approaches use the system’s floating-point
variables as search space and assume the system to be a black box in order to
find the best configuration with some loss in accuracy. By analyzing the
dependence between floating-point variables, the authors in (Guo and Rubio-
González, 2018) design a community structure of floating-point variables and
devise a scalable hierarchy for optimization. Furthermore, the tools presented
in (Chiang et al., 2014) focus on determining the input settings for a
floating-point routine to understand how they affect the result’s error.

Even though cluster computers are relatively reliable, minor software and
hardware faults may still occur, particularly during the execution of lengthy
tasks, like those of scientific computing. This makes reliability and
robustness an important consideration when carrying out scientific computing.
(Rinard, 2006) presents a methodology that estimates an acceptable accuracy
bound based on the impacts of different computation errors and faults on the
entire task. The technique is not only useful in helping to create robust
scientific computing frameworks, but it can also be used to discard
computations to save execution time in a reasonable manner. The work in
(Carbin et al., 2013) presents a programming language that can determine the
quantitative reliability of a specific computing application running on
unreliable hardware. The skipping of data accesses is not only for precision
tuning and robustness analysis but also for boosting the computations.
Similarly, special hardware designs can be viewed as an approximation
technique. (Jiang et al., 2019) devise a special divider and square root
circuit that uses an adaptive approximation to increase the computation rate
and save energy.

Financial Analysis: Financial analysis is another area in which approximate
computations can be useful. The internet and the digitalization of the
financial industry have led to increased importance of computation in
financial analysis, especially when analyzing large amounts of data and
incorporating machine learning. With the advent of these technologies,
quantitative finance models continue to develop. The use of approximate
computations increases the efficiency of data analysis, as well as enables
real-time processes. For example, (Tziantzioulis et al., 2018) demonstrate a
compiler-directed output-based approximate memoization function that provides
speedup in two different financial analysis applications to pricing a
portfolio of stock options and swaptions. In the meanwhile, (Joshi et al.,
2019) presents a framework for algorithmic profiling known as AXPROF for
analyzing randomized approximate programs, which are important to the analysis
of big financial data.

Physics Simulations: Apart from being a part of scientific computing,
simulation of physical phenomena involves some more specific areas, such as
hydrodynamics simulation, thermodynamics simulation, and optical simulation.
Many of these tasks are very compute-intensive. Approximate Computing can be
applied to the physics simulation to accelerate this process. (Mitra et al.,
2017) presents a novel system called OPPROX for the application’s execution-
phase-aware approximation. OPPROX is demonstrated to be an efficient method
for reducing dozens of workloads in a simulation of the Sedov blast wave
problem. Additionally, the authors in (Campanoni et al., 2015) seek to combine
Approximate Computing with automatic parallelization by allowing the user to
select tuning knobs that can be used to trade performance gains and/or energy
savings for output distortion.

###  5.2. Application-Driven Analysis of Case Studies

Table 4. Remarkable improvements among all examined works with respect to the application domain and the different layers of computing stack. Application Domain | Stack | #Works | Main Techniques | Remarkable Gains | Ref.
---|---|---|---|---|---
Image Processing | SW | 24 | Approx. Progr. Language |  | 34% energy gains &
---
113$\times$ less programming effort
(Park et al., 2014)
HW | 25 | Multiplier Approx. |  | 95% energy gains & 85% area
---
reduction for 1% accuracy loss
(Vahdat et al., 2019)
Arch | 25 | Approx. Data Storage |  1.7$\times$ speedup for <10% quality loss | (Sampson et al., 2014)
Signal Processing | SW | 13 | Precision Scaling |  1.33$\times$ speedup for no accuracy loss | (Kang et al., 2020)
HW | 11 | Approx. Synthesis | 60% power gains for <2% avg. error | (Venkataramani et al., 2013)
Arch | 4 | Approx. Processor |  |  2.3$\times$ speedup & 3$\times$ energy gains
---
for <10% accuracy loss
(Esmaeilzadeh et al., 2012b)
Computer Vision | SW | 12 | Loop Perforation | 35% energy gains & 40% area reduction | (Baharvand and Miremadi, 2020)
HW | 3 | Approx. Synthesis | 23% power gains & 19% area savings | (Nepal et al., 2014)
Arch | 1 | Approx. Processors | 40% energy gains for negligible quality loss | (de Kruijf et al., 2010)
Computer Graphics | SW | 10 | Approx. Progr. Language |  2$\times$–17$\times$ energy gains | (Park et al., 2015)
HW | 0 | – | – | –
Arch | 3 | Approx. Processor | up to 43% energy gains | (Esmaeilzadeh et al., 2012a)
Big Data Analysis | SW | 13 | Data Sampling |  up to 8$\times$ speedup & 38% wait time reduction | (Anderson and Cafarella, 2016)
HW | 0 | – | – | –
Arch | 2 | Approx. Data Storage |  |  1.8$\times$–5.7$\times$ speedup for <1%
---
memory overhead
(Liu et al., 2012)
Databases | SW | 5 | Data Sampling |  up to 20$\times$ speedup for precise execution | (Zhang et al., 2016)
HW | 0 | – | – |
Arch | 2 | Approx. Data Storage |  | 22%–45% energy gains for
---
0.1% performance loss
(Tseng et al., 2013)
Data Mining | SW | 19 | Loop Perforation |  6.4$\times$/7.1$\times$ for 5%/10% error budget | (Li et al., 2018)
HW | 5 | Multiplier Approx. |  | up to 86% power, 46% delay & 63% area
---
gains for NMED <0.0081
(Liu et al., 2018b)
Arch | 14 | Approx. Processor |  |  1.2$\times$ speedup, 1.4$\times$ energy gains
---
for 6% quality loss
(Esmaeilzadeh et al., 2012b)
Machine Learning | SW | 12 | Computation Skipping |  2.18$\times$ energy gains for <0.5% accuracy loss | (Raha et al., 2015)
HW | 10 | Voltage Over-Scaling | 22% power reduction for no accuracy loss | (Armeniakos et al., 2023b)
Arch | 10 | Approx. Processor | 24% energy reduction for no accuracy loss | (Ndour et al., 2019)
Artificial Neural Networks | SW | 40 | Computation Skipping |  |  2$\times$ speedup, 1.9$\times$ energy gains
---
for 3% accuracy loss
(Akhlaghi et al., 2018)
HW | 40 | Multiplier Approx. |  2.8$\times$ power gains for 5% accuracy loss | (Leon et al., 2021a)
Arch | 7 | Approx. Data Storage |  |  up to 2$\times$ energy gains for
---
negligible accuracy loss
(Ranjan et al., 2020)
Scientific Computing | SW | 26 | Approx. Progr. Language |  |  up to 1.25$\times$ energy gains for
---
negligible quality loss
(Misailovic et al., 2014)
HW | 2 | Divider Approx. |  |  3.9$\times$ speedup, 4.8$\times$ power gains
---
for <5% NMED
(Jiang et al., 2019)
Arch | 6 | Approx. Data Storage |  |  up to 2.55$\times$ energy gains, 1.55$\times$ cache
---
area reduction for <10% quality error
(Miguel et al., 2015)
Financial Analysis | SW | 19 | Approx. Memoization |  |  16$\times$ speedup for 5% memory overhead &
---
<3% accuracy loss
(Brumar et al., 2017)
HW | 0 | – | – |
Arch | 4 | Approx. Processor |  2.1$\times$ energy gains for 4% quality loss | (Rinard, 2006)
Physics Simulations | SW | 16 | Approx. Memoization |  3$\times$ speedup for 10% quality loss | (Samadi et al., 2014)
HW | 0 | – | – |
Arch | 5 | Approx. Processor |  1.25$\times$ energy gains for negligible quality loss | (de Kruijf et al., 2010)

Table 4 presents the respective analysis of the aforementioned application
domains, including also some statistical results about the dominant sub-
categories for each layer of the computing stack. Regarding the distribution
of the main techniques in the various research areas, Table 4 reveals a
considerable heterogeneity that is contingent upon the particular use case. As
shown, works in image processing are almost evenly distributed through the
entire computing stack (i.e., 24 software-, 25 hardware-, and 25 architecture-
level works). However, within the specific domain, notably, multiplier
approximations dominate over the other hardware techniques, accounting for
almost 80% of the total works. Similar observations arise for big data
analysis, where software-oriented approximations this time, and specifically
data sampling sub-category, constitute the vast majority and the most
prominent solutions. On the other hand, it is noteworthy that in five
application domains (computer graphics, big data analysis, databases,
financial analysis and physics simulations) there are no works focusing on
hardware-level approximations. This might be explained by the fact that
research and development efforts in these domains are traditionally revolved
around software algorithms, optimizations and data management techniques,
rather than the lower level of the design abstraction hierarchy. The latter
highlights, thus, the space for further exploration and development of
hardware-oriented approximate designs.

Table 4 also reports some significant experimental results, most of them
concerning speedup, area and power/energy gains over conventional designs,
with their respective overheads and/or quality losses. Out of all the
techniques reported, it is observed that software-based approximations realize
the highest speedups compared to hardware and architectural approximations.
For example, the memoization approach of (Brumar et al., 2017) achieves
16$\times$ speedup for only 5% memory overhead and 3% accuracy loss, while
(Zhang et al., 2016) manages up to 20$\times$ speedup for accurate execution.
Finally, the table underscores the potential of Approximate Computing in
machine learning applications, at each layer of the computing stack, that can
attain remarkable energy reduction (22%–54%), while maintaining unaffected the
level of quality with zero accuracy loss.

###  5.3. Benchmark Suites and Error Metrics

Various open source benchmark suites for approximate computing have been
proposed and released. In Table 5, we report some of the most well-established
suites, which have been employed in the state-of-the-art works examined in
this survey. Parallel programming benchmarks including PARSEC (Princeton
Application Repository for Shared-Memory Computers) (Bienia et al., 2008) and
SPLASH-2 (Stanford Parallel Applications for Shared Memory) (Woo et al., 1995)
are cross-domain benchmark suites with different emerging applications for
evaluating and studying parallel chip-multiprocessors. There are also
benchmarks focusing on multimedia and communication applications such as
MediaBench (Lee et al., 1997). SciMark is a benchmark suite primarily focusing
on Java language applications of scientific computing, including kernels like
FFT, sparse matrix multiplication, Monte Carlo simulation and successive over-
relaxation (Pozo and Miller, 2004). With the development of multi-platform
parallel or acceleration libraries such as OpenMP, OpenCL and CUDA, more
recent benchmarks focus on those libraries and frameworks. Rodinia is a
benchmark set for heterogenous computing with diverse applications targeting
at platforms from multi-core CPU systems to GPUs (Che et al., 2009). Regarding
hardware, AxBench provides Verilog and C benchmark implementations
(Yazdanbakhsh et al., 2017).

Table 5. Open-source benchmark suites used in state-of-the-art works of Approximate Computing. Benchmark Suite |  Source Code |  Application Domain
---|---|---
_PARSEC_ (Bienia et al., 2008) | C/C++ |  Image Processing, Computer Vision, Data Mining, Financial Analysis, Physics Simulations
_SPLASH-2_ (Woo et al., 1995) | C |  Scientific Computing, Computer Graphics, Physics Simulations
_MediaBench_ (Lee et al., 1997) | C |  Image Processing, Signal Processing
_MiBench_ (Guthaus et al., 2001) | C |  Image Processing, Signal Processing
_MiniBench_ (Narayanan et al., 2006) | C/C++ |  Data Mining
_Rodinia_ (Che et al., 2009) | OpenMP, OpenCL, CUDA |  Data Mining, Scientific Computing, Physics Simulation, Machine Learning
_PolyBench_ (Pouchet, 2015) | C, CUDA |  Scientific Computing
_SciMark 2.0_ (Pozo and Miller, 2004) | Java |  Scientific Computing
_AxBench_ (Yazdanbakhsh et al., 2017) | C++, CUDA, Verilog |  Image Processing, Signal Processing, Computer Graphics, Data Mining, Financial Analysis
Table 6. Error/QoS metrics of Approximate Computing. Metric |  Description |  Application Domain
---|---|---
_ER_ |  Error Rate – Erroneous results per total results | General Computing
_EP_ |  Error Probability – Probability of error occurrence
_MED/MRED_ |  Mean (Relative) Error Distance
_NMED/NMRED_ |  Normalized Mean (Relative) Error Distance
_Max ED/RED_ |  Maximum (Relative) Error Distance
_PED/PRED_ |  Probability of (Relative) Error Distance $>X$
_MSE_ |  Mean Squared Error
_RMSE_ |  Root Mean Squared Error
_HD_ |  Hamming Distance
_BER_ |  Bit Error Ratio – Bit errors per total received bits |  Digital Systems, Telecommunications
_PER_ |  Packet Error Ratio – Incorrect packets per total received packets
_PSNR_ |  Peak Signal-to-Noise Ratio – Quality measurement between images |  Image Processing, Video Processing, Computer Vision
_SSIM_ |  Structural Similarity – Quality measurement between images
_MPD_ |  Mean Pixel Difference
_Classif. Accuracy_ |  Correct classifications per total classifications |  Pattern Recognition, Information Retrieval, Machine Learning
_Precision_ |  Relevant instances per total retrieved instances
_Recall_ |  Relevant instances per total relevant instances

Various error/QoS metrics have been proposed to describe and evaluate the
capability of Approximate Computing techniques and methodologies, as shown in
Table 6. At the bottom level, different error rates are used, such as Error
Rate (ER), which calculates the number of erroneous results over the total
number of results, and correspondingly, Bit Error Ratio (BER), which
calculates the number of erroneous bits over the total bits. Another family of
error metrics is the Error Distance (ED), including Hamming Distance (HD),
Mean (Relative) ED (MED/MRED), Normalized MED (NMED), and other numerical-
based metrics. Another metric that is employed in the evaluation of
approximate designs is the Probability of (Relative) ED higher than $X$
(PRED/PRED), where $X$ is a numerical value, Finally, Mean Squared Error (MSE)
and Root MSE (RMSE) are also common metrics to evaluate the output quality.

There are also application-specific error metrics to describe the efficiency
of the approximations at a higher level. For example, in telecommunications,
Packet Error Ratio (PER) is usually considered to evaluate the communication
quality. In ML applications, such as pattern recognition and information
retrieval, classification accuracy is usually considered, as well as other
metrics such as precision (relevant instances of retrieved instances) and
recall (relevant instances of total instances). These metrics provide a
systematic view on the assessment of the approximate application.

##  6\. Challenges and Future Directions

This section highlights several key challenges that need to be addressed to
accelerate progress in Approximate Computing and enable its use in real-world
systems.

Cross-Layer and End-to-End System-Level Approximations: Most of the research
in Approximate Computing have focused on individual abstraction layers of the
computing stack. However, the true potential of Approximate Computing lies in
cross-layer and end-to-end system-level approximations, where multiple
complementary approximation techniques are combined to achieve a better
quality–efficiency trade-off. Therefore, a system-level view is necessary for
trading quality for efficiency, as approximation can be deployed at different
abstraction layers and in different components. Only the right set of
approximations deployed at the right layers and in the right components can
offer optimal returns. Some existing works in this direction include (Agrawal
et al., 2016; Ghosh et al., 2020; Hashemi et al., 2018b). However, still a
significant amount of research is required to develop sophisticated automated
methodologies that can efficiently identify the appropriate set of
approximations for all the components in a system to offer the best
quality–efficiency trade-off while satisfying the user-defined constraints.
One of the key limitations towards enabling such methodologies is the lack of
tools and methods that can efficiently and accurately quantify the impact of
approximations, specifically multiple types of approximations, on the
application-level accuracy of the systems.

Hardware Models: The field of Approximate Computing lacks validated hardware
models that are essential for performing efficient-yet-accurate design space
exploration to select appropriate level of approximation for each hardware
module in the system. For example, the models used for voltage overscaling are
based on assumptions about the distribution of errors in computing and memory
structures. Similarly, most of the ReRAM-based in-memory computing works are
based on assumptions about the precision with which values can be written to
or read from the memory arrays. Moreover, different works use different models
and assumptions, which makes it difficult to compare techniques based on the
reported results. Therefore, there is a dire need for building hardware models
that have been validated by the hardware community through extensive
simulations. The models need to be validated for a wide variety of scenarios
to enable their reliable deployment in cross-layer approximation
methodologies.

Benchmarks: The Approximate Computing community lacks representative sets of
applications as well as datasets from different application domains that can
be used for benchmarking approximation techniques. Having a carefully selected
set of applications and datasets is crucial, as the impact of approximations
can vary drastically from application to application and even from data sample
to data sample. Some efforts have been made towards defining benchmarks, e.g.,
AxBench (Yazdanbakhsh et al., 2016); however, these efforts cover only a small
set of applications and scenarios. Therefore, there is a need for a much
broader set of applications and datasets from a wider spectrum of application
domains. Moreover, as it is difficult to cover all the application domains and
applications, specifically when new applications are emerging on a daily basis
due to the rapid pace of technology growth, there is a need for standards and
rules for defining evaluation strategies and selecting datasets for an
unbiased and thorough evaluation of approximation techniques.

Evaluation Metrics: Design space exploration methodologies are guided through
quality and performance evaluation metrics to find the optimal configurations
that offer the best quality–efficiency trade-offs and meet all the user-
defined constraints. As a result, it is crucial to have reliable quality and
performance evaluation metrics in place. Metrics that do not capture suitable
characteristics can lead to sub-optimal configurations, eventually affecting
the user experience. Therefore, it is essential to define the right set of
quality evaluation metrics for each application.

Post-Fabrication Testing: Process variations, which lead to permanent faults
and variations in the hardware characteristics of transistors, are a major
concern in nano-scale devices. All the fabricated devices are passed through
post-fabrication testing to detect manufacturing-induced defects and
variations. However, approximations make this already challenging process
further challenging. Only a limited amount of work has been carried out
towards testing of Approximate Computing devices. Therefore, there is a dire
need for specialized approximation-aware testing methodologies that can enable
efficient-yet-accurate testing of these devices and reduce the yield loss,
wherever possible, through binning.

Reproducibility for Fair Comparison and Future Developments: In most cases, it
is challenging to replicate the exact evaluation methodology and setup
reported in research works, making it difficult (if not impossible) to
reproduce the results. Therefore, it is essential to promote open-source
contributions to ensure the reproducibility of the results. The open-source
contributions will also facilitate further research and development in the
area of Approximate Computing, resulting in rapid progress towards uncovering
the true potential of Approximate Computing for improving the efficiency of
computing systems.

##  7\. Conclusion

In this article, we presented Part II of our survey on Approximate Computing,
which reviews the state-of-the-art application-specific and architectural
approximation techniques. Regarding the application-specific techniques, we
focused on the emerging AI/ML applications and discussed about software,
hardware, cross-layer and end-to-end approximations. Regarding the
architectural techniques, we focused on approximate processors & accelerators
and different memory types for approximate data storage. Moreover, we
performed an extensive analysis of the application spectrum of Approximate
Computing, i.e., we classified per domain all the works reviewed in our two-
part survey, we presented representative techniques and remarkable results, as
well as we reported well-established error metrics and benchmark suites for
evaluating the quality-of-service of approximate designs. Despite the notable
progress demonstrated by Approximate Computing, there remains a pressing need
for ongoing and significant innovation to fully realize the potential of
approximations in the design of complex computing systems. These open
challenges are discussed along with future directions at the end of our
survey.

## Acknowledgement

This research is supported in parts by ASPIRE, the technology program
management pillar of Abu Dhabi’s Advanced Technology Research Council (ATRC),
via the ASPIRE Awards for Research Excellence.

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