its output reliability and its resiliency against ML-based attacks. In CMA-PUF
(Wang et al., 2017a), transistors are sized small and are operated in sub-
threshold region to maximize the mismatch. Further, the PUF utilizes a current
controlled oscillator (CCO) to digitize the current values of each column in
the CMA. In (Shah et al., 2021), the authors propose a Rec-CMAPUF where they
replace CCO with a shared comparator to eliminate each column CCO’s bias. They
then feed the comparator’s digitized output back to the input and perform the
XOR operation to get the final output. This feedback or recurrence operation
introduces non-linearity in the challenge-response-pair (CRP) space and
increases the resistance to ML attacks. As analog PUFs are becoming more
attractive, especially in the context of cryptographic ICs, the deep learning
based sizing tools like RL based tools will surely be used to explore the
design space and devise more reliable PUFs. For example, the sizing tools in
(Settaluri et al., 2020; Wang et al., 2020; Wang et al., 2018c) can easily be
used to include the PUF specifications as the additional design requirement
and size the circuit to design a PUF robust across all possible challenge-
response pairs.

Table 6. AI/ ML based techniques and primitives to tackle security issues in
analog ICs.

| Design stage
---
Techniques | AI/ ML algorithm | Security Issues tackled
| PUF (Shah et al., 2021; Chowdhury et al., 2020a) | RNN (Shah et al., 2021), (GA, LP) (Chowdhury et al., 2020a) | IP Piracy and Counterfeiting
Circuit Design | Logic Locking (Volanis et al., 2019; GummidipoondiJayasankaran et al., 2020) | ANN (Volanis et al., 2019), Simulated annealing (GummidipoondiJayasankaran et al., 2020) | IP Piracy (Volanis et al., 2019), Overproduction (GummidipoondiJayasankaran et al., 2020)
Layout | ObfusX (Zeng et al., 2021) | Explainability with RepTree | IP Piracy, Hardware Trojans
Simulation | Aging simulation |  | RNN (Rosenbaum et al., 2020),
---
(K-means, NN, SVM) (Santhana Krishnan and Palanisamy, 2021)
IC Recycling
Fabrication |  | Split Chip Design (Pagliarini et al., 2020),
---
Fab-of-origin (Ahmadi et al., 2016)
| Branch-and-bound algorithm (Pagliarini et al., 2020),
---
(PCA, DNN, etc.,) (Ahmadi et al., 2016)
IP Piracy
Test |  | Side-channel fingerprinting
---
and Authentication
mechanisms
| ANN (Liu et al., 2015), (MLP, CNN)] (Hanna and Cabric, 2019), PCA (Casto,
2018),
---
SVM (Chang et al., 2014; Acharya et al., 2021), (K-means, KNN, SVM) (Chowdhury
et al., 2020c)
| Hardware Trojan (Liu et al., 2015),
---
(Counterfeiting, Cloning) (Casto, 2018),
IC Recycling (Chowdhury et al., 2020c; Chang et al., 2014; Acharya et al.,
2021; Huang et al., 2012)

####  4.4.2. Analog Locking Techniques

There have been several attempts to expand logic locking to protect analog ICs
from piracy and counterfeiting. These techniques either try to obfuscate the
circuit current or the voltage biasing to hide the correct functionality of an
analog IC. However, most of these techniques are susceptible to logic removal
and model approximation attacks (Jayasankaran et al., 2019b; Acharya et al.,
2020) because of low transistor count, large transistor size, and the fact
that the key is implemented in digital domain. To improve the resiliency
against such attacks, logic locking techniques utilizing ML algorithms have
been proposed. Volanis et al. in (Volanis et al., 2019) proposed the use of an
on-die analog neural network where the trained ANN acts as a lock and its
analog input acts as a key. This is achieved by eliminating direct access to
the biasing inputs of the analog IC by utilizing the ANN for biasing the IC to
its operating point. The ANN is made programmable by the use of floating-gate
transistors which serves as a permanent storage for the synapse weights.
Furthermore, the keys are in analog domain and are continuous in nature
allowing for a large number of key options making this locking technique
resilient against brute-force and logic removal attacks. However, because of
the very same fact, there does exist a number of possible keys that can give
one similar performance as the oracle output. A possible way to ensure that
does not happen is to find a global solution using methods such as the one
described in (Li et al., 2019) that utilizes GA-based global search and ANN-
based local minima search techniques.

Similarly, (GummidipoondiJayasankaran et al., 2020) attempts to tackle the
issue of overproduction of an IC by a foundry. This technique, however,
implements the lock in the digital section of an AMS circuit to minimize the
effects of process variation by implementing a tuning knob to optimize the
values of passive components in an analog circuit. The lock essentially
controls the tuning knob based on an on-chip simulated annealing (SA) based
digital optimizer (Wang et al., 2015b) to help nullify process variation-
related effects. This optimizer hence acts as an post-processing tool that
helps obtain a robust output. However, the area overhead of implementing the
self-optimization architecture and the lock is too high for a typical AMS
circuit such as band-pass filter, LNA, and a low-dropout oscillator (LDO) as
proposed in the paper. This could be overcome by designing robust analog
models using learning based approaches (Hasani et al., 2017; Pan et al., 2019)
to find optimal design parameters without the use of additional circuitry.
Moreover, the RL-based techniques (Wang et al., 2020; Settaluri et al., 2020)
can tune the design to be robust against process variations by using multiple
design runs and leveraging its transfer learning abilities.

####  4.4.3. Layout Obfuscation

(Zeng et al., 2021) proposed an obfuscator for split manufacturing that relied
on explainability of ML-based attacks. As discussed earlier, split
manufacturing is a technique where the untrusted foundry only receives and
fabricates a partial layout to prevent the attacker from extracting the full
design or IP of an IC. However, this still does not prevent ML-based attacks
if the layout is either not obfuscated properly or is not obfuscated at all.
The method in (Zeng et al., 2021) implements different routing-based
obfuscation techniques such as blockage insertion, routing perturbation, and
wire-lifting based on an explanatory metric devised by leveraging ML attack
models. The metric, shapely additive explanation (SHAP) value essentially
helps identify the most vulnerable connections within a layout and helps the
obfuscator redo the obfuscation until the desired SHAP value is reached. This
obfuscator can be easily incorporated with automated layout tools such as
MAGICAL (Chen et al., 2020b) to perform highly secure layouts of analog ICs.

####  4.4.4. Aging Simulation

Incorporating aging analysis and simulation in the design step helps the
designer or the IP owner characterize the performance of the circuit according
to its life-cycle or usage. Such characterization can also help classify if
the chip has been recycled or not. There are commercially available tools such
as RelXpert by Cadence (Schaldenbrand, 2019) and MOSRA by Synopsys (Tudor et
al., 2011) which calculate the damage to transistors at incremental simulation
times. There are also behavioral models utilizing RNNs to model aged circuits
as RNNs are compatible with transient current simulation. The trained RNN
models can effectively predict the behavior of a “fresh” circuit if it is aged
and inversely can help predict the age of an used or aged chip (Rosenbaum et
al., 2020). In this regard, the works in (Rosenbaum et al., 2020; Santhana
Krishnan and Palanisamy, 2021; Chowdhury et al., 2020c; Chang et al., 2014)
utilize different ML algorithms to predict the age of an used IC. The recent
work in (Santhana Krishnan and Palanisamy, 2021) can predict as low as just
1-day of aging. However, the success of this classification is highly
dependent on the aging model developed during the design step which uses the
model library, the aging models, and Monte Carlo simulations to help
distinguish between process variation related changes and aging related
effects. Incorporating circuit specific behavioral models developed using ML
techniques such as the operational amplifier model in (Murphy and McCarthy,
2021), LNA model in (Dumesnil et al., 2014), and oscillator model in (Yu et
al., 2017) can help design more accurate and robust aging models for various
analog circuits. These aging characteristics can be further used after the
chip is fabricated by comparing the output performance of fresh, unused ICs to
a used one. There are several such techniques proposed which will be explained
in Section 4.4.6.

####  4.4.5. Split Chip Design and Fab-of-origin

Split chip design as proposed in (Pagliarini et al., 2020) differs from its
previous counterpart split chip manufacturing proposed in (Vaidyanathan et
al., 2014). The split-chip design consists of dividing the entire chip design
into two parts such that they can later be integrated to produce the intended
functionality. By doing this, split-chip design avoids technological
complexity and logistical challenges of split manufacturing. The design
partitioning into multiple sections is then formulated as an optimization
problem which is solved using a branch-and-bound algorithm. The objective
function is devised based on the vulnerability metric which is essentially the
product of exposure (effectiveness of a particular configuration) and
criticality (importance of individual models) (Pagliarini et al., 2020). Split
chip design has been described as being effective in tackling the problems of
IP theft and piracy within the IC supply chain. However, the chip is split
into multiple parts after the design is finalized meaning the appropriate
topology is selected and the circuit is already sized and biased
appropriately. The circuit designer can easily incorporate this vulnerability
metric based optimization with the automated circuit sizing tools such as the
one shown in Table 5 to design even more secure analog circuits. Similarly,
Ahmadi et al. (Ahmadi et al., 2016) proposed a fab-of-origin attestation
technique that leverages wafer-level parametric measurements without any
information of the design underneath the die to distinguish between chips
fabricated in different facilities. The authors proposed solutions for
different scenarios related to this attestation problem and relied on several
ML techniques such as PCA and DNN.

####  4.4.6. Side-channel based Fingerprinting and Authentication Mechanisms

The side-channel parameters such as power, delay, EM, etc., emitted by an
electronic device can be used as a fingerprint of such device to statistically
assess if the device is authentic or not. There are several works which make
use of behavioral models developed during the design stage to help
characterize a fabricated chip as authentic or not. In this regards, the
concurrent hardware Trojan detection (CHTD) technique proposed in (Liu et al.,
2015) helps detect Trojans in a wireless RFICs specifically in cryptographic
ICs by continuously extracting side-channel fingerprints and evaluating them
on a trained on-chip neural classifier. This classifier essentially looks for
systematic variations introduced by the hardware Trojan in the transient
supply current to expose the malicious operation.

Similarly, the work in (Hanna and Cabric, 2019) trains behavioral models (MLP
and CNN) of RF transmitters to devise an authentication mechanism. Essentially
these models exploit the non-linear characteristics exhibited by the power
amplifier to uniquely identify each RF transmitter deployed in the field. The
authors evaluated these models under various factors concerning the effects of
signal quality, packet length, channel model and modulation type to
demonstrate its effectiveness. Similarly in (Casto, 2018), the author proposes
to use Process Specific Function (PSFs) for authenticating AMS ICs such as
data converters. The harmonic frequencies and their corresponding magnitude
levels are used to develop the PSF-based device identification model. The
presented results showed the detection rate of $90\%$ using PCA and the PSF-
based model. These side-channel based fingerprints however may not be as
effective once the circuit starts to age. Hence, integrating aging models
during the design step such as (Rosenbaum et al., 2020) can help design robust
fingerprinting mechanisms. Similarly, there are several techniques such as
(Chang et al., 2014; Chowdhury et al., 2020c; Huang et al., 2012; Chowdhury et
al., 2020b) who instead exploit aging characteristics without the behavioral
models to train a classifier that can successfully distinguish between an aged
and an authentic IC. However, these techniques require the use of a golden IC
to train an effective model.

One of the recent works in (Acharya et al., 2021) which is basically the
extension of the work in (Chowdhury et al., 2020c) instead devises an odometer
by re-purposing the existing LDO structure present inside almost every IC.
This LDO-odometer basically contains two different paths, a reference path
which is not aged even when its send out to the field, and a normal path which
is activated when out in the field. This self-referencing approach and a
trained one-class SVM is then exploited to help characterize if the chip is
recycled or not (Acharya et al., 2021) without the use of a golden IC. These
aging-based classifiers can be improved by developing behavioral models at the
design step which can help better characterize the profiles of these analog
devices. For example, the learning methodology to develop behavioral models
for complex MIMO system in (Hasani et al., 2017) can be used to characterize
the LDO in (Chowdhury et al., 2020c) and the oscillator and LNA in (Chang et
al., 2014) at the design stage which helps improve the robustness of these
aging-based authentication mechanisms. Furthermore, the automated synthesis
techniques such as (Settaluri et al., 2020; Wang et al., 2020; Wang et al.,
2018c) can be used to size the odometer in (Acharya et al., 2021) without
incurring extra area and performance overhead.

###  4.5. Security Issues for Analog Security Primitives

Table 7. Security vulnerabilities faced by analog ICs.

Attacks on | Technique | AI/ ML alg
---|---|---
Analog design | Reverse engineering (Cornforth and Lipson, 2014) | EC (Cornforth and Lipson, 2014)
PUFs |  | Poster attack (Ye et al., 2016),
---
Ensemble meta-algorithms (Vijayakumar et al., 2016)
| Simulated annealing and EA (Ye et al., 2016),
---
Bagging and Gradient Boosting (Vijayakumar et al., 2016)
Logic locking techniques | Attack of the genes (Acharya et al., 2020) | GA (Acharya et al., 2020)

Table 7 summarizes some of the techniques that utilizes ML and optimization
algorithms to execute attacks on an analog IC.

####  4.5.1. Attacks on Analog Design

The reverse engineering technique proposed in (Cornforth and Lipson, 2014) was
one of the earliest works that used evolutionary computation (EC) to reverse
engineer the netlist of a simple non-linear analog IP by treating the circuit
as a ”black box”. Although the reverse engineered netlist might differ from
the actual netlist, the performance of both of these circuits matched
rendering the success of such an approach. The recent automated design
approaches specially the ones using DL and RL-based techniques may be used to
reverse engineer an analog circuit. For example, the automated CNN-based
topology selection technique in (Matsuba et al., 2018) and the RL-based
circuit sizing tool in (Wang et al., 2018c) can figure out the netlist with
comparable performance within a day. Furthermore, MAGICAL (Chen et al.,
2020b), the automated layout technique can perform an optimized layout that
might even outperform the actual design.

####  4.5.2. Attacks on PUFs

Although PUFs could be resilient to physical as well as ML-based attacks,
there are several works which leverages ML techniques to attack a PUF. The
work proposed in (Ye et al., 2016) was one of the first works that used a
compound heuristics of evolutionary strategy (ES), SA, and ant-colony to
efficiently attack current mirror PUF (Kumar and Burleson, 2014) and the
voltage transfer PUF (Vijayakumar and Kundu, 2015) with an accuracy of $99\%$.
Similarly, the work in (Vijayakumar et al., 2016) use bagged trees and
boosting technique to attack the non-linear analog PUFs. Bagged trees
basically aggregates predictions from different instances of decision trees
which are fed with disjoint subsets of training set to obtain the final
response. While boosting ensemble of meta-algorithms is used to reduce the
inherent bias present in DTs by increasing the model complexity. Nonetheless,
the authors in (Vijayakumar et al., 2016) elaborate on some analytical
techniques based on the principal of functional composition to evaluate a PUF
on its ML-attack resistance. These techniques can be used as security
constraints during the process of analog synthesis using automated sizing
frameworks like (Settaluri et al., 2020; Wang et al., 2018c) to size the PUF
accordingly and design a ML-attack resistant PUF.

####  4.5.3. Attacks on logic locking techniques

There are several methods proposed to attack analog logic locking techniques
such as (Jayasankaran et al., 2019a; Acharya et al., 2020). Both of these
works assume that the attacker has access to the obfuscated netlist and knows
where in the IC the key is being applied. The work in (Jayasankaran et al.,
2019a) uses SMT-solver to extract the correct key locking the analog circuit.
While the work in (Acharya et al., 2020) uses GA to find the obfuscated
parameter and the secret key. For this purpose, they devise an objective
function based on the difference of the oracle output and the simulated output
where the simulated output represents the output obtained by applying a random
key generated using GA. Then given given the oracle output and the obfuscated
netlist, they demonstrate how the attacker can easily estimate the value of
the obfuscated parameter to reduce the search space for finding the correct
key.

##  5\. Gaps and Opportunities in AI-based Security-aware EDA

###  5.1. Ecosystem Essentials for Accelerating Research and Development

####  5.1.1. Open-Source Benchmarks, Benchmark Generation Tools, and Data
Augmentation

The academic community is plagued by a lack of benchmarks to facilitate
research and experimentation. For pre-silicon tool development, most
researchers rely on common sets such as the ISCAS (’85, ’89, ’99) and
OpenCores benchmarks (Jenihhin, [n.d.]). Although these have varying degrees
of complexity, the available designs do not accurately capture the entire
space of today’s IC industry. Companies are particularly hesitant to make even
their most outdated designs available due to confidentiality of IPs. The
result is a dissonance between academic research and industrial development,
which is even more problematic for AI-based EDA. To develop effective AI/ML
models, vast amounts of quality data are required. This requires a concerted
effort from industry giants, irrespective of their own internal research and
development investments.

Hardware security-focused benchmarks like the ones available on Trust Hub seek
to push research in the field. This online resource provides a few hundred
examples of board level Trojans (Harrison et al., 2021), chip level Trojans
(Salmani et al., 2012; Shakya et al., 2017) and obfuscation (Amir et al.,
2018) benchmarks. Without benchmark generation tools, the samples become
tedious to create. It is imperative that such tools are developed and made
open-source, especially for AI training and validation that require large
datasets. For this, Amir and Forte (Amir and Forte, 2020) propose a technique
that leverages linear optimization to generate synthetic combinational
benchmarks that are adaptable to user input constraints and structurally
different from input reference benchmarks. This can be viewed as a form of
data augmentation to increase variation of features seen by AI/ML/DL
algorithms, which should make them learn better and avoid overfitting.
Similarly, behavioral models of common analog circuits can act as benchmarks
for analog ICs which designers can easily evaluate and integrate security-
related constraints and metrics within those models.

####  5.1.2. Standardized Domain Knowledge

As the academic community needs vast amounts of data, researchers also needs
standardized domain knowledge. Domain knowledge helps standardize data
collection processes, so data collected from different labs is consistent. It
also guides researchers to identify relevant features for their specific
applications; such prior knowledge means more informed feature selection and
dimensionality reduction. Both allow practitioners to reduce the number of
features in a dataset by only focusing on important ones. The EDA pipeline
produces reports and tunable parameters that may be useful to a model. Without
that distinction, an ML model may not achieve its improved automation and
efficiency goals. The general benefits include requiring less data for high-
accuracy models, creating more robust models, and utilizing interpretable
features that help advance explainable AI (XAI) in EDA.

####  5.1.3. Open-source EDA Tools and PDKs

As this survey demonstrates, designing ICs requires many stages; IP cores must
be verified and tested for synthesis to different FPGA architectures and
various standard cell libraries. Tools like ones available on OpenCores.org
are suitable for less-complex demands, and foster collaboration among users.
However, they are not industry standard, hence they differ in functionality
from commercial tools provided by Synopsys, Cadence, and Xilinx. They are also
less-reliable and may have trouble scaling up to modern designs.

Some tools have been provided through extensive research within the academic
and industrial communities. The OpenROAD initiative seeks to reduce effort,
cost and time for hardware designs by providing 24-hour layout implementation
(Ajayi et al., 2019). Their GitHub repository also allows designers with
available PDKs to add to the ones available. Similarly, the ALIGN initiative
consists of a joint academic/industry team to develop open-source software for
analog/mixed-signal circuit layout to translate a netlist into a physical
layout, with 24-hour turnaround and no human in the loop (Kunal et al., 2019).
The development of more security-aware designs needs a similar effort from
interested parties. With the same emphasis on automation, AI/ML requires
working EDA tools to build from.

###  5.2. Advanced AI Techniques to Explore and Benefits

####  5.2.1. Transfer Learning (TL)

Transfer learning (TL) is built on the knowledge of previously-learned tasks;
the knowledge gained from solving one machine learning problem can be used to
address another one (see Fig. 19). The benefits of utilizing transfer learning
are faster training times, increased accuracy, and eliminating the need for
large amounts of data. Pan and Yang (Pan and Yang, 2010) use domain, task, and
marginal probabilities to describe transfer learning. Take a domain $D$, a
two-element tuple with feature space $\chi$ and marginal probability $P(X)$.
$X$ is a sample data point, and the entire domain is represented as

(1) $\displaystyle D=\\{\chi,P(X)\\}$

Now consider a task $T$, another two-element tuple of label space $\gamma$ and
predictive function $\eta$. The objective function can be denoted as
P($\gamma|$ X). Also, $Y$ is a corresponding label point for $X$. Therefore,

(2) $\displaystyle{T=\\{\gamma,P(Y|X)\\}=\\{\gamma,\eta\\}}$

A source domain can be represented as $D_{s}$, source task as $T_{s}$, target
domain as $D_{t}$, and target task as $T_{t}$. Hence, the aim of transfer
learning is to learn the target conditional probability function $\eta_{t}$ or
P($Y_{t}|X_{t}$) in $D_{t}$ with information gained from $D_{s}$ and $T_{s}$.

TL is ideal for applications within the IC design domain because general
design rules are used globally. Design libraries and technology nodes may
differ, but pre-trained deep learning models can be applied to various
optimization and security-aware problems. This is especially the case in
analog IP design where the lack of portability and re-usability across
different circuits, design stages, and technology nodes has acted as
impediments to the advancement of analog EDA tools. TL has become common in
the community for its ability to help train models and quickly deploy models
in applications where data is not readily available, as is often the case in
the hardware assurance domain.

Figure 19. High level description of transfer learning: the applied knowledge
from pre-training using Model 1 helps reduce data required for Model 2.

####  5.2.2. Federated Learning for Collaboration Without Hardware IP
Compromise

Federated learning (FL) or collaborative learning involves training an
algorithm in a decentralized manner across multiple edge devices or servers,
which each possess their own local data. FL, first coined by McMahan and
Ramage (McMahan and Ramage, 2017), combines machine learning with edge
computing for training (and data collection). Each endpoint, a low-powered
computation device, has a copy of the model, improves the model locally,
summarizes changes and sends the updates to the cloud where the global model
is updated, updates are then aggregated in the cloud and updates sent back to
edge devices. Li et al. summarize the problem as:

(3) $\min_{w}F(w),\text{ where }F(w)\coloneqq\sum_{k}^{N}p_{k}F_{k}(w)$

where, $N$ is the number of total devices, $p_{k}\in[0,1]$ and
$\sum_{k}p_{k}=1$; $F_{k}$ is the local objective function for the $k$th
device (Li et al., 2020c).

Ideally, FL allows for smarter models, reduced latency and power consumption,
all while securing privacy (McMahan and Ramage, 2017). Distributed data
resources also eliminates the need for a central massive data store.

A limiting factor for AI-based IC design is the confidentiality of IPs. Large
datasets are required from many existing AI-based design approaches as well as
updates over those designs to generate labels. However, companies and
governments are typically reluctant to share their IPs, which might include
proprietary algorithms, novel design techniques, or in-house countermeasures.
The lack of data stifles any one organization’s ability to build sufficient
datasets and robust models. For instance, a single company’s data might
provide a lot of data on a particular corner case or vulnerability but have
little or no data on others resulting in class imbalance. One solution to this
data sharing problem is differential privacy-based FL, which allows datasets
to be computed over at each edge-point without compromising IP. Note however
that for hardware security applications, this architecture may only be
meaningful for cases where the model provides benefits to ALL participating
organizations, such as piracy detection (Yasaei et al., 2021b) and security
rule checks (Xiao et al., 2016).

####  5.2.3. Explainable AI and Engineer Education

Explainable AI (XAI) is a field of AI concerned with making ML models
understandable by humans. For perspective, take an ANN and attempts to
understand the decisions it makes. ANNs are opaque (a.k.a., black-box)
predictors and their experimental performance is largely due to their large
parametric space, efficient learning algorithms and computation advances in
hardware. Transparent (a.k.a., white-box) models expose directly how the
model/mechanism works. Decision tree models (and other rule based models) are
largely considered an example of an easily interpretable model for both local
and global explanations. Other transparent models include $k$-Nearest
Neighbors, generative additive models and bayesian models (Barredo Arrieta et
al., 2020).

Due to their successes, ANNs are increasingly being deployed for high-stakes
decision-making. The opaque nature of ANNs raises critical issues because
without an understanding of how the mechanism is predicting, there is no way
of justifying the rationale behind any prediction. The complex latent
manifolds within which ANNs operate are difficult to visualize and reason
around. Further complicating things, explainability is defined not only by the
details and reasons behind its processes, but also the audience doing the
observing (Barredo Arrieta et al., 2020). Essentially, explanation methods are
intended to be a useful interface/translation between a complex model and a
stakeholder.

A variety of post-hoc methods that attempt to explain opaque predictors have
been proposed that can be broadly characterized into model-agnostic and model-
specific techniques. Explainers can be considered global (a.k.a., the model
explanation problem) or local (a.k.a., the prediction explanation problem).
Global explainers attempt to approximate the original model but also remain
understandable. Often global explanation approaches represent the final
explanation as a decision tree. Local explanations focus on creating
explanations for a particular input, i.e., for a given input, explain a
specific prediction. In the model-agnostic case, this often results in
explanations that quantify the contribution of each feature to the prediction.
However, explainers themselves tend to be fragile. As shown in Figure 20,
explanations can vary widely due to small changes in the input. Or more
problematically, they can be equivalent for very different predictions.

Figure 20. Examples illustrating how small perturbations in input do not
change predicitons, but create very different attribution maps. Reprinted from
(Ghorbani et al., 2019).

The landscape of explainable AI is still evolving and there is much work still
needed to be done. Explanation tooling can provide some guidance as to “where
the model is looking” but there is also a need for designing interpretable
models (Rudin, 2019).

In the semiconductor industry, many design engineers do not have the
experience and background to deal with hardware security issues. Even those
that do may have very specialized experience, e.g., experts in applied
cryptography but novices in supply chain security. Further, security is a
domain in constant state of flux with new attack vectors popping up each year.
Explainable AI is an important research area and could provide feedback to
organizations and help them train or re-train their design engineers to keep
up with new attacks and vulnerabilities. The lessons learned from explainable
AI both in its limitations and possibilities can provide useful insight to the
appropriate application, or more importantly interpretation, of ML models in
security applications.

##  6\. Conclusion

In this survey, we summarized the state-of-the-art AI/ ML-based EDA
techniques, their contemporary and potential use in security-aware design and
provide a general perspective on needs and requirements for an automated
security-aware IC design process. Our literature review showed that ML/AI is
remarkably suitable for tuning the design to incorporate security constraints
without deteriorating performance, develop reliable and robust security
primitives to tackle supply chain related vulnerabilities, and make the
designs more resilient against both invasive and non-invasive, side-channel,
and fault-injection attacks. In that regard, we have extensively covered the
intersection between learning and design with the objective of protecting
electronic systems against malicious parties, whether it be by AI-based
integration of multiple primitives and protections, guidance and optimization
of design tradeoffs, or real-time feedback/training for users. We also
discussed problems and solutions within this domain, such as scarcity of data,
confidentiality, and open-source tools, and highlighted opportunities that
will make the AI-based design more formidable and help solidify hardware as
the root-of-trust for industry and government.

## References

  * (1)
  * els (2009) 2009\.  https://booksite.elsevier.com/samplechapters/9780750678667/Sample_Chapter.pdf
  * IHS (2012) 2012\.  Top 5 Most Counterfeited Parts Represent a 169 Billion Potential Challenge for Global Semiconductor Market.  https://technology.ihs.com/405654/top-5-most-counterfeited-parts-represent-a-169-billion-potential-challenge-for-global-semiconductor-market
  * Bar (2019) 2019\.  Machine learning-based pre-routing timing prediction with reduced pessimism.  _Proceedings - Design Automation Conference_.  https://doi.org/10.1145/3316781.3317857
  * Abadi et al. (2015) Martín Abadi, Ashish Agarwal, Paul Barham, Eugene Brevdo, Zhifeng Chen, Craig Citro, Greg S. Corrado, Andy Davis, Jeffrey Dean, Matthieu Devin, Sanjay Ghemawat, Ian Goodfellow, Andrew Harp, Geoffrey Irving, Michael Isard, Yangqing Jia, Rafal Jozefowicz, Lukasz Kaiser, Manjunath Kudlur, Josh Levenberg, Dandelion Mané, Rajat Monga, Sherry Moore, Derek Murray, Chris Olah, Mike Schuster, Jonathon Shlens, Benoit Steiner, Ilya Sutskever, Kunal Talwar, Paul Tucker, Vincent Vanhoucke, Vijay Vasudevan, Fernanda Viégas, Oriol Vinyals, Pete Warden, Martin Wattenberg, Martin Wicke, Yuan Yu, and Xiaoqiang Zheng. 2015\.  TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems.  https://www.tensorflow.org/ Software available from tensorflow.org.
  * Acharya et al. (2020) Rabin Yu Acharya, Sreeja Chowdhury, Fatemeh Ganji, and Domenic Forte. 2020.  Attack of the genes: Finding keys and parameters of locked analog ICs using genetic algorithm. In _2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)_. IEEE, 284–294.
  * Acharya et al. (2021) Rabin Yu Acharya, Michael Valentin Levin, and Domenic Forte. 2021.  LDO-based Odometer to Combat IC Recycling. In _2021 IEEE 34th International System-on-Chip Conference (SOCC)_. IEEE, 206–211.
  * Ahmadi et al. (2016) Ali Ahmadi, Mohammad-Mahdi Bidmeshki, Amit Nahar, Bob Orr, Michael Pas, and Yiorgos Makris. 2016\.  A machine learning approach to fab-of-origin attestation. In _Proceedings of the 35th International Conference on Computer-Aided Design_. 1–6.
  * Ajayi et al. (2019) T Ajayi, D Blaauw, TB Chan, CK Cheng, VA Chhabria, DK Choo, M Coltella, S Dobre, R Dreslinski, M Fogaça, et al. 2019\.  OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain.  _Proc. GOMACTECH_ (2019), 1105–1110.
  * Alam et al. (2018) Md Mahbub Alam, Sreeja Chowdhury, Beomsoo Park, David Munzer, Nima Maghari, Mark Tehranipoor, and Domenic Forte. 2018.  Challenges and opportunities in analog and mixed signal (AMS) integrated circuit (IC) security.  _Journal of Hardware and Systems Security_ 2, 1 (2018), 15–32.
  * Alam et al. (2019) Md Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark Tehranipoor, and Domenic Forte. 2019.  RAM-Jam: Remote temperature and voltage fault attack on FPGAs using memory collisions. In _2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)_. IEEE, 48–55.
  * Alaql and Bhunia (2021) Abdulrahman Alaql and Swarup Bhunia. 2021.  SARO: Scalable Attack-Resistant Logic Locking.  _IEEE Transactions on Information Forensics and Security_ 16 (2021), 3724–3739.
  * Alaql et al. (2021) Abdulrahman Alaql, Saranyu Chattopadhyay, Prabuddha Chakraborty, Tamzidul Hoque, and Swarup Bhunia. 2021\.  LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ (2021), 1–1.  https://doi.org/10.1109/TCAD.2021.3075939
  * Alkabani and Koushanfar (2007) Yousra Alkabani and Farinaz Koushanfar. 2007.  Active Hardware Metering for Intellectual Property Protection and Security.. In _USENIX security symposium_ , Vol. 20. 1–20.
  * ALPAYDIN (2020) ETHEM ALPAYDIN. 2020\.  _Introduction to machine learning_.  MIT Press.
  * Alsaiari and Gebali (2019) Uthman Alsaiari and Fayez Gebali. 2019.  Hardware Trojan Detection Using Reconfigurable Assertion Checkers.  _IEEE Transactions on Very Large Scale Integration (VLSI) Systems_ 27, 7 (2019), 1575–1586.  https://doi.org/10.1109/TVLSI.2019.2908964
  * Alvarez et al. (2015) Anastacia Alvarez, Wenfeng Zhao, and Massimo Alioto. 2015\.  14.3 15fJ/b static physically unclonable functions for secure chip identification with¡ 2% native bit instability and 140$\times$ Inter/Intra PUF hamming distance separation in 65nm. In _2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers_. IEEE, 1–3.
  * Amir and Forte (2020) Sarah Amir and Domenic Forte. 2020.  Adaptable and divergent synthetic benchmark generation for hardware security. In _Proceedings of the 39th International Conference on Computer-Aided Design_. 1–9.
  * Amir et al. (2018) Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark Tehranipoor, and Domenic Forte. 2018.  Development and evaluation of hardware obfuscation benchmarks.  _Journal of Hardware and Systems Security_ 2, 2 (2018), 142–161.
  * Ardeshiricham et al. (2017) Armaiti Ardeshiricham, Wei Hu, Joshua Marxen, and Ryan Kastner. 2017\.  Register transfer level information flow tracking for provably secure hardware design. In _Design, Automation Test in Europe Conference Exhibition (DATE), 2017_. 1691–1696.  https://doi.org/10.23919/DATE.2017.7927266
  * Arribas et al. (2018) Victor Arribas, Svetla Nikova, and Vincent Rijmen. 2018\.  VerMI: Verification tool for masked implementations. In _2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)_. IEEE, 381–384.
  * Babighian et al. (2004) Pietro Babighian, Luca Benini, Alberto Macii, and Enrico Macii. 2004.  Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion. In _Proceedings of the 2004 International Symposium on Low Power Electronics and Design_ (Newport Beach, California, USA) _(ISLPED ’04)_. Association for Computing Machinery, New York, NY, USA, 138–143.  https://doi.org/10.1145/1013235.1013275
  * Bagnato et al. (2014) Alessandra Bagnato, Leandro Soares Indrusiak, Imran Rafiq Quadri, and Matteo Rossi. 2014\.  _Handbook of Research on Embedded Systems Design_.  Information Science Reference.
  * Bandeira et al. (2020) Vitor Bandeira, Mateus Fogaça, Eder Matheus Monteiro, Isadora Oliveira, Mingyu Woo, and Ricardo Reis. 2020.  Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching. In _2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)_. 74–77.  https://doi.org/10.1109/NEWCAS49341.2020.9159791
  * Bar-El et al. (2006) Hagai Bar-El, Hamid Choukri, David Naccache, Michael Tunstall, and Claire Whelan. 2006\.  The sorcerer’s apprentice guide to fault attacks.  _Proc. IEEE_ 94, 2 (2006), 370–382.
  * Barredo Arrieta et al. (2020) Alejandro Barredo Arrieta, Natalia Díaz-Rodríguez, Javier Del Ser, Adrien Bennetot, Siham Tabik, Alberto Barbado, Salvador Garcia, Sergio Gil-Lopez, Daniel Molina, Richard Benjamins, Raja Chatila, and Francisco Herrera. 2020.  Explainable Artificial Intelligence (XAI): Concepts, taxonomies, opportunities and challenges toward responsible AI.  _Inf. Fusion_ 58 (June 2020), 82–115.  https://doi.org/10.1016/j.inffus.2019.12.012
  * Barthe et al. (2015) Gilles Barthe, Sonia Belaïd, François Dupressoir, Pierre-Alain Fouque, Benjamin Grégoire, and Pierre-Yves Strub. 2015\.  Verified proofs of higher-order masking. In _Annual International Conference on the Theory and Applications of Cryptographic Techniques_. Springer, 457–485.
  * Bayern et al. (2019) Macy Bayern, Bill Detwiler, TechRepublic Academy, Erik Eckel, and Jack Wallen. 2019\.  63$\%$ of organizations face security breaches due to hardware vulnerabilities.  https://www.techrepublic.com/article/63-of-organizations-face-security-breaches-due-to-hardware-vulnerabilities/
  * Bertoni et al. (2017) Guido Bertoni, Marco Martinoli, and Maria Chiara Molteni. 2017\.  A methodology for the characterisation of leakages in combinatorial logic.  _Journal of Hardware and Systems Security_ 1, 3 (2017), 269–281.
  * Bhandari et al. (2021) Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, and Ramesh Karri. 2021.  Exploring eFPGA-based Redaction for IP Protection. In _2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)_. 1–9.  https://doi.org/10.1109/ICCAD51958.2021.9643548
  * Bhatia et al. (2016) Veepsa Bhatia, Neeta Pandey, and Asok Bhattacharyya. 2016\.  Modelling and Design of Inverter Threshold Quantization Based Current Comparator using Artificial Neural Networks.  _International Journal of Electrical & Computer Engineering (2088-8708)_ 6, 1 (2016).
  * Binu and Kariyappa (2018) D Binu and BS Kariyappa. 2018.  RideNN: A new rider optimization algorithm-based neural network for fault diagnosis in analog circuits.  _IEEE Transactions on Instrumentation and Measurement_ 68, 1 (2018), 2–26.
  * Bloem et al. (2018) Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, and Johannes Winter. 2018.  Formal verification of masked hardware implementations in the presence of glitches. In _Annual International Conference on the Theory and Applications of Cryptographic Techniques_. Springer, 321–353.
  * Bogaerts (2014) J. Bogaerts. 2014\.  9 - Complementary metal-oxide-semiconductor (CMOS) image sensors for use in space.  In _High Performance Silicon Imaging_ , Daniel Durini (Ed.). Woodhead Publishing, 250–280.  https://doi.org/10.1533/9780857097521.2.250
  * Brayton et al. (1990) R.K. Brayton, G.D. Hachtel, and A.L. Sangiovanni-Vincentelli. 1990\.  Multilevel logic synthesis.  _Proc. IEEE_ 78, 2 (1990), 264–300.  https://doi.org/10.1109/5.52213
  * Bronstein et al. (2017) Michael M Bronstein, Joan Bruna, Yann LeCun, Arthur Szlam, and Pierre Vandergheynst. 2017.  Geometric Deep Learning: Going beyond Euclidean data.  _IEEE Signal Process. Mag._ 34, 4 (July 2017), 18–42.  https://doi.org/10.1109/MSP.2017.2693418
  * Buhan et al. (2021) Ileana Buhan, Lejla Batina, Yuval Yarom, and Patrick Schaumont. 2021.  SoK: Design Tools for Side-Channel-Aware Implementations.  arXiv:2104.08593 [cs.CR]
  * Bushnell and Agrawal (2004) Michael Bushnell and Vishwani Agrawal. 2004.  _Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits_. Vol. 17.  Springer Science & Business Media.
  * Cardoso et al. (2017) João M.P. Cardoso, José Gabriel F. Coutinho, and Pedro C. Diniz. 2017\.  Chapter 4 - Source code analysis and instrumentation.  In _Embedded Computing for High Performance_ , João M.P. Cardoso, José Gabriel F. Coutinho, and Pedro C. Diniz (Eds.). Morgan Kaufmann, Boston, 99–135.  https://doi.org/10.1016/B978-0-12-804189-5.00004-1
  * Cassel and Lima (2006) M. Cassel and F. Lima. 2006\.  Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs. In _12th IEEE International On-Line Testing Symposium (IOLTS’06)_. 6 pp.–.  https://doi.org/10.1109/IOLTS.2006.32
  * Casto (2018) Matthew James Casto. 2018\.  _Multi-Attribute Design for Authentication and Reliability (MADAR)_.  Ph.D. Dissertation. The Ohio State University.
  * Chakraborty et al. (2018) Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia. 2018\.  SAIL: Machine learning guided structural analysis attack on hardware obfuscation. In _2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)_. IEEE, 56–61.
  * Chakraborty and Bhunia (2009) Rajat Subhra Chakraborty and Swarup Bhunia. 2009.  HARPOON: An obfuscation-based SoC design methodology for hardware protection.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 28, 10 (2009), 1493–1502.
  * Chakraborty and Bhunia (2010) Rajat Subhra Chakraborty and Swarup Bhunia. 2010.  RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. In _2010 23rd International Conference on VLSI Design_. 405–410.  https://doi.org/10.1109/VLSI.Design.2010.54
  * Chang et al. (2016) Chip-Hong Chang, Miodrag Potkonjak, and Li Zhang. 2016\.  _Hardware IP Watermarking and Fingerprinting_.  Springer International Publishing, Cham, 329–368.  https://doi.org/10.1007/978-3-319-14971-4_10
  * Chang et al. (2014) Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, and Ramesh Karri. 2014.  Approximating the age of RF/analog circuits through re-characterization and statistical estimation. In _2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)_. IEEE, 1–4.
  * Chang et al. (2006) Po-Hao Chang, Jia-Ming Chen, and Chao-Ying Shen. 2006\.  On an Efficient Closed Form Expression to Estimate the Crosstalk Noise in the Circuit with Multiple Wires. In _APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems_. 1329–1332.  https://doi.org/10.1109/APCCAS.2006.342429
  * Chen et al. (2019) Huili Chen, Cheng Fu, Jishen Zhao, and Farinaz Koushanfar. 2019\.  GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic Encryption. In _2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. 1–8.  https://doi.org/10.1109/ICCAD45719.2019.8942134
  * Chen et al. (2020b) Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, and David Z Pan. 2020b.  MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII.  _IEEE Design & Test_ 38, 2 (2020), 19–26.
  * Chen et al. (2020a) Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj P.D., Houman Homayoun, and Liang Zhao. 2020a.  Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning. In _2020 Design, Automation Test in Europe Conference Exhibition (DATE)_. 358–363.  https://doi.org/10.23919/DATE48585.2020.9116544
  * Chen et al. (2017) Zaichen Chen, Maxim Raginsky, and Elyse Rosenbaum. 2017\.  Verilog-A compatible recurrent neural network model for transient circuit simulation. In _2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)_. IEEE, 1–3.
  * Chow et al. (2012) Lap Wai Chow, James P Baukus, Bryan J Wang, and Ronald P Cocchi. 2012.  Camouflaging a standard cell based integrated circuit.  US Patent 8,151,235.
  * Chowdhury et al. (2020a) Sreeja Chowdhury, Rabin Acharya, William Boullion, Andrew Felder, Mark Howard, Jia Di, and Domenic Forte. 2020a.  A weak asynchronous reset (ares) puf using start-up characteristics of null conventional logic gates. In _2020 IEEE International Test Conference (ITC)_. IEEE, 1–10.
  * Chowdhury et al. (2020b) Sreeja Chowdhury, Fatehmeh Ganji, and Domenic Forte. 2020b.  Low-cost remarked counterfeit IC detection using LDO regulators. In _2020 IEEE International Symposium on Circuits and Systems (ISCAS)_. IEEE, 1–5.
  * Chowdhury et al. (2020c) Sreeja Chowdhury, Fatemeh Ganji, and Domenic Forte. 2020c.  Recycled SoC Detection Using LDO Degradation.  _SN Computer Science_ 1, 6 (2020), 1–21.
  * Cong and Pan (2008) Jason Cong and Peichen Pan. 2008.  Chapter 13 - Technology Mapping.  In _Reconfigurable Computing_ , Scott Hauck and André Dehon (Eds.). Morgan Kaufmann, Burlington, 277–296.  https://doi.org/10.1016/B978-012370522-8.50019-4
  * Connor (2018) Katherine Connor. 2018\.  UC San Diego selected to lead development of open-source tools for hardware design automation.  https://ucsdnews.ucsd.edu/pressrelease/uc_san_diego_selected_to_lead_development_of_open_source_tools_for_hardware_design_automation
  * Contreras et al. (2013) Gustavo K. Contreras, Md. Tauhidur Rahman, and Mohammad Tehranipoor. 2013.  Secure Split-Test for preventing IC piracy by untrusted foundry and assembly. In _2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)_. 196–203.  https://doi.org/10.1109/DFT.2013.6653606
  * Cornforth and Lipson (2014) Theodore W Cornforth and Hod Lipson. 2014.  Reverse-Engineering Nonlinear Analog Circuits with Evolutionary Computation. In _International Conference on Unconventional Computation and Natural Computation_. Springer, 105–116.
  * Coron (2018) Jean-Sébastien Coron. 2018\.  Formal verification of side-channel countermeasures via elementary circuit transformations. In _International Conference on Applied Cryptography and Network Security_. Springer, 65–82.
  * Cruz et al. (2018) Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra. 2018.  Hardware Trojan Detection Using ATPG and Model Checking. In _2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)_. 91–96.  https://doi.org/10.1109/VLSID.2018.43
  *<EMAIL_ADDRESS>(2022<EMAIL_ADDRESS>2022\.  HW CWE SIG.  https://cwe.mitre.org/documents/HW_CWE_SIG.pdf.
  * Dai et al. (2018) Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F.Y. Young, and Zhiru Zhang. 2018.  Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning.  _Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018_ , 129–132.  https://doi.org/10.1109/FCCM.2018.00029
  * Das and Vemuri (2007) Angan Das and Ranga Vemuri. 2007.  An automated passive analog circuit synthesis framework using genetic algorithms. In _IEEE computer society annual symposium on VLSI (ISVLSI’07)_. IEEE, 145–152.
  * De Meyer et al. (2018) Lauren De Meyer, Victor Arribas Abril, Svetla Nikova, Ventzislav Nikov, and Vincent Rijmen. 2018\.  M&m: Masks and macs against physical attacks.  _IACR Transactions on Cryptographic Hardware and Embedded Systems_ 2019, 1 (2018), 25–50.
  * Ding et al. (2011) Duo Ding, Jhih-Rong Gao, Kun Yuan, and David Z Pan. 2011\.  AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. In _Proceedings of the 48th Design Automation Conference_. 795–800.
  * Ding and Vemur (2005) Mengmeng Ding and RI Vemur. 2005.  An active learning scheme using support vector machines for analog circuit feasibility classification. In _18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design_. IEEE, 528–534.
  * Docking and Sachdev (2003) S. Docking and M. Sachdev. 2003.  A method to derive an equation for the oscillation frequency of a ring oscillator.  _IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications_ 50, 2 (2003), 259–264.  https://doi.org/10.1109/TCSI.2002.808235
  * Dumesnil et al. (2014) Etienne Dumesnil, Frederic Nabki, and Mounir Boukadoum. 2014\.  RF-LNA circuit synthesis by genetic algorithm-specified artificial neural network. In _2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)_. IEEE, 758–761.
  * Dumesnil et al. (2015) Etienne Dumesnil, Frederic Nabki, and Mounir Boukadoum. 2015\.  RF-LNA circuit synthesis using an array of artificial neural networks with constrained inputs. In _2015 IEEE International Symposium on Circuits and Systems (ISCAS)_. IEEE, 573–576.
  * Dunbar and Qu (2015) Carson Dunbar and Gang Qu. 2015.  Satisfiability Don’t Care condition based circuit fingerprinting techniques.  _The 20th Asia and South Pacific Design Automation Conference_ (2015), 815–820.
  * Education ([n.d.]) By: IBM Cloud Education. [n.d.].  What is deep learning?  https://www.ibm.com/cloud/learn/deep-learning
  * El Massad et al. (2015) Mohamed El Massad, Siddharth Garg, and Mahesh V Tripunitara. 2015.  Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes.. In _NDSS_. 1–14.
  * Elshamy et al. (2020) Mohamed Elshamy, Giorgio Di Natale, Antonios Pavlidis, Marie-Minerve Louërat, and Haralampos-G Stratigopoulos. 2020\.  Hardware trojan attacks in analog/mixed-signal ICs via the test access mechanism. In _2020 IEEE European Test Symposium (ETS)_. IEEE, 1–6.
  * Fogaça et al. (2019) Mateus Fogaça, Andrew B Kahng, Ricardo Reis, and Lutong Wang. 2019.  Finding placement-relevant clusters with fast modularity-based clustering. In _Proceedings of the 24th Asia and South Pacific Design Automation Conference_. 569–576.
  * Froemmer et al. (2020) Jens Froemmer, Yara Gowayed, Nico Bannow, Wolfgang Kunz, Christoph Grimm, and Klaus Schneider. 2020\.  Area Estimation Framework for Digital Hardware Design using Machine Learning. In _MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop_. 1–10.
  * Fung (2022) Jason Fung. 2022\.  7 essentials for more security-aware design automation.  https://www.darkreading.com/vulnerabilities-threats/7-essentials-for-more-security-aware-design-automation.
  * Gabriel et al. (2010) Christian Gabriel, Christoffer Wittmann, Denis Sych, Ruifang Dong, Wolfgang Mauerer, Ulrik L. Andersen, Christoph Marquardt, and Gerd Leuchs. 2010.  A generator for unique quantum random numbers based on vacuum states.  _Nature Photonics_ 4, 10 (2010), 711–715.  https://doi.org/10.1038/nphoton.2010.197
  * Gao et al. ([n.d.]) Minyan Gao, Huanyu Wang, Mark M. Tehranipoor, and Domenic Forte. [n.d.].  iPROBE V2: Internal Shielding-based Countermeasures against Both Back-side and Front-side Probing Attacks.  _SRC TECHCON_ ([n. d.]).  https://par.nsf.gov/biblio/10174121
  * Gao et al. (2019) Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, and Xuan Zeng. 2019\.  Efficient performance trade-off modeling for analog circuit based on Bayesian neural network. In _2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. IEEE, 1–8.
  * Gassend et al. (2002) Blaise Gassend, Dwaine Clarke, Marten Van Dijk, and Srinivas Devadas. 2002.  Silicon physical random functions. In _Proceedings of the 9th ACM Conference on Computer and Communications Security_. 148–160.
  * Ghorbani et al. (2019) Amirata Ghorbani, Abubakar Abid, and James Zou. 2019.  Interpretation of Neural Networks Is Fragile.  _AAAI_ 33, 01 (July 2019), 3681–3688.  https://doi.org/10.1609/aaai.v33i01.33013681
  * Gielen and Rutenbar (2000) Georges GE Gielen and Rob A Rutenbar. 2000.  Computer-aided design of analog and mixed-signal integrated circuits.  _Proc. IEEE_ 88, 12 (2000), 1825–1854.
  * Giraud and Thillard (2010) Christophe Giraud and Adrian Thillard. 2010.  Piret and Quisquater’s DFA on AES Revisited.  _IACR Cryptology ePrint Archive_ 2010 (01 2010), 440\.
  * Goldie and Mirhoseini (2020) Anna Goldie and Azalia Mirhoseini. 2020.  Placement optimization with deep reinforcement learning. In _Proceedings of the 2020 International Symposium on Physical Design_. 3–7.
  * Grabmann et al. (2019) Martin Grabmann, Frank Feldhoff, and Georg Gläser. 2019\.  Power to the model: Generating energy-aware mixed-signal models using machine learning. In _2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 5–8.
  * Green (1999) L. Green. 1999.  Understanding the importance of signal integrity.  _IEEE Circuits and Devices Magazine_ 15, 6 (1999), 7–10.  https://doi.org/10.1109/101.808850
  * Guan et al. (2020) Zhibin Guan, Xiaomeng Wang, Wei Xin, Jiajie Wang, and Li Zhang. 2020.  A survey on deep learning-based source code defect analysis. In _2020 5th International Conference on Computer and Communication Systems (ICCCS)_. IEEE, 167–171.
  * Guerra et al. (2019) Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, and Ricardo Martins. 2019.  Artificial neural networks as an alternative for automatic analog IC placement. In _2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 1–4.
  * Guin et al. (2015) Ujjwal Guin, Domenic Forte, and Mark Tehranipoor. 2015\.  Design of accurate low-cost on-chip structures for protecting integrated circuits against recycling.  _IEEE Transactions on Very Large Scale Integration (VLSI) Systems_ 24, 4 (2015), 1233–1246.
  * Guin et al. (2014) Ujjwal Guin, Xuehui Zhang, Domenic Forte, and Mohammad Tehranipoor. 2014.  Low-cost on-chip structures for combating die and IC recycling. In _2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)_. 1–6.  https://doi.org/10.1145/2593069.2593157
  * GummidipoondiJayasankaran et al. (2020) Nithyashankari GummidipoondiJayasankaran, Adriana Sanabria Borbon, Edgar Sanchez Sinencio, Jiang Hu, and Jeyavijayan Rajendran. 2020.  Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.  _IEEE Transactions on Emerging Topics in Computing_ (2020).
  * Gusmão et al. (2020) António Gusmão, Fábio Passos, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, and Ricardo Martins. 2020.  Semi-supervised artificial neural networks towards analog IC placement recommender. In _2020 IEEE International Symposium on Circuits and Systems (ISCAS)_. IEEE, 1–5.
  * Haaswijk et al. (2018) Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan, Sabine Süsstrunk, and Giovanni De Micheli. 2018\.  Deep Learning for Logic Optimization Algorithms. In _2018 IEEE International Symposium on Circuits and Systems (ISCAS)_. 1–4.  https://doi.org/10.1109/ISCAS.2018.8351885
  * Hakhamaneshi et al. (2019) Kourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, and Vladimir Stojanović. 2019.  BagNet: Berkeley analog generator with layout optimizer boosted with deep neural networks. In _2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. IEEE, 1–8.
  * Hamilton (2020) William L Hamilton. 2020\.  Graph Representation Learning.  _Synthesis Lectures on Artificial Intelligence and Machine Learning_ 14, 3 (Sept. 2020), 1–159.  https://doi.org/10.2200/S01045ED1V01Y202009AIM046
  * Han et al. (2020) Kwangsoo Han, Andrew B. Kahng, and Jiajia Li. 2020.  Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 39 (2020), 478–491.
  * Hanna and Cabric (2019) Samer S Hanna and Danijela Cabric. 2019.  Deep learning based transmitter identification using power amplifier nonlinearity. In _2019 International Conference on Computing, Networking and Communications (ICNC)_. IEEE, 674–680.
  * Harrison et al. (2021) Jacob Harrison, Navid Asadizanjani, and Mark Tehranipoor. 2021\.  On malicious implants in PCBs throughout the supply chain.  _Integration_ 79 (2021), 12–22.  https://doi.org/10.1016/j.vlsi.2021.03.002
  * Harsha and Harish (2018) MV Harsha and BP Harish. 2018.  An integrated maxFit genetic algorithm-SPICE framework for 2-Stage Op-Amp design automation. In _2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)_. IEEE, 170–174.
  * Hart et al. (1968) Peter E Hart, Nils J Nilsson, and Bertram Raphael. 1968\.  A formal basis for the heuristic determination of minimum cost paths.  _IEEE transactions on Systems Science and Cybernetics_ 4, 2 (1968), 100–107.
  * Hasani et al. (2017) Ramin M Hasani, Dieter Haerle, Christian F Baumgartner, Alessio R Lomuscio, and Radu Grosu. 2017\.  Compositional neural-network modeling of complex analog circuits. In _2017 International Joint Conference on Neural Networks (IJCNN)_. IEEE, 2235–2242.
  * Herder et al. (2014) Charles Herder, Meng-Day Yu, Farinaz Koushanfar, and Srinivas Devadas. 2014.  Physical Unclonable Functions and Applications: A Tutorial.  _Proc. IEEE_ 102, 8 (2014), 1126–1141.  https://doi.org/10.1109/JPROC.2014.2320516
  * Hiller et al. (2020) Matthias Hiller, Ludwig Kürzinger, and Georg Sigl. 2020\.  Review of error correction for PUFs and evaluation on state-of-the-art FPGAs.  _Journal of Cryptographic Engineering_ 10, 3 (2020), 229–247.
  * Hsiao (2006) Michael S. Hsiao. 2006\.  Chapter 4 - Test Generation.  In _VLSI Test Principles and Architectures_ , Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen (Eds.). Morgan Kaufmann, San Francisco, 161–262.  https://doi.org/10.1016/B978-012370597-6/50008-1
  * Hu et al. (2021) Wei Hu, Armaiti Ardeshiricham, and Ryan Kastner. 2021\.  Hardware Information Flow Tracking.  _ACM Comput. Surv._ 54, 4, Article 83 (may 2021), 39 pages.  https://doi.org/10.1145/3447867
  * Huang et al. (2021a) Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, et al. 2021a.  Machine learning for electronic design automation: A survey.  _ACM Transactions on Design Automation of Electronic Systems (TODAES)_ 26, 5 (2021), 1–46.
  * Huang et al. (2021b) Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng. 2021b.  Bayesian Optimization Approach for Analog Circuit Design Using Multi-task Gaussian Process. In _2021 IEEE International Symposium on Circuits and Systems (ISCAS)_. IEEE, 1–5.
  * Huang et al. (2012) Ke Huang, John M Carulli, and Yiorgos Makris. 2012.  Parametric counterfeit IC detection via support vector machines. In _2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)_. IEEE, 7–12.
  * Huss et al. (2013) Sorin A Huss, Marc Stöttinger, and Michael Zohner. 2013\.  Amasive: an adaptable and modular autonomous side-channel vulnerability evaluation framework.  In _Number theory and cryptography_. Springer, 151–165.
  * Imeson et al. (2013) Frank Imeson, Ariq Emtenan, Siddharth Garg, and Mahesh Tripunitara. 2013.  Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation. In _22nd USENIX Security Symposium (USENIX Security 13)_. 495–510.
  * İslamoğlu et al. (2019) Gamze İslamoğlu, Tuğberk Oğulcan Çakici, Engin Afacan, and Günhan Dündar. 2019.  Artificial neural network assisted analog IC sizing tool. In _2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 9–12.
  * Jafari et al. (2010) Ali Jafari, Saeed Sadri, and Maryam Zekri. 2010.  Design optimization of analog integrated circuits by using artificial neural networks. In _2010 international conference of soft computing and pattern recognition_. IEEE, 385–388.
  * Jayasankaran et al. (2019a) Nithyashankari Gummidipoondi Jayasankaran, A Sanabria Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, and Jeyavijayan Rajendran. 2019a.  Breaking analog locking techniques via satisfiability modulo theories. In _2019 IEEE International Test Conference (ITC)_. IEEE, 1–10.
  * Jayasankaran et al. (2019b) N. G. Jayasankaran, A. Sanabria Borbon, A. Abuellil, E. Sánchez-Sinencio, J. Hu, and J. Rajendran. 2019b.  Breaking Analog Locking Techniques via Satisfiability Modulo Theories. In _2019 IEEE International Test Conference (ITC)_. 1–10.  https://doi.org/10.1109/ITC44170.2019.9000113
  * Jenihhin ([n.d.]) Maksim Jenihhin. [n.d.].  https://pld.ttu.ee/~maksim/benchmarks/
  * Jiang and Devadas (2009) Jie-Hong (Roland) Jiang and Srinivas Devadas. 2009.  CHAPTER 6 - Logic synthesis in a nutshell.  In _Electronic Design Automation_ , Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting (Tim) Cheng (Eds.). Morgan Kaufmann, Boston, 299–404.  https://doi.org/10.1016/B978-0-12-374364-0.50013-8
  * Jiang et al. (2018) Zhenghong Jiang, Steve Dai, G. Edward Suh, and Zhiru Zhang. 2018\.  High-Level Synthesis with Timing-Sensitive Information Flow Enforcement. In _2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. 1–8.  https://doi.org/10.1145/3240765.3240813
  * Jin et al. (2020) Sunghyun Jin, Suhri Kim, HeeSeok Kim, and Seokhie Hong. 2020\.  Recent advances in deep learning-based side-channel analysis.  _ETRI Journal_ 42, 2 (2020), 292–304.
  * Kahng et al. ([n.d.]) Andrew B Kahng, Ravi Varadarajan, and Zhiang Wang. [n.d.].  RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement.
  * Karpovsky and Taubin (2004) Mark Karpovsky and Alexander Taubin. 2004.  New class of nonlinear systematic error detecting codes.  _IEEE Transactions on Information Theory_ 50, 8 (2004), 1818–1819.
  * Kaya et al. (2018) Ezgi Kaya, Engin Afacan, and Gunhan Dundar. 2018.  An analog/RF circuit synthesis and design assistant tool for analog IP: DATA-IP. In _2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 1–9.
  * Keating and Bricaud (2007) Michael Keating and Pierre Bricaud. 2007.  _Reuse methodology manual: For system-on-a-chip designs_.  Springer.
  * Khwaja (1997) Amir A. Khwaja. 1997\.  Enhancing Extensibility of the Design Rule Checker of an EDA Tool by Object-Oriented Modeling. In _Proceedings of the 21st International Computer Software and Applications Conference_ _(COMPSAC ’97)_. IEEE Computer Society, USA, 104–108.
  * Kim et al. (2019) Jaehun Kim, Stjepan Picek, Annelie Heuser, Shivam Bhasin, and Alan Hanjalic. 2019.  Make Some Noise. Unleashing the Power of Convolutional Neural Networks for Profiled Side-channel Analysis.  _IACR Trans. on Cryptographic Hardware and Embedded Systems_ (2019), 148–179.
  * Kim et al. (2020) Minsu Kim, Hyunwook Park, Seongguk Kim, Keeyoung Son, Subin Kim, Kyunjune Son, Seonguk Choi, Gapyeol Park, and Joungho Kim. 2020.  Reinforcement learning-based auto-router considering signal integrity. In _2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)_. IEEE, 1–3.
  * Kison et al. (2019) Christian Kison, Omar Mohamed Awad, Marc Fyrbiak, and Christof Paar. 2019.  Security implications of intentional capacitive crosstalk.  _IEEE Transactions on Information Forensics and Security_ 14, 12 (2019), 3246–3258.
  * Kocher et al. (2019) Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, et al. 2019\.  Spectre attacks: Exploiting speculative execution. In _2019 IEEE Symposium on Security and Privacy (SP)_. IEEE, 1–19.
  * Konigsmark et al. (2017) S.T. Choden Konigsmark, Deming Chen, and Martin D.F. Wong. 2017\.  High-Level Synthesis for side-channel defense. In _2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)_. 37–44.  https://doi.org/10.1109/ASAP.2017.7995257
  * Krachenfels et al. (2021) Thilo Krachenfels, Tuba Kiyan, Shahin Tajik, and Jean-Pierre Seifert. 2021.  Automatic Extraction of Secrets from the Transistor Jungle using Laser-Assisted Side-Channel Attacks. In _30th USENIX Security Symposium (USENIX Security 21)_. 627–644.
  * Kumar and Burleson (2014) Raghavan Kumar and Wayne Burleson. 2014.  On design of a highly secure PUF based on non-linear current mirrors. In _2014 IEEE international symposium on hardware-oriented security and trust (HOST)_. IEEE, 38–43.
  * Kunal et al. (2019) Kishor Kunal, Meghna Madhusudan, Arvind K Sharma, Wenbin Xu, Steven M Burns, Ramesh Harjani, Jiang Hu, Desmond A Kirkpatrick, and Sachin S Sapatnekar. 2019.  ALIGN: Open-source analog layout automation from the ground up. In _Proceedings of the 56th Annual Design Automation Conference 2019_. 1–4.
  * Kunal et al. (2020) Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, and Sachin S Sapatnekar. 2020.  A general approach for identifying hierarchical symmetry constraints for analog circuit layout. In _2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)_. IEEE, 1–8.
  * Lecun et al. (2015) Yann Lecun, Yoshua Bengio, and Geoffrey Hinton. 2015\.  Deep learning.  _Nature Cell Biology_ 521, 7553 (27 May 2015), 436–444.  https://doi.org/10.1038/nature14539 Funding Information: Acknowledgements The authors would like to thank the Natural Sciences and Engineering Research Council of Canada, the Canadian Institute For Advanced Research (CIFAR), the National Science Foundation and Office of Naval Research for support. Y.L. and Y.B. are CIFAR fellows. Publisher Copyright: © 2015 Macmillan Publishers Limited. All rights reserved.
  * Lee and Touba (2015) Yu-Wei Lee and Nur A Touba. 2015.  Improving logic obfuscation via logic cone analysis. In _2015 16th Latin-American Test Symposium (LATS)_. IEEE, 1–6.
  * Leef ([n.d.]) Serge Leef. [n.d.].  https://www.darpa.mil/program/automatic-implementation-of-secure-silicon
  * Leiserson et al. (2014) Andrew J. Leiserson, Mark E. Marson, and Megan A. Wachs. 2014\.  Gate-Level Masking under a Path-Based Leakage Metric. In _Cryptographic Hardware and Embedded Systems – CHES 2014_ , Lejla Batina and Matthew Robshaw (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 580–597.
  * Leprince-Ringuet (2021) Daphne Leprince-Ringuet. 2021\.  The global chip shortage is creating a new problem: More fake components.  https://www.zdnet.com/article/the-global-chip-shortage-is-creating-a-new-problem-more-fake-components-as-fraudsters-cash-in/
  * Levi et al. (2020) Itamar Levi, Davide Bellizia, David Bol, and François-Xavier Standaert. 2020\.  Ask less, get more: Side-channel signal hiding, revisited.  _IEEE Transactions on Circuits and Systems I: Regular Papers_ 67, 12 (2020), 4904–4917.
  * Li et al. (2016) Hao Li, Fanshu Jiao, and Alex Doboli. 2016.  Analog circuit topological feature extraction with unsupervised learning of new sub-structures. In _2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)_. IEEE, 1509–1512.
  * Li et al. (2020c) Tian Li, Anit Kumar Sahu, Ameet Talwalkar, and Virginia Smith. 2020c.  Federated Learning: Challenges, Methods, and Future Directions.  _IEEE Signal Process. Mag._ 37, 3 (May 2020), 50–60.  https://doi.org/10.1109/MSP.2020.2975749
  * Li et al. (2020a) Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin Sapatnekar, Ramesh Harjani, and Jiang Hu. 2020a.  Exploring a machine learning approach to performance driven analog IC placement. In _2020 IEEE computer society annual symposium on VLSI (ISVLSI)_. IEEE, 24–29.
  * Li et al. (2020b) Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S Sapatnekar, Ramesh Harjani, and Jiang Hu. 2020b.  A customized graph neural network model for guiding analog IC placement. In _2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)_. IEEE, 1–9.
  * Li et al. (2019) Yaping Li, Yong Wang, Yusong Li, Ranran Zhou, and Zhaojun Lin. 2019.  An artificial neural network assisted optimization system for analog design space exploration.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 39, 10 (2019), 2640–2653.
  * Li et al. (2018) Zhen Li, Deqing Zou, Shouhuai Xu, Xinyu Ou, Hai Jin, Sujuan Wang, Zhijun Deng, and Yuyi Zhong. 2018\.  Vuldeepecker: A deep learning-based system for vulnerability detection.  _arXiv preprint arXiv:1801.01681_ (2018).
  * Liang et al. (2020) Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, and Gi-Joon Nam. 2020\.  Routing-Free Crosstalk Prediction. In _2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)_. 1–9.
  * Liao et al. (2020) Haiguang Liao, Wentai Zhang, Xuliang Dong, Barnabas Poczos, Kenji Shimada, and Levent Burak Kara. 2020\.  A deep reinforcement learning approach for global routing.  _Journal of Mechanical Design_ 142, 6 (2020).
  * Lienig and Scheible (2020) Jens Lienig and Juergen Scheible. 2020.  _Steps in Physical Design: From Netlist Generation to Layout Post Processing_.  Springer International Publishing, Cham, 165–211.  https://doi.org/10.1007/978-3-030-39284-0_5
  * Lin (2012) Kuang Tsan Lin. 2012\.  Based on Binary Encoding Methods and Visual Cryptography Schemes to Hide Data. In _2012 Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing_. 59–62.  https://doi.org/10.1109/IIH-MSP.2012.20
  * Lipp et al. (2018) Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, et al. 2018\.  Meltdown: Reading kernel memory from user space. In _27th USENIX Security Symposium (USENIX Security 18)_. 973–990.
  * Liu et al. (2009) Bo Liu, Yan Wang, Zhiping Yu, Leibo Liu, Miao Li, Zheng Wang, Jing Lu, and Francisco V Fernández. 2009.  Analog circuit optimization system based on hybrid evolutionary algorithms.  _Integration_ 42, 2 (2009), 137–148.
  * Liu and Kim (2019) Muqing Liu and Chris H. Kim. 2019.  Demonstration of a Passive IC Tamper Sensor Based on an Exposed Floating Gate Device in a Standard Logic Process.  _IEEE Transactions on Electron Devices_ 66, 6 (2019), 2735–2740.  https://doi.org/10.1109/TED.2019.2909558
  * Liu et al. (2020a) Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z Pan. 2020a.  Towards decrypting the art of analog layout: Placement quality prediction via transfer learning. In _2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)_. IEEE, 496–501.
  * Liu et al. (2015) Yu Liu, Georgios Volanis, Ke Huang, and Yiorgos Makris. 2015\.  Concurrent hardware Trojan detection in wireless cryptographic ICs. In _2015 IEEE International Test Conference (ITC)_. IEEE, 1–8.
  * Liu et al. (2020b) Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, and Ankur Srivastava. 2020b.  Strong anti-sat: Secure and effective logic locking. In _2020 21st International Symposium on Quality Electronic Design (ISQED)_. IEEE, 199–205.
  * Liu et al. (2017) Zhenbao Liu, Zhen Jia, Chi-Man Vong, Shuhui Bu, Junwei Han, and Xiaojun Tang. 2017\.  Capturing high-discriminative fault features for electronics-rich analog system via deep learning.  _IEEE Transactions on Industrial Informatics_ 13, 3 (2017), 1213–1226.
  * Livengood et al. (2011) R Livengood, S Tan, P Hack, M Kane, and Y Greenzweig. 2011.  Focused Ion Beam Circuit Edit–A Look into the Past, Present, and Future.  _Microscopy and Microanalysis_ 17, S2 (2011), 672–673.  https://doi.org/10.1017/S1431927611004235
  * Lourenço et al. (2019) Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, and G Dundar. 2019\.  Using polynomial regression and artificial neural networks for reusable analog ic sizing. In _2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 13–16.
  * Lourenço et al. (2018) Nuno Lourenço, João Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Póvoa, and Nuno Horta. 2018\.  On the exploration of promising analog IC designs via artificial neural networks. In _2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)_. IEEE, 133–136.
  * Lu et al. (2021a) Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim. 2021a.  RL-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning. In _2021 58th ACM/IEEE Design Automation Conference (DAC)_. IEEE, 733–738.
  * Lu et al. (2020) Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim. 2020\.  VLSI Placement Optimization using Graph Neural Networks. In _34th Advances in Neural Information Processing Systems (NeurIPS) Workshop on ML for Systems_.
  * Lu et al. (2021b) Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim. 2021b.  The law of attraction: Affinity-aware placement optimization using graph neural networks. In _Proceedings of the 2021 International Symposium on Physical Design_. 7–14.
  * Lyons and Vanderkulk (1962) Robert E Lyons and Wouter Vanderkulk. 1962.  The use of triple-modular redundancy to improve computer reliability.  _IBM journal of research and development_ 6, 2 (1962), 200–209.
  * Ma et al. (2021) Haocheng Ma, Jiaji He, Yanjiang Liu, Leibo Liu, Yiqiang Zhao, and Yier Jin. 2021\.  Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel Protection.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 40, 6 (2021), 1077–1089.  https://doi.org/10.1109/TCAD.2020.3024938
  * Magaña et al. (2017) Jonathon Magaña, Daohang Shi, Jackson Melchert, and Azadeh Davoodi. 2017.  Are proximity attacks a threat to the security of split manufacturing of integrated circuits?  _IEEE Transactions on Very Large Scale Integration (VLSI) Systems_ 25, 12 (2017), 3406–3419.
  * Makrani et al. (2019) Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, and Setareh Rafatirad. 2019.  Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design.  _Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019_ , 397–403.  https://doi.org/10.1109/FPL.2019.00069
  * Markowitch et al. (2011) Olivier Markowitch, Liran Lerman, and Gianluca Bontempi. 2011\.  Side channel attack: An approach based on machine learning.  _Constructive Side-Channel Analysis and Secure Design, COSADE_.
  * Martin et al. (2016) Grant Martin, Louis Scheffer, and Luciano Lavagno. 2016\.  _Electronic Design Automation for Integrated Circuits Handbook_.  CRC Press.
  * Massad et al. (2017) Mohamed El Massad, Jun Zhang, Siddharth Garg, and Mahesh V Tripunitara. 2017.  Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism.  _arXiv preprint arXiv:1703.10187_ (2017).
  * Matsuba et al. (2018) Teruki Matsuba, Nobukazu Takai, Masafumi Fukuda, and Yusuke Kubo. 2018.  Inference of suitable for required specification analog circuit topology using deep learning. In _2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)_. IEEE, 131–134.
  * McMahan and Ramage (2017) Brendan McMahan and Daniel Ramage. 2017.  Federated Learning: Collaborative Machine Learning without Centralized Training Data.  https://ai.googleblog.com/2017/04/federated-learning-collaborative.html.  Accessed: 2022-2-1.
  * Mina et al. (2022) Rayan Mina, Chadi Jabbour, and George E Sakr. 2022\.  A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation.  _Electronics_ 11, 3 (2022), 435.
  * Mirhoseini et al. (2020) Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae, et al. 2020\.  Chip placement with deep reinforcement learning.  _arXiv preprint arXiv:2004.10746_ (2020).
  * Mirhoseini et al. (2021) Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim M. Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, Will Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, and Jeff Dean. 2021\.  A graph placement methodology for fast chip design.  _Nature_ 594 7862 (2021), 207–212.
  * Moos et al. (2021) Thorben Moos, Felix Wegener, and Amir Moradi. 2021\.  DL-LA: Deep Learning Leakage Assessment: A modern roadmap for SCA evaluations.  _IACR Transactions on Cryptographic Hardware and Embedded Systems_ (2021), 552–598.
  * Murphy and McCarthy (2021) Seán D Murphy and Kevin G McCarthy. 2021.  Automated Design of CMOS Operational Amplifier Using a Neural Network. In _2021 32nd Irish Signals and Systems Conference (ISSC)_. IEEE, 1–6.
  * Nahiyan et al. (2019) Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, and Mark Tehranipoor. 2019\.  Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 38, 6 (2019), 1003–1016.  https://doi.org/10.1109/TCAD.2018.2834396
  * Nahiyan et al. (2017) Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo Contreras, Domenic Forte, and Mark Tehranipoor. 2017\.  Hardware trojan detection through information flow security verification. In _2017 IEEE International Test Conference (ITC)_. 1–10.  https://doi.org/10.1109/TEST.2017.8242062
  * Narayanan et al. (2017) Annamalai Narayanan, Mahinthan Chandramohan, Rajasekar Venkatesan, Lihui Chen, Yang Liu, and Shantanu Jaiswal. 2017.  graph2vec: Learning Distributed Representations of Graphs.  arXiv:1707.05005 [cs.AI]
  * Neto et al. (2019) W. L. Neto, Max Austin, Scott Temple, L. Amarù, Xifan Tang, and P. Gaillardon. 2019\.  LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper.  _2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_ (2019), 1–6.
  * Neumeier and Keren (2012) Yaara Neumeier and Osnat Keren. 2012.  Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices. In _2012 IEEE 18th International On-Line Testing Symposium (IOLTS)_. IEEE, 156–161.
  * Pagliarini et al. (2020) Samuel Pagliarini, Joseph Sweeney, Ken Mai, Shawn Blanton, Larry Pileggi, and Subhasish Mitra. 2020\.  Split-chip design to prevent ip reverse engineering.  _IEEE Design & Test_ 38, 4 (2020), 109–118.
  * Pan et al. (2019) Po-Cheng Pan, Chien-Chia Huang, and Hung-Ming Chen. 2019\.  Late breaking results: An efficient learning-based approach for performance exploration on analog and RF circuit synthesis. In _2019 56th ACM/IEEE Design Automation Conference (DAC)_. IEEE, 1–2.
  * Pan and Yang (2010) S. J. Pan and Q. Yang. 2010.  A Survey on Transfer Learning.  _IEEE Trans Knowl Data Eng_ 22, 10 (2010), 1345–1359.  https://doi.org/10.1109/TKDE.2009.191
  * Pan and Mishra (2021) Zhixin Pan and Prabhat Mishra. 2021.  Automated Test Generation for Hardware Trojan Detection Using Reinforcement Learning. In _Proceedings of the 26th Asia and South Pacific Design Automation Conference_ (Tokyo, Japan) _(ASPDAC ’21)_. Association for Computing Machinery, New York, NY, USA, 408–413.  https://doi.org/10.1145/3394885.3431595
  * Pasandi et al. (2019) Ghasem Pasandi, Shahin Nazarian, and Massoud Pedram. 2019\.  Approximate logic synthesis: A reinforcement learning-based technology mapping approach. In _20th International Symposium on Quality Electronic Design (ISQED)_. IEEE, 26–32.
  * Pasandi et al. (2020) Ghasem Pasandi, MacKenzie Peterson, Moises Herrera, Shahin Nazarian, and Massoud Pedram. 2020\.  Deep-PowerX: A deep learning-based framework for low-power approximate logic synthesis.  _ACM International Conference Proceeding Series_.  https://doi.org/10.1145/3370748.3406555
  * Passos et al. (2006) Márcio G Passos, PH da F Silva, and Humberto CC Fernandes. 2006.  A RBF/MLP modular neural network for microwave device modeling.  _International Journal of computer science and network security_ 6, 5A (2006), 81–86.
  * Paszke et al. (2019) Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, Alban Desmaison, Andreas Kopf, Edward Yang, Zachary DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fang, Junjie Bai, and Soumith Chintala. 2019.  PyTorch: An Imperative Style, High-Performance Deep Learning Library.  In _Advances in Neural Information Processing Systems 32_ , H. Wallach, H. Larochelle, A. Beygelzimer, F. d'Alché-Buc, E. Fox, and R. Garnett (Eds.). Curran Associates, Inc., 8024–8035.  http://papers.neurips.cc/paper/9015-pytorch-an-imperative-style-high-performance-deep-learning-library.pdf
  * Pecht and Tiku (2006) M. Pecht and S. Tiku. 2006\.  Bogus: Electronic Manufacturing and Consumers Confront a Rising Tide of Counterfeit Electronics.  _IEEE Spectr._ 43, 5 (may 2006), 37–46.  https://doi.org/10.1109/MSPEC.2006.1628506
  * Pedregosa et al. (2011) F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion, O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg, J. Vanderplas, A. Passos, D. Cournapeau, M. Brucher, M. Perrot, and E. Duchesnay. 2011.  Scikit-learn: Machine Learning in Python.  _Journal of Machine Learning Research_ 12 (2011), 2825–2830.
  * Perry (2007) Guy Perry. 2007\.  _The fundamentals of Digital Semiconductor testing_.  Soft Test Inc.
  * Petrovic et al. (2012) Vladimir Petrovic, Marko Ilic, Gunter Schoof, and Zoran Stamenkovic. 2012.  Design methodology for fault tolerant ASICs. In _2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS)_. 8–11.  https://doi.org/10.1109/DDECS.2012.6219014
  * Picek et al. (2019) Stjepan Picek, Annelie Heuser, Alan Jovic, Shivam Bhasin, and Francesco Regazzoni. 2019.  The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations.  _IACR Trans. on Cryptographic Hardware and Embedded Systems_ 2019, 1 (2019), 1–29.
  * Picek et al. (2021) Stjepan Picek, Guilherme Perin, Luca Mariot, Lichao Wu, and Lejla Batina. 2021.  SoK: Deep Learning-based Physical Side-channel Analysis.  _Cryptology ePrint Archive_ (2021).
  * Popp and Mangard (2005) Thomas Popp and Stefan Mangard. 2005.  Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In _Cryptographic Hardware and Embedded Systems – CHES 2005_ , Josyula R. Rao and Berk Sunar (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 172–186.
  * Prouff and Rivain (2013) Emmanuel Prouff and Matthieu Rivain. 2013.  Masking against Side-Channel Attacks: A Formal Security Proof. In _Advances in Cryptology – EUROCRYPT 2013_ , Thomas Johansson and Phong Q. Nguyen (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 142–159.
  * Prouff et al. (2009) Emmanuel Prouff, Matthieu Rivain, and Regis Bevan. 2009\.  Statistical Analysis of Second Order Differential Power Analysis.  _IEEE Trans. Comput._ 58, 6 (2009), 799–811.  https://doi.org/10.1109/TC.2009.15
  * Rajendran et al. (2015a) Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, and Ramesh Karri. 2015a.  Belling the CAD: Toward Security-Centric Electronic System Design.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 34, 11 (2015), 1756–1769.  https://doi.org/10.1109/TCAD.2015.2428707
  * Rajendran et al. (2012) Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2012.  Security analysis of logic obfuscation. In _Proceedings of the 49th Annual Design Automation Conference_. 83–89.
  * Rajendran et al. (2015b) Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2015b.  Fault Analysis-Based Logic Encryption.  _IEEE Trans. Comput._ 64, 2 (2015), 410–424.  https://doi.org/10.1109/TC.2013.193
  * Razavi (2000) Behzad Razavi. 2000\.  Design of Analog CMOS Integrated Circuits.
  * Reparaz (2016) Oscar Reparaz. 2016\.  Detecting flawed masking schemes with leakage detection tests. In _International Conference on Fast Software Encryption_. Springer, 204–222.
  * Reparaz et al. (2018) Oscar Reparaz, Lauren De Meyer, Begül Bilgin, Victor Arribas, Svetla Nikova, Ventzislav Nikov, and Nigel Smart. 2018\.  CAPA: the spirit of beaver against physical attacks. In _Annual International Cryptology Conference_. Springer, 121–151.
  * Rijsdijk et al. (2021a) Jorai Rijsdijk, Lichao Wu, and Guilherme Perin. 2021a.  Reinforcement Learning-based Design of Side-channel Countermeasures.  _Cryptology ePrint Archive_ (2021).
  * Rijsdijk et al. (2021b) Jorai Rijsdijk, Lichao Wu, Guilherme Perin, and Stjepan Picek. 2021b.  Reinforcement Learning for Hyperparameter Tuning in Deep Learning-based Side-channel Analysis.  _Cryptology ePrint Archive, Report 2021/526_ (2021), 71.
  * Robertson and Riley (2018) Jordan Robertson and Michael Riley. 2018.  The big hack: How china used a tiny chip to infiltrate us companies.  _Bloomberg Businessweek_ 4, 2018 (2018).
  * Rosenbaum et al. (2020) E Rosenbaum, J Xiong, A Yang, Z Chen, and Maxim Raginsky. 2020.  Machine learning for circuit aging simulation. In _2020 IEEE International Electron Devices Meeting (IEDM)_. IEEE, 39–1.
  * Rotman and Wolf (2020) Michael Rotman and Lior Wolf. 2020.  Electric analog circuit design with hypernetworks and a differential simulator. In _ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)_. IEEE, 4157–4161.
  * Rudin (2019) Cynthia Rudin. 2019\.  Stop explaining black box machine learning models for high stakes decisions and use interpretable models instead.  _Nature Machine Intelligence_ 1, 5 (May 2019), 206–215.  https://doi.org/10.1038/s42256-019-0048-x
  * Rutenbar (2006) Rob A Rutenbar. 2006\.  Design automation for analog: the next generation of tool challenges. In _2006 IEEE/ACM International Conference on Computer Aided Design_. IEEE, 458–460.
  * Salmani et al. (2012) Hassan Salmani, Mark Tehranipoor, and J. Plusquellic. 2012\.  A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.  _Very Large Scale Integration (VLSI) Systems, IEEE Transactions on_ 20 (02 2012), 112 – 125.  https://doi.org/10.1109/TVLSI.2010.2093547
  * Sanabria-Borbón et al. (2020) Adriana C Sanabria-Borbón, Sergio Soto-Aguilar, Johan J Estrada-López, Douglas Allaire, and Edgar Sánchez-Sinencio. 2020\.  Gaussian-process-based surrogate for optimization-aided and process-variations-aware analog circuit design.  _Electronics_ 9, 4 (2020), 685.
  * Santhana Krishnan and Palanisamy (2021) Udaya Shankar Santhana Krishnan and Kalpana Palanisamy. 2021.  Recycled integrated circuit detection using reliability analysis and machine learning algorithms.  _IET Computers & Digital Techniques_ 15, 1 (2021), 20–35.
  * Schaldenbrand (2019) A Schaldenbrand. 2019\.  Analog reliability analysis for mission-critical applications white paper.  _Cadence Design Systems, Inc_ (2019).
  * Scheible and Lienig (2015) Juergen Scheible and Jens Lienig. 2015.  Automation of analog IC layout: Challenges and solutions. In _Proceedings of the 2015 Symposium on International Symposium on Physical Design_. 33–40.
  * Settaluri et al. (2020) Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, and Borivoje Nikolic. 2020\.  Autockt: Deep reinforcement learning of analog circuit designs. In _2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)_. IEEE, 490–495.
  * Shah et al. (2021) Nimesh Shah, Durba Chatterjee, Brojogopal Sapui, Debdeep Mukhopadhyay, and Arindam Basu. 2021\.  Introducing recurrence in strong PUFs for enhanced machine learning attack resistance.  _IEEE Journal on Emerging and Selected Topics in Circuits and Systems_ 11, 2 (2021), 319–332.
  * Shakya et al. (2015) Bicky Shakya, Ujjwal Guin, Mark Tehranipoor, and Domenic Forte. 2015.  Performance optimization for on-chip sensors to detect recycled ICs. In _2015 33rd IEEE International Conference on Computer Design (ICCD)_. IEEE, 289–295.
  * Shakya et al. (2017) Bicky Shakya, Tony He, Hassan Salmani, Domenic Forte, Swarup Bhunia, and Mark Tehranipoor. 2017\.  Benchmarking of hardware trojans and maliciously affected circuits.  _Journal of Hardware and Systems Security_ 1, 1 (2017), 85–102.
  * Shakya et al. (2019) Bicky Shakya, Haoting Shen, Mark Tehranipoor, and Domenic Forte. 2019.  Covert gates: Protecting integrated circuits with undetectable camouflaging.  _IACR Transactions on Cryptographic Hardware and Embedded Systems_ (2019), 86–118.
  * Shamsi et al. (2017) Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z Pan, and Yier Jin. 2017\.  AppSAT: Approximately deobfuscating integrated circuits. In _2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)_. IEEE, 95–100.
  * Shi et al. (2016) Qihang Shi, Navid Asadizanjani, Domenic Forte, and Mark M Tehranipoor. 2016.  A layout-driven framework to assess vulnerability of ICs to microprobing attacks. In _2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)_. IEEE, 155–160.
  * Shi et al. (2018) Qihang Shi, Mark M Tehranipoor, and Domenic Forte. 2018\.  Obfuscated built-in self-authentication with secure and efficient wire-lifting.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 38, 11 (2018), 1981–1994.
  * Sisejkovic et al. (2021) Dominik Sisejkovic, Farhad Merchant, Lennart M Reimann, Harshit Srivastava, Ahmed Hallawa, and Rainer Leupers. 2021.  Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.  _J. Emerg. Technol. Comput. Syst._ 17, 3 (May 2021), 1–26.  https://doi.org/10.1145/3431389
  * Stratigopoulos and Sunter (2014) Haralampos-G Stratigopoulos and Stephen Sunter. 2014.  Fast Monte Carlo-based estimation of analog parametric test metrics.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 33, 12 (2014), 1977–1990.
  * Subramani et al. (2017) Kiruba Sankaran Subramani, Angelos Antonopoulos, Ahmed Attia Abotabl, Aria Nosratinia, and Yiorgos Makris. 2017.  ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceivers. In _2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. IEEE, 722–727.
  * Subramanyan et al. (2015) Pramod Subramanyan, Sayak Ray, and Sharad Malik. 2015.  Evaluating the security of logic encryption algorithms. In _2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)_. IEEE, 137–143.
  * Sugawara et al. (2019) Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, and Makoto Nagata. 2019\.  Side-channel leakage from sensor-based countermeasures against fault injection attack.  _Microelectronics Journal_ 90 (2019), 63–71.  https://doi.org/10.1016/j.mejo.2019.05.017
  * Sun et al. (2019) Shiliang Sun, Zehui Cao, Han Zhu, and Jing Zhao. 2019\.  A survey of optimization methods from a machine learning perspective.  _IEEE transactions on cybernetics_ 50, 8 (2019), 3668–3681.
  * Sunar et al. (2007) Berk Sunar, Gunnar Gaubatz, and Erkay Savas. 2007\.  Sequential circuit design for embedded cryptographic applications resilient to adversarial faults.  _IEEE Trans. Comput._ 57, 1 (2007), 126–138.
  * Svyatkovskiy et al. (2019) Alexey Svyatkovskiy, Ying Zhao, Shengyu Fu, and Neel Sundaresan. 2019.  Pythia: AI-assisted code completion system. In _Proceedings of the 25th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining_. 2727–2735.
  * Swings et al. (1990) Koen Swings, Georges Gielen, and Willy Sansen. 1990\.  An intelligent analog IC design system based on manipulation of design equations. In _IEEE Proceedings of the Custom Integrated Circuits Conference_. IEEE, 8–6.
  * Takai and Fukuda (2017) Nobukazu Takai and Masafumi Fukuda. 2017.  Prediction of element values of OPAmp for required specifications utilizing deep learning. In _2017 International Symposium on Electronics and Smart Devices (ISESD)_. IEEE, 300–303.
  * Tan et al. (2020) Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Amin Rezaei, Yuanqi Shen, et al. 2020\.  Benchmarking at the frontier of hardware security: Lessons from logic locking.  _arXiv preprint arXiv:2006.06806_ (2020).
  * Tao et al. (2015) Jun Tao, Changhai Liao, Xuan Zeng, and Xin Li. 2015\.  Harvesting design knowledge from the internet: High-dimensional performance tradeoff modeling for large-scale analog circuits.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 35, 1 (2015), 23–36.
  * Tehranipoor and Koushanfar (2010) Mohammad Tehranipoor and Farinaz Koushanfar. 2010.  A Survey of Hardware Trojan Taxonomy and Detection.  _IEEE Design Test of Computers_ 27, 1 (2010), 10–25.  https://doi.org/10.1109/MDT.2010.7
  * Tehranipoor and Wang (2011) Mohammad Tehranipoor and Cliff Wang. 2011.  _Introduction to Hardware Security and Trust_.  Springer Publishing Company, Incorporated.
  * Terapasirdsin and Wattanapongsakorn (2010) Apichat Terapasirdsin and Naruemon Wattanapongsakorn. 2010\.  Crosstalk minimization in VLSI design using signal transition avoidance. In _2010 10th International Symposium on Communications and Information Technologies_. 911–915.  https://doi.org/10.1109/ISCIT.2010.5665117
  * Timon (2019) Benjamin Timon. 2019\.  Non-profiled deep learning-based side-channel attacks with sensitivity analysis.  _IACR Transactions on Cryptographic Hardware and Embedded Systems_ (2019), 107–131.
  * Tomashevich et al. (2014) Victor Tomashevich, Yaara Neumeier, Raghavan Kumar, Osnat Keren, and Ilia Polian. 2014.  Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. In _2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)_. IEEE, 40–45.
  * Trichina (2003) Elena Trichina. 2003\.  Combinational logic design for AES subbyte transformation on masked data.  _Cryptology EPrint Archive_ (2003).
  * Tudor et al. (2011) Bogdan Tudor, Joddy Wang, Weidong Liu, and Hany Elhak. 2011\.  MOS device aging analysis with HSPICE and CustomSim.  _Synopsys, White Paper_ (2011).
  * Utyamishev and Partin-Vaisband (2020) Dmitry Utyamishev and Inna Partin-Vaisband. 2020.  Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 39, 1 (2020), 45–55.  https://doi.org/10.1109/TCAD.2018.2883971
  * Vaidyanathan et al. (2014) Kaushik Vaidyanathan, Bishnu P Das, Ekin Sumbul, Renzhi Liu, and Larry Pileggi. 2014\.  Building trusted ICs using split fabrication. In _2014 IEEE international symposium on hardware-oriented security and trust (HOST)_. IEEE, 1–6.
  * Vijayakumar and Kundu (2015) Arunkumar Vijayakumar and Sandip Kundu. 2015.  A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. In _2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)_. IEEE, 653–658.
  * Vijayakumar et al. (2016) Arunkumar Vijayakumar, Vinay C Patil, Charles B Prado, and Sandip Kundu. 2016.  Machine learning resistant strong PUF: Possible or a pipe dream?. In _2016 IEEE international symposium on hardware oriented security and trust (HOST)_. IEEE, 19–24.
  * Volanis et al. (2019) Georgios Volanis, Yichuan Lu, Sai Govinda Rao Nimmalapudi, Angelos Antonopoulos, Andrew Marshall, and Yiorgos Makris. 2019.  Analog performance locking through neural network-based biasing. In _2019 IEEE 37th VLSI Test Symposium (VTS)_. IEEE, 1–6.
  * Wang et al. (2015a) Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, Rouwaida Kanj, and Chenjie Gu. 2015a.  Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 35, 8 (2015), 1255–1268.
  * Wang et al. (2017b) Huanyu Wang, Domenic Forte, Mark M. Tehranipoor, and Qihang Shi. 2017b.  Probing Attacks on Integrated Circuits: Challenges and Research Opportunities.  _IEEE Design Test_ 34, 5 (2017), 63–71.  https://doi.org/10.1109/MDAT.2017.2729398
  * Wang et al. (2019) Huanyu Wang, Qihang Shi, Domenic Forte, and Mark M. Tehranipoor. 2019.  Probing Assessment Framework and Evaluation of Antiprobing Solutions.  _IEEE Trans. Very Large Scale Integr. Syst._ 27, 6 (jun 2019), 1239–1252.  https://doi.org/10.1109/TVLSI.2019.2901449
  * Wang et al. (2020) Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, and Song Han. 2020.  GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning. In _2020 57th ACM/IEEE Design Automation Conference (DAC)_. IEEE, 1–6.
  * Wang et al. (2018c) Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, and Song Han. 2018c.  Learning to design circuits.  _arXiv preprint arXiv:1812.02734_ (2018).
  * Wang et al. (2015b) Jiafan Wang, Congyin Shi, Edgar Sanchez-Sinencio, and Jiang Hu. 2015b.  Built-in self optimization for variation resilience of analog filters. In _2015 IEEE Computer Society Annual Symposium on VLSI_. IEEE, 656–661.
  * Wang et al. (2009) Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Tim Cheng. 2009\.  _Electronic design automation: synthesis, verification, and test_.  Morgan Kaufmann.
  * Wang et al. (2018a) Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, and Jeyavijayan Rajendran. 2018a.  The cat and mouse in split manufacturing.  _IEEE Transactions on Very Large Scale Integration (VLSI) Systems_ 26, 5 (2018), 805–817.
  * Wang and Franzon (2018) Yi Wang and Paul D Franzon. 2018.  RFIC IP redesign and reuse through surrogate based machine learning method. In _2018 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO)_. IEEE, 1–4.
  * Wang et al. (2017a) Zheng Wang, Yi Chen, Aakash Patil, Jayasanker Jayabalan, Xueyong Zhang, Chip-Hong Chang, and Arindam Basu. 2017a.  Current mirror array: A novel circuit topology for combining physical unclonable function and machine learning.  _IEEE Transactions on Circuits and Systems I: Regular Papers_ 65, 4 (2017), 1314–1326.
  * Wang et al. (2018b) Zhenyu Wang, Xiangzhong Luo, and Zheng Gong. 2018b.  Application of deep learning in analog circuit sizing. In _Proceedings of the 2018 2nd International Conference on Computer Science and Artificial Intelligence_. 571–575.
  * Wolfe and Vemuri (2003) Glenn Wolfe and Ranga Vemuri. 2003.  Extraction and use of neural network models in automated synthesis of operational amplifiers.  _IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems_ 22, 2 (2003), 198–212.
  * Wu et al. (2020) Lichao Wu, Guilherme Perin, and Stjepan Picek. 2020\.  I Choose You: Automated Hyperparameter Tuning for Deep Learning-based Side-channel Analysis.  _IACR Cryptol. ePrint Arch._ 2020 (2020), 1293.
  * Wu et al. (2021) Nan Wu, Yuan Xie, and Cong Hao. 2021.  IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning.  _CoRR_ abs/2102.08138 (2021).  arXiv:2102.08138 https://arxiv.org/abs/2102.08138
  * Xiao et al. (2016) Kan Xiao, Adib Nahiyan, and Mark Tehranipoor. 2016.  Security rule checking in IC design.  _Computer_ 49, 8 (2016), 54–61.
  * Xiao and Tehranipoor (2013) Kan Xiao and Mohammed Tehranipoor. 2013.  BISA: Built-in self-authentication for preventing hardware Trojan insertion.  _Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013_ , 45–50.  https://doi.org/10.1109/HST.2013.6581564
  * Xie et al. (2020) Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, and Yiran Chen. 2020.  PowerNet: Transferable dynamic IR drop estimation via maximum convolutional neural network. In _2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)_. IEEE, 13–18.
  * Xu et al. (2018) Keyulu Xu, Weihua Hu, Jure Leskovec, and Stefanie Jegelka. 2018\.  How powerful are graph neural networks?  _arXiv preprint arXiv:1810.00826_ (2018).
  * Xu et al. (2017) Xiaolin Xu, Bicky Shakya, Mark M Tehranipoor, and Domenic Forte. 2017\.  Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. In _International conference on cryptographic hardware and embedded systems_. Springer, 189–210.
  * Yasaei et al. (2021a) Rozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, and Mohammad Abdullah Al Faruque. 2021a.  GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection.  _CoRR_ abs/2107.09130 (2021).  arXiv:2107.09130 https://arxiv.org/abs/2107.09130
  * Yasaei et al. (2021b) Rozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, and Mohammad Abdullah Al Faruque. 2021b.  GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection. In _2021 58th ACM/IEEE Design Automation Conference (DAC)_. ieeexplore.ieee.org, 217–222.  https://doi.org/10.1109/DAC18074.2021.9586150
  * Yasin et al. (2017) Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, and Jeyavijayan Rajendran. 2017.  Security analysis of anti-sat. In _2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)_. IEEE, 342–347.
  * Yasin et al. (2020) Muhammad Yasin, Jeyavijayan (JV) Rajendran, and Ozgur Sinanoglu. 2020.  _A Brief History of Logic Locking_.  Springer International Publishing, Cham, 17–31.  https://doi.org/10.1007/978-3-030-15334-2_2
  * Yasin and Sinanoglu (2015) Muhammad Yasin and Ozgur Sinanoglu. 2015.  Transforming between logic locking and IC camouflaging. In _2015 10th International Design & Test Symposium (IDT)_. IEEE, 1–4.
  * Ye et al. (2016) Jing Ye, Yu Hu, and Xiaowei Li. 2016.  POSTER: Attack on non-linear physical unclonable function. In _Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security_. 1751–1753.
  * Yu et al. (2018) Cunxi Yu, Houping Xiao, and Giovanni De Micheli. 2018\.  Developing synthesis flows without human knowledge. In _Proceedings of the 55th Annual Design Automation Conference_. 1–6.
  * Yu et al. (2017) Huan Yu, Madhavan Swaminathan, Chuanyi Ji, and David White. 2017.  A method for creating behavioral models of oscillators using augmented neural networks. In _2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)_. IEEE, 1–3.
  * Yu et al. (2021) Shih-Yuan Yu, Rozhin Yasaei, Qingrong Zhou, Tommy Nguyen, and Mohammad Abdullah Al Faruque. 2021\.  HW2VEC: A Graph Learning Tool for Automating Hardware Security.  arXiv:2107.12328 [cs.CR]
  * Zargari et al. (2021) Amir Hosein Afandizadeh Zargari, Marzieh Ashrafiamiri, Minjun Seo, Sai Manoj Pudukotai Dinakarrao, Mohammed E. Fouda, and Fadi J. Kurdahi. 2021.  CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering.  _CoRR_ abs/2110.11459 (2021).  arXiv:2110.11459 https://arxiv.org/abs/2110.11459
  * Zebulum et al. (2018) Ricardo Salem Zebulum, Marco Aurélio Pacheco, and Marley Maria Be Vellasco. 2018.  _Evolutionary electronics: automatic design of electronic circuits and systems by genetic algorithms_.  CRC press.
  * Zeng et al. (2021) Wei Zeng, Azadeh Davoodi, and Rasit Onur Topaloglu. 2021\.  ObfusX: routing obfuscation with explanatory analysis of a machine learning attack. In _2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)_. IEEE, 548–554.
  * Zennaro et al. (2018) Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, and Wolfgang Ecker. 2018.  A machine learning approach for area prediction of hardware designs from abstract specifications.  _Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018_ , 413–420.  https://doi.org/10.1109/DSD.2018.00076
  * Zhang et al. (2003) Qi-Jun Zhang, Kuldip C Gupta, and Vijay K Devabhaktuni. 2003\.  Artificial neural networks for RF and microwave design-from theory to practice.  _IEEE transactions on microwave theory and techniques_ 51, 4 (2003), 1339–1350.
  * Zhang and Tehranipoor (2014) Xuehui Zhang and Mohammad Tehranipoor. 2014.  Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs.  _IEEE Transactions on Very Large Scale Integration (VLSI) Systems_ 22, 5 (2014), 1016–1029.  https://doi.org/10.1109/TVLSI.2013.2264063
  * Zhang et al. (2020) Zhiming Zhang, Jaya Dofe, and Qiaoyan Yu. 2020.  Improving power analysis attack resistance using intrinsic noise in 3D ICs.  _Integration_ 73 (2020), 30–42.  https://doi.org/10.1016/j.vlsi.2020.02.007
  * Zhao et al. (2018) Guangquan Zhao, Xiaoyong Liu, Bin Zhang, Yuefeng Liu, Guangxing Niu, and Cong Hu. 2018\.  A novel approach for analog circuit fault diagnosis based on deep belief network.  _Measurement_ 121 (2018), 170–178.
  * Zhao and Zhang (2020) Zhenxin Zhao and Lihong Zhang. 2020.  Deep reinforcement learning for analog circuit sizing. In _2020 IEEE International Symposium on Circuits and Systems (ISCAS)_. IEEE, 1–5.
  * Zhou et al. (2017) Hai Zhou, Ruifeng Jiang, and Shuyu Kong. 2017.  CycSAT: SAT-based attack on cyclic logic encryptions. In _2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. 49–56.  https://doi.org/10.1109/ICCAD.2017.8203759
  * Zhou and Wong (1998) H. Zhou and D.F. Wong. 1998\.  Global routing with crosstalk constraints. In _Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)_. 374–377.  https://doi.org/10.1145/277044.277147
  * Zhu et al. (2020) Huifeng Zhu, Xiaolong Guo, Yier Jin, and Xuan Zhang. 2020\.  PowerScout: A Security-Oriented Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis. In _2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)_. 1–6.  https://doi.org/10.1109/AsianHOST51057.2020.9358263
  * Zhu et al. (2019) Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z Pan. 2019\.  Geniusroute: A new analog routing paradigm using generative neural network guidance. In _2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)_. IEEE, 1–8.
  * Zohner et al. (2012) Michael Zohner, Marc Stöttinger, Sorin A. Huss, and Oliver Stein. 2012.  An adaptable, modular, and autonomous side-channel vulnerability evaluator. In _2012 IEEE International Symposium on Hardware-Oriented Security and Trust_. 43–48.  https://doi.org/10.1109/HST.2012.6224317