evaluating the nonlinearity. Building Presgan on top of Stylegan therefore
requires to sample all noise variables $\mathbf{z}$ through hmc at each
training step. To speed up the training procedure, we only sample the noise
variables corresponding to the input latent code and condition on all the
other Gaussian noise variables. In addition, we do not follow the progressive
growing of the networks of Karras et al. (2019) for simplicity.

For this experiment, we choose the same hmc hyperparameters as for the
previous experiments but restrict the variance of the generative distribution
to be $\mathbold{\sigma}_{\text{high}}=0.2$. We set $\lambda=0.001$ for this
experiment.

Figure 4.3 shows cherry-picked images generated from Stylegan and Presgan. We
can observe that the Presgan maintains as good perceptual quality as the base
architecture. In addition, we also observed that the Stylegan tends to produce
some redundant images (these are not shown in Figure 4.3), something that we
did not observe with the Presgan. This lack of diversity was also reflected in
the fid scores which were $14.72\pm 0.09$ for Stylegan and $12.15\pm 0.09$ for
Presgan. These results suggest that entropy regularization effectively reduces
mode collapse while preserving sample quality.

#### 4.3.4Assessing held-out predictive log-likelihood

In this section we evaluate Presgans for generalization using predictive log-
likelihood. We use the dcgan architecture to build Presgan and evaluate the
log-likelihood on two benchmark datasets, mnist and cifar-10. We use images of
size $32\times 32$.

We compare the generalization performance of the Presgan against the vae
(Kingma & Welling, 2013; Rezende et al., 2014) by controlling for the
architecture and the evaluation procedure. In particular, we fit a vae that
has the same decoder architecture as the Presgan. We form the vae encoder by
using the same architecture as the dcgan discriminator and getting rid of the
output layer. We used linear maps to get the mean and the log-variance of the
approximate posterior.

To measure how Presgans compare to traditional gans in terms of log-
likelihood, we also fit a Presgan with $\lambda=0$.

Consider an unseen datapoint $\mathbf{x}^{*}$. We estimate its log marginal
likelihood $\log p_{\theta}(\mathbf{x}^{*})$ using importance sampling,

$\log
p_{\theta}(\mathbf{x}^{*})\approx\log\left(\frac{1}{S}\sum_{s=1}^{S}\frac{p_{\theta}\left(\mathbf{x}^{*}\,|\,\mathbf{z}^{(s)}\right)\cdot
p\left(\mathbf{z}^{(s)}\right)}{r\left(\mathbf{z}^{(s)}\,|\,\mathbf{x}^{*}\right)}\right),$
(4.32)

where we draw $S$ samples $\mathbf{z}^{(1)},\dots,\mathbf{z}^{(S)}$ from a
proposal distribution $r(\mathbf{z}\,|\,\mathbf{x}^{*})$.

There are different ways to form a good proposal
$r(\mathbf{z}\,|\,\mathbf{x}^{*})$, and we discuss several alternatives in
Section 4.5.1 of the appendix. In this paper, we take the following approach.
We define the proposal as a Gaussian distribution,

$\displaystyle r(\mathbf{z}\,|\,\mathbf{x}^{*})$
$\displaystyle=\mathcal{N}(\mathbold{\mu}_{r},\mathbold{\Sigma}_{r}).$ (4.33)

We set the mean parameter $\mathbold{\mu}_{r}$ to the maximum a posteriori
solution, i.e.,

$\displaystyle\mathbold{\mu}_{r}$
$\displaystyle=\operatorname*{arg\,max}_{z}\left(\log
p_{\theta}\left(\mathbf{x}^{*}\,|\,\mathbf{z}\right)+\log
p\left(\mathbf{z}\right)\right).$

We initialize this maximization algorithm using the mean of a pre-fitted
encoder, $q_{\gamma}(\mathbf{z}\,|\,\mathbf{x}^{*})$. The encoder is fitted by
minimizing the reverse kl divergence between
$q_{\gamma}(\mathbf{z}\,|\,\mathbf{x})$ and the true posterior
$p_{\theta}(\mathbf{z}\,|\,\mathbf{x})$ using the training data. This kl is

$\displaystyle\lx@glossaries@gls@link{acronym}{KL}{\leavevmode\textsc{kl}}\left(q_{\gamma}(\mathbf{z}\,|\,\mathbf{x})||p_{\theta}(\mathbf{z}\,|\,\mathbf{x})\right)=\log
p_{\theta}(\mathbf{x})-\mathbb{E}_{q_{\gamma}(\mathbf{z}\,|\,\mathbf{x})}\left[\log
p_{\theta}(\mathbf{x}\,|\,\mathbf{z})p(\mathbf{z})-\log
q_{\gamma}(\mathbf{z}\,|\,\mathbf{x})\right].$ (4.34)

Because the generative distribution is fixed at test time, minimizing the kl
here is equivalent to maximizing the second term in Eq. 4.34, which is the
elbo objective of vaes.

We set the proposal covariance $\mathbold{\Sigma}_{r}$ as an overdispersed
version444In general, overdispersed proposals lead to better importance
sampling estimates. of the encoder’s covariance matrix, which is diagonal. In
particular, to obtain $\mathbold{\Sigma}_{r}$ we multiply the elements of the
encoder’s covariance by a factor $\gamma$. In our experiments we set $\gamma$
to $1.2$.

We use $S=2{,}000$ samples to form the importance sampling estimator. Since
the pixel values are normalized in $[-1,+1]$, we use a truncated Gaussian
likelihood for evaluation. Specifically, for each pixel of the test image, we
divide the Gaussian likelihood by the probability (under the generative model)
that the pixel is within the interval $[-1,+1]$. We use the truncated Gaussian
likelihood at test time only.

Settings. For the Presgan, we use the same hmc hyperparameters as for the
previous experiments. We constrain the variance of the generative distribution
using $\mathbold{\sigma}_{\text{low}}=0.001$ and
$\mathbold{\sigma}_{\text{high}}=0.2$. We use the default dcgan values for the
remaining hyperparameters, including the optimization settings. For the
cifar-10 experiment, we choose $\lambda=0.001$. We set all learning rates to
$0.0002$. We set the dimension of the latent variables to $100$. We ran both
the vae and the Presgan for a maximum of $200$ epochs. For mnist, we use the
same settings as for cifar-10 but use $\lambda=0.0001$ and ran all methods for
a maximum of $50$ epochs.

Table 4.5: Generalization performance as measured by negative log-likelihood (lower is better) on mnist and cifar-10. Here the gan denotes a Presgan fitted without entropy regularization ($\lambda=0$). The Presgan reduces the gap in performance between the gan and the vae on both datasets. | mnist |  cifar-10
---|---|---
| Train | Test | Train | Test
vae | $-3483.94$ | $-3408.16$ | $-1978.91$ | $-1665.84$
gan | $-1410.78$ | $-1423.39$ | $-572.25$ | $-569.17$
Presgan | $-1418.91$ | $-1432.50$ | $-1050.16$ | $-1031.70$

Results. Table 4.3.4 summarizes the results. Here gan denotes the Presgan
fitted using $\lambda=0$. The vae outperforms both the gan and the Presgan on
both mnist and cifar-10. This is unsurprising given vaes are fitted to
maximize log-likelihood. The gan’s performance on cifar-10 is particularly
bad, suggesting it suffered from mode collapse. The Presgan, which mitigates
mode collapse achieves significantly better performance than the gan on
cifar-10. To further analyze the generalization performance, we also report
the log-likelihood on the training set in Table 4.3.4. We can observe that the
difference between the training log-likelihood and the test log-likelihood is
very small for all methods.

### 4.4 Appendix

#### 4.5.1Other ways to compute predictive log-likelihood

Here we discuss different ways to obtain a proposal in order to approximate
the predictive log-likelihood. For a test instance $\mathbf{x}^{*}$, we
estimate the marginal log-likelihood $\log p_{\theta}(\mathbf{x}^{*})$ using
importance sampling,

$\log
p_{\theta}(\mathbf{x}^{*})\approx\log\left(\frac{1}{S}\sum_{s=1}^{S}\frac{p_{\theta}\left(\mathbf{x}^{*}\,|\,\mathbf{z}^{(s)}\right)\;p\left(\mathbf{z}^{(s)}\right)}{r\left(\mathbf{z}^{(s)}\,|\,\mathbf{x}^{*}\right)}\right),$
(4.35)

where we draw the $S$ samples $\mathbf{z}^{(1)},\dots,\mathbf{z}^{(S)}$ from a
proposal distribution $r(\mathbf{z}\,|\,\mathbf{x}^{*})$. We next discuss
different ways to form the proposal $r(\mathbf{z}\,|\,\mathbf{x}^{*})$.

One way to obtain the proposal is to set $r(\mathbf{z}\,|\,\mathbf{x}^{*})$ as
a Gaussian distribution whose mean and variance are computed using samples
from an hmc algorithm with stationary distribution
$p_{\theta}(\mathbf{z}\,|\,\mathbf{x}^{*})\propto
p_{\theta}(\mathbf{x}^{*}\,|\,\mathbf{z})p(\mathbf{z})$. That is, the mean and
variance of $r(\mathbf{z}\,|\,\mathbf{x}^{*})$ are set to the empirical mean
and variance of the hmc samples.

The procedure above requires to run an hmc sampler, and thus it may be slow.
We can accelerate the procedure with a better initialization of the hmc chain.
Indeed, the second way to evaluate the log-likelihood also requires the hmc
sampler, but it is initialized using a mapping
$\mathbf{z}=g_{\eta}(\mathbf{x}^{\star})$. The mapping
$g_{\eta}(\mathbf{x}^{\star})$ is a network that maps from observed space
$\mathbf{x}$ to latent space $\mathbf{z}$. The parameters $\eta$ of the
network can be learned at test time using generated data. In particular,
$\eta$ can be obtained by generating data from the fitted generator of Presgan
and then fitting $g_{\eta}(\mathbf{x}^{\star})$ to map $\mathbf{x}$ to
$\mathbf{z}$ by maximum likelihood. This is, we first sample $M$ pairs
$(\mathbf{z}_{m},\mathbf{x}_{m})_{m=1}^{M}$ from the learned generative
distribution and then we obtain $\eta$ by minimizing
$\sum_{m=1}^{M}||\mathbf{z}_{m}-g_{\eta}(\mathbf{x}_{m})||_{2}^{2}$. Once the
mapping is fitted, we use it to initialize the hmc chain.

A third way to obtain the proposal is to learn an encoder network
$q_{\eta}(\mathbf{z}\,|\,\mathbf{x})$ jointly with the rest of the Presgan
parameters. This is effectively done by letting the discriminator distinguish
between pairs $(\mathbf{x},\mathbf{z})\sim p_{d}(\mathbf{x})\cdot
q_{\eta}(\mathbf{z}\,|\,\mathbf{x})$ and $(\mathbf{x},\mathbf{z})\sim
p_{\theta}(\mathbf{x},\mathbf{z})$ rather than discriminate $\mathbf{x}$
against samples from the generative distribution. These types of discriminator
networks have been used to learn a richer latent space for gan (Donahue et
al., 2016; Dumoulin et al., 2016). In such cases, we can use the encoder
network $q_{\eta}(\mathbf{z}\,|\,\mathbf{x})$ to define the proposal, either
by setting
$r(\mathbf{z}\,|\,\mathbf{x}^{*})=q_{\eta}(\mathbf{z}\,|\,\mathbf{x}^{*})$ or
by initializing the hmc sampler at the encoder mean.

The use of an encoder network is appealing but it requires a discriminator
that takes pairs $(\mathbf{x},\mathbf{z})$. The approach that we follow in the
paper also uses an encoder network but keeps the discriminator the same as for
the base dcgan. We found this approach to work better in practice. More in
detail, we use an encoder network $q_{\eta}(\mathbf{z}\,|\,\mathbf{x})$;
however the encoder is fitted at test time by maximizing the variational elbo,
given by
$\sum_{n}\mathbb{E}_{q_{\eta}(\mathbf{z}_{n}\,|\,\mathbf{x}_{n})}\left[\log
p_{\theta}(\mathbf{x}_{n},\mathbf{z}_{n})-\log
q_{\eta}(\mathbf{z}_{n}\,|\,\mathbf{x}_{n})\right]$. We set the proposal
$r(\mathbf{z}\,|\,\mathbf{x}^{*})=q_{\eta}(\mathbf{z}\,|\,\mathbf{x}^{*})$.
(Alternatively, the encoder can be used to initialize a sampler.)

#### 4.5.2Assessing mode collapse under increased data imbalance

In the main paper we show that mode collapse can happen not only when there
are increasing number of modes, as done in the gan literature, but also when
the data is imbalanced. We consider a perfectly balanced version of mnist by
using 5,000 training examples per class, totalling 50,000 training examples.
We refer to this original balanced dataset as D$1$. We build nine additional
training sets from this balanced dataset. Each additional training set D$k$
leaves only $5$ training examples for each class $j<k$. See Table 4.6 for all
the class distributions.

Table 4.6: Class distributions using the mnist dataset. There are $10$ class—one class for each of the $10$ digits in mnist. The distribution D$1$ is uniform and the other distributions correspond to different imbalance settings as given by the proportions in the table. Note these proportions might not sum to one exactly because of rounding. Dist | $0$ | $1$ | $2$ | $3$ | $4$ | $5$ | $6$ | $7$ | $8$ | $9$
---|---|---|---|---|---|---|---|---|---|---
D$1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$ | $0.1$
D$2$ | $10^{-3}$ | $0.11$ | $0.11$ | $0.11$ | $0.11$ | $0.11$ | $0.11$ | $0.11$ | $0.11$ | $0.11$
D$3$ | $10^{-3}$ | $10^{-3}$ | $0.12$ | $0.12$ | $0.12$ | $0.12$ | $0.12$ | $0.12$ | $0.12$ | $0.12$
D$4$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.14$ | $0.14$ | $0.14$ | $0.14$ | $0.14$ | $0.14$ | $0.14$
D$5$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.17$ | $0.17$ | $0.17$ | $0.17$ | $0.17$ | $0.17$
D$6$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.20$ | $0.20$ | $0.20$ | $0.20$ | $0.20$
D$7$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.25$ | $0.25$ | $0.25$ | $0.25$
D$8$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.33$ | $0.33$ | $0.33$
D$9$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.49$ | $0.49$
D$10$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $10^{-3}$ | $0.99$

Conclusion

Probabilistic graphical modeling with latent variables provides a useful
framework for learning from data. It enables accounting for uncertainty,
learning the latent structure underlying data in an interpretable way, and
incorporating prior knowledge. However probabilistic graphical modeling might
lack flexibility for the purpose of learning from the types of high-
dimensional complex data we currently encounter in practice. This thesis
developed deep probabilistic graphical modeling, which leverages deep learning
to bring flexibility to probabilistic graphical modeling. We used neural
networks to extend the canonical ef-pca to model and learn interpretable
quantities from image and text data. We leveraged recurrent neural networks to
build a class of models for sequential data where long-term dependencies are
accounted for using latent variables. We solved several problems that
probabilistic topic models suffer from using distributed representations of
words for model specification and neural networks for inference. This thesis
also made contributions on the algorithmic front. We developed reweighted
expectation maximization (rem), an algorithm that unifies several existing
maximum likelihood-based algorithms for learning models parameterized by deep
neural networks. This unifying view is made possible using expectation
maximization, a canonical inference algorithm for probabilistic graphical
models. rem leads to better generalization to unseen data. Finally, we showed
how to leverage the learning procedure behind generative adversarial networks
to fit probabilistic latent-variable models. This new algorithm, called
entropy-regularized adversarial learning, constitutes a solution to the mode
collapse problem that is pervasive in generative adversarial networks.

There are several choice points for deep probabilistic graphical modeling,
each of which can be explored for future work.

  1. 1.

Prior. Choosing a prior pertains to specifying our a priori knowledge of the
latent structure. Several of the model classes we developed above used simple
priors. Future work will explore how to devise richer priors for deep
probabilistic graphical modeling. We will also explore how to translate domain
knowledge into prior specification to apply deep probabilistic graphical
modeling to new domains (e.g. science.)

  2. 2.

Likelihood. We leveraged neural networks or word embeddings to define the
conditional distribution of the data given the latent variables as an
exponential family. The exponential family provides an umbrella distribution
for the types of data we encounter in practice (e.g. real-valued, categorical,
and binary.) Future work can explore other distributional forms for the
likelihood (e.g. distributions specified via a sampling procedure) or use
constrained neural networks to parameterize the likelihood (e.g. invertible
neural networks.)

  3. 3.

Posterior. We used variational inference as a framework for inferring the
posterior distribution of the latent variables. In particular, we used
distributions that are amenable to reparameterization such as the Gaussian,
and parameterized them using neural networks. Future work can explore other
choices of approximate posterior distributions, especially for discrete latent
variables often used in probabilistic graphical modeling.

  4. 4.

Algorithm. We explored both maximum likelihood and adversarial learning for
model fitting. These two paradigms are complementary. Adversarial learning
favors high quality of simulation of new data while maximum likelihood favors
high held-out likelihood on unseen data. In future work we will explore how we
can combine the strength of these two approaches to achieve all aspects of
generalization as described in our desiderata. We will also explore how to
make entropy-regularized adversarial learning amenable to discrete data and
discrete latent variables.

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# Hardware-aware training of models with synaptic delays for digital event-
driven neuromorphic processors

Alberto Patiño-Saucedoa, Roy Meijerb, Amirreza Yousefzadehc, d, Manil-Dev
Gomonyb,
Federico Corradib, Paul Detteterc, Laura Garrido-Regifea, Bernabé Linares-
Barrancoa, and Manolis Sifalakisc
a Instituto de Microelectrónica de Sevilla, CSIC/Universidad de Sevilla,
Seville, Spain,
b Eindhoven University of Technology, Dept. Electrical Engineering, Eindhoven,
Netherlands,
c IMEC-Netherlands, Eindhoven, Netherlands,
d University of Twente, Twente, Netherlands
Corresponding author email<EMAIL_ADDRESS>

###### Abstract

Configurable synaptic delays are a basic feature in many neuromorphic neural
network hardware accelerators. However, they have been rarely used in model
implementations, despite their promising impact on performance and efficiency
in tasks that exhibit complex (temporal) dynamics, as it has been unclear how
to optimize them. In this work, we propose a framework to train and deploy, in
digital neuromorphic hardware, highly performing spiking neural network models
(SNNs) where apart from the synaptic weights, the per-synapse delays are also
co-optimized. Leveraging spike-based back-propagation-through-time, the
training accounts for both platform constraints, such as synaptic weight
precision and the total number of parameters per core, as a function of the
network size. In addition, a delay pruning technique is used to reduce memory
footprint with a low cost in performance. We evaluate trained models in two
neuromorphic digital hardware platforms: Intel’s Loihi and Imec’s Seneca.
Loihi offers synaptic delay support using the so-called Ring-Buffer hardware
structure. Seneca does not provide native hardware support for synaptic
delays. A second contribution of this paper is therefore a novel area- and
memory-efficient hardware structure for acceleration of synaptic delays, which
we have integrated in Seneca. The evaluated benchmark involves several models
for solving the SHD (Spiking Heidelberg Digits) classification task, where
minimal accuracy degradation during the transition from software to hardware
is demonstrated. To our knowledge, this is the first work showcasing how to
train and deploy hardware-aware models parameterized with synaptic delays, on
multicore neuromorphic hardware accelerators.

###### Index Terms:

Spiking Neural Networks, Synaptic Delays, Neuromorphic processors, Loihi,
Temporal Signal Analysis, Spiking Heidelberg Digits

##  I Introduction

Axonal and dendritic synaptic delays are known to be subject to learning and
play a time-warping role in the information propagation in biological neural
networks [1]. Therefore, drawing inspiration from neuroscience, many
neuromorphic neural network accelerators offer primitives and constructs to
facilitate synaptic delays [2, 3, 4, 5, 6].

However, up until recently, parameterization of neural networks models with
synaptic delays had been a largely unexplored territory (for SNNs and ANNs
alike), with only a small corpus of literature historically dedicated in the
topic [7, 8, 9, 10, 11, 12, 13, 14, 15].

Nevertheless, recently, a few alternative approaches have started emerging for
training such delay models using back-propagation [16, 17, 18, 19, 20],
offering a fresh coverage of the topic with promising results. A shared
observation that seems to be confirmed in all of these recent works is that
models parameterized with synaptic delays achieve competitive, and often
superior, performance than other models (both spiking or non-spiking), with
on-average smaller model sizes. In addition in [16] it was also observed that
such models additionally tend to have sparser activity, which makes them more
memory and energy efficient, despite the memory overhead in neuromorphic
accelerators for implementing the delay structures.

Motivated by the study in [16], which defended the energy and memory
efficiency of delay models executing on neuromorphic accelerators based on
estimations, in this paper we conduct actual experiments with two digital
hardware platforms (Intel’s Loihi [5] and Imec’s Seneca [3]), in order to
assess various aspects of the efficiency of delay models. One key question
regards the fidelity of delay models trained offline and deployed for
inference on neural accelerators. A second question regards the actual
energy/power, latency, and memory efficiency of deploying delay models on
hardware. The main contributions of this paper are

  * •

a hardware-aware training framework generating (synaptic) delay models suited
for hardware acceleration

  * •

a newly proposed hardware structure for accelerating synaptic delays in
digital neuromorphic processors, with amortizable memory cost that scales with
model density and not network depth or size

  * •

a first-of-its-kind benchmark of (synaptic) delay models executed on
neuromorphic hardware accelerators

  * •

a validation of the credibility of the methodology presented in[21] for
algorithm-hardware benchmarking

##  II Related Work

A canonical formalization of delays, often seen in the literature has been to
parameterize synapses with an additional learnable delay variable, which can
be learned with back-propagation [10, 11, 22, 19, 12], local Hebbian-like
learning rules [17], annealing algorithms [7], etc. An alternative approach
featured in TDNNs [8, 15, 23, 14, 24], and recently for SNNs [18] involves
mapping delays in the spatial domain and train them with autoregressive models
as temporal convolution kernels (of fixed receptive fields).

Digital neuromorphic accelerator platforms have typically implemented support
structures for synaptic delays using one of two methods: Ring Buffer [4, 5,
25] or Shared Delay Queue[2, 3]. A ring buffer is a special type of circular
queue where currents with different delays accumulate in separate slots of the
queue. When using the ring buffer, the maximum possible delay in the system
will be limited to the size of the buffer, and the set of possible delays is
linearly distributed i.e., the temporal stride is constant. In this method,
there is one ring buffer per neuron; therefore, the memory overhead scales
with the number of neurons. By contrast, a delay queue is a shared structure
across neurons, lending to more area/memory efficiency when spike activity is
sparse. The axon delay is encoded directly in each spike packet containing a
few extra bits to indicate the amount of delay. The destination neuro-synaptic
core has several queues, each corresponding to a specific delay amount,
connected in a cascade. In this scheme, the number of queues scales with the
number of possible delays and not the maximum delay. The size of each queue
increases if the queue applies more delay on the spikes.

In [21] a useful hardware-algorithm benchmarking methodology was introduced,
which was adopted in [16] for producing estimates of the memory and energy
cost of deploying synaptic delay models on a neuromorphic accelerator. In this
work, we follow this methodology to generate similar reference estimates for
the networks that we deployed and contrast them with the actual measurements
that we performed.

##  III Methods

###  III-A Delay Model Description

In this work, we use a multilayer Spiking Neural Network (SNN) based on Leaky
Integrate-and-Fire (LIF) neurons. Their dynamic depends on their internal
state, known as the membrane potential, $u$, and their time-dependent input,
$I$. Also, it considers leaky integration that depends on a time constant,
${\tau}$. This model permits computational efficiency for hardware
implementation and, at the same time, reproduces biological processes. In a
discrete-time realization of a LIF neuron, the membrane potential updates as
follows:

$u_{k}=u_{k-1}e^{-\frac{1}{\tau}}(1-\theta_{k-1})+I_{k-1}$ (1)

$\theta_{k}=\begin{cases}1&{u}_{k}\geq u_{th}\\\
0&\text{otherwise}\end{cases}$ (2)

where ${\theta}$ denotes a function to generate activations or spikes whenever
the membrane potential reaches a threshold, $u_{th}$.

To incorporate synaptic delays in a conventional feed-forward SNN, we create
multiple time-delayed projections or synapses for every pre-synaptic/post-
synaptic neuron pair. Consequently, the firing of a neuron at a specific time
depends on both its current state and a subset of past activations from
neurons in the pre-synaptic layer, connected through direct projections. The
input of a neuron implementing the suggested framework for synaptic delays is:

$I_{k}=\sum_{d\in D}\sum_{i=1}^{N}w_{i,k}^{(d)}\theta_{i}^{(d)}$ (3)

where $D=\\{0,s,2s,...d_{max}\\}$ is the set of delays chosen for a given
task, which is defined with the maximum delay, $d_{max}$, and the stride, $s$.
The set of weights $\\{w_{i,j}\\}$ in a classic SNN is replaced by
$\\{w_{i,j}^{(d)}\\}$, since the group of weights can take different values
for each delay (see Fig.1(a)). This increases flexibility in the model by
allowing to control the total number of parameters.

Figure 1: Weight-delay representation before (a) and after (b) prune delay-
synapses.

###  III-B Training Framework

We train models that incorporate synaptic delays using the following strategy,
which is compatible with vanilla training frameworks used to train SNNs and
RNNs today (i.e. no special framework extensions), such as back-propagation in
our case.

The idea is to express the (temporal) parameterization of delays as a spatial
parameterization of synaptic weights, such that delay training is effected by
merely optimizing for synaptic weights. We start with a set of parallel
synapses per pair of pre- and post-synaptic neurons, each associated with a
delayed output from the pre-synaptic neuron (using a predetermined range of
delays and stride, see Fig.1(a)). We optimize the model as usual and prune all
delay-synapses that end up with small weights. We then fine-tune the model
with only the remaining synapses (see Fig.1(b)). We may introduce new synapses
to replace the pruned ones, with incrementally higher delay resolution in
localized sub-regions of the initial delay range, and repeat the process. As a
result, different neurons end up with different fan-in delay inputs. The
resulting models are topologically feed-forward, consistently shallower with
fewer parameters than their recurrent-connectivity counterparts, and exhibit
state-of-art performance (observed in in [16] and confirmed in other related
literature [18, 26, 19]). Their simpler structure renders them attractive for
resource-efficient deployment on neuromorphic accelerators.

Note that this training strategy for the delays allows us a priori to take
into account hardware constraints such as the maximum delay supported in the
platform (e.g. 60 timesteps in Loihi) as well as the delay memory constraints
(stride and pruning level may be amortized so that the resulting spike
activity does not exceed the available memory).

Another appealing consequence of the simplicity of this strategy is that it is
also compatible with on-device local learning rules such as STDP[27, 28], as
it reduces the goal of learning delays to one of adapting weights.

We train our SNN synaptic delay capable models with spatio-temporal back-
propagation (STBP) [29], a back-propagation through time (BPTT) variant for
SNNs. To account for the discontinuity of the membrane potential, we employed
a surrogate gradient function [30] with a fast sigmoid function as in [31].

###  III-C Hardware Model Deployment and Experimental Setup

####  III-C1 Network Models and Dataset - SHD

Using the delay model and training framework that was introduced in the
previous sections, we trained three network models for the Spiking Heidelberg
Digits (SHD) benchmark[32]: 700-48-48-20, 700-32-32-20, and 700-24-24-20. In
each network, synaptic delays are employed between the hidden layers and
between the second hidden and output layers. We did not consider synaptic
delays from input to the first hidden layer, as the input layer usually has
many neurons and is responsible for a large portion of the synaptic
parameters. Table I details the trained network topologies, training
configurations, initial delay configuration per hidden layer, as well as the
final number of delay levels retained after the iterative synapse pruning, and
the reference accuracy achieved for each model on the test-set. The initial
delay configurations are provided as max delay level and stride, which for
example (60, 2) would imply that we utilize synapses with delay levels {0,2,4
.. 58}. Finally, for the 700-48-48-20 model, we also explored a variation
involving _axonal-only delay pruning_. This means that instead of removing
individual synapses, we removed entire groups of synapses per axon until only
15 delay axons remained (700-48-48-20 Ax). The goal here was to understand the
trade-off in hardware resource savings between these two pruning strategies.
Fig. 2 illustrates the steps in the training pipeline.

TABLE I: The models trained with synaptic delays for the experiments Parameters | Model 1 | Model 2 | Model 3
---|---|---|---
Topology | 700-48-48-20 | 700-32-32-20 | 700-24-24-20
Num timesteps | 64 | 64 | 64
Max delay, stride | 60,2 | 60,2 | 60,2
# Delays after prune | 15 | 15 | 15
# Parameters | 82.6K | 47.4K | 32.6K
Ref. Accuracy | 87% | 82% | 83%

####  III-C2 Model deployment on Seneca and Loihi

We used PyTorch to train the SNN models with synaptic delays. After training,
we perform hardware-aware fine-tuning with weight quantization and type
conversion to produce models that can execute on the neuromorphic accelerators
that we used. In the case of Imec’s Seneca, we quantized the models to 16-bit
Brain-float, and in the case of Intel’s Loihi to 8-bit integer (see Fig.2).

On Seneca, we map the networks to 3 cores (one layer per core, and each core
is served by one shared delay queue). In Loihi, we could fit each model in one
core, but we also considered a mapping on three cores for the comparison with
Seneca, in terms of energy and latency (as this accounts also the overheads
for inter-core routing).

Loihi implements delays with a structure similar to ring-buffers, while Seneca
uses a variation of shared delay queues, which are introduced in the next
section. Tests on Seneca were done with the acceleration of synaptic delays
using the shared delay queue as well as without, whereby delays were emulated
in C within the RISC-V controller in each core. This way we can have a
quantitative assessment of the cost of using hw-support for synaptic delays.

Figure 2: Delay model training pipeline.

###  III-D Memory Efficient Synaptic Delay Acceleration (Seneca)

####  III-D1 Shared Circular Delay Queue Architecture

The proposed synaptic delay structure draws inspiration from the shared queue
model in [2] and incorporates the concept of “double-buffering”. Instead of a
linear chain of FIFOs (one per delay level), it simplifies the design to only
two FIFOs: the _pre-processing queue_ (PRQ) and the _post-processing queue_
(POQ). These two FIFOs are interconnected in a circular arrangement (see
Figure 3), hence the name “Shared Circular Delay Queue” (SCDQ).

There is an SCDQ module at every compute core of a neural network accelerator.
Conceptually it is positioned between a presynaptic and a postsynaptic layer,
with the input of the SCDQ queue facing the presynaptic layer and the output
of the SCDQ facing the postsynaptic layer, and is shared across all synapses
between neuron pairs. If multiple layers can be mapped in the same compute
core, then an SCDQ can also be shared across layers. As a result, the memory
complexity is not a function of the number of layers in a model, but rather a
function of the number of compute cores in use (and the aggregate activation
traffic as we will explain).

When an event packet (AER) is received at the SCDQ input, a delay counter is
added to it, which counts the maximum number of algorithmic timesteps by which
the event should be delayed. The event then traverses the PRQ and arrives at
the output if delivery to some postsynaptic neuron is expected at the current
algorithmic timestep. It will (_also_) be pushed to the POQ if it is expected
that a delayed copy will be delivered at a future timestep. At the POQ, the
delay counter of events is decremented by one timestep. At some point, a
special event packet signaling the _end of the algorithmic timestep_ is
intercepted at the output and will trigger a buffer-swap between POQ and PRQ.
When this happens, the events previously held in POQ will be propagated
through PRQ towards the output (if their delay counter has reached a due delay
value for delivery in this new timestep), and/or will be pushed back again to
the POQ for further delaying and delivery at a future timestep. When the delay
counter of an event expires, this event will no longer be pushed to the POQ
and will only be forwarded to the output. Figure 3 exemplifies such a flow of
events through the SCDQ across two layers of an SNN network with delays of
three timesteps.

It is important to note that by contrast to its ancestral architecture [2],
SCDQ makes it possible for an event to “orbit around” and exit the queue at
several timesteps. This way it can support event delays not only per axon but
also per axon-dendrite pair (i.e. per individual synapse), which we will
discuss further in section IV.

Figure 3:  An example of the event flow over three timesteps in a two-layer
SNN with synaptic delays. The maximum delay is 2, and the Shared Circular
Delay Queue is positioned between the two layers. In timestep $t=0$, neurons
$A$ and $B$ spike, and neuron $C$ receives spikes from neurons $A$ and $B$
with a delay value of 0. In timestep $t=1$, neuron $B$ spikes, and neuron $C$
receives a spike from neuron $A$ with a delay value of 0, from neuron $B$ with
a delay value of 0, and from neuron $B$ with a delay value of 1. In timestep
$t=2$, no neuron spikes, and neuron $C$ receives a spike from neuron $A$ with
a delay value of 2, from neuron $B$ with a delay value of 2, and from neuron
$B$ with a delay value of 1.

SCDC consists of six submodules shown in the Delay IP block diagram of Figure
4: the _write controller_ and _read controller_ which get triggered by
external transactions, the _PRQ_ and _POQ_ , the _pruning filter_ , and
_memory_. The _write controller_ is responsible for reading the events from
the input, writing them to the PRQ, and adding to them an initialized delay
counter value. Additionally, it is responsible for swapping the PRQ and POQ
buffers when a special _end-of-timestep_ (EOT) event is intercepted at the
output. The _read controller_ is responsible for reading events from the PRQ
and writing them to the output and the POQ while decreasing the delay counter.
It will also signal the write controller to start the EOT sequence when there
is an EOT event at the output. The PRQ and POQ are FIFO abstractions around
memory buffers available in the memory module and thereby implement the actual
data-path through the SCDQ.

Figure 4:  A mapping on the Seneca platform of a three-layer SNN with 700 wide
input samples, 48 neurons in both hidden layers, 20 neurons in the output
layer, and 60 delays between the hidden layers

####  III-D2 Zero-Skipping Delay-Forwarding

One observes in Figure 1 that the network topology with multiple delay
synapses can become quite intricate. The number of synapses increases linearly
with the maximum number of delay steps, $D$, which we aim to accommodate. In
practical scenarios, weight training-quantization-pruning, and the potential
use of suitable regularization removes a substantial number of synapses,
keeping only those that effectively contribute to the model performance. This
results in a much more compact model for practical deployment on an
accelerator.

In a zero-skipping capable accelerator, weights are typically stored in sparse
matrix format, and a zero weight will not trigger memory IO. A zero activation
will similarly skip fetching weights from memory and computing the partial
MAC, thereby in both cases saving energy and likely improving latency.

When accelerating synaptic delays with SCDQ this zero-skipping decision is not
taken on event generation, but rather after an event exits the queue and is
about to be broadcast to the postsynaptic neurons. This is because even if an
event activation is not useful at the current timestep, it may still be in
future timesteps. This situation may unnecessarily occupy FIFO memory, consume
power for repeated lookups in weight-memory, and affect latency in SCDQ, when
some or all of the postsynaptic neuron connections have zero weights at
certain timesteps.

To limit this overhead a _zero-skiping delay-forwarding_ capability is
implemented by means of the _pruning filter_ of SCDQ. A binary matrix called
$WVU$ (which stands for “weight value useful”) is maintained locally, where
every element represents a delayed axon. $WVU$ has two dimensions: dimension
$I$ representing every presynaptic neuron, and dimension $D$ representing
every delay level. If $WVU_{i,d}=1$, this means that for the current delay
value $d$ and the presynaptic neuron address $i$, at least one of the weights
is a non-zero value. If $WVU_{i,d}=0$, this means that for all $i$ and $d$,
the weights are 0 (which implies that event delivery can be skipped at the
current timestep). Using this method, the SCDQ can determine for every event
in the PRQ if it is useful for the postsynaptic layer (or if it should be
ignored). Figure 5 shows an example of a network with some pruned delayed
axons and the corresponding $WVU$ matrix.

To determine when an event should be removed from the delay queue (i.e. every
next timestep of the event, $WVU_{i,d}$ will be 0), a row of $WVU$, which
corresponds to some presynaptic neuron $i$, can be treated as a binary number.
If we count the number of leading zeros (clz(x)) of this binary number, we
know for which delay counter value $d$ the event does not have to move from
the PRQ to the POQ anymore. For example, in Figure 5, clz($WVU_{A}$) = 1 and
clz($WVU_{B}$) = 0, which means events from neuron $A$ have to stay for 2
timesteps (can be removed at delay counter 1) and events from neuron $B$ do
not have to stay for 3 timesteps (can be removed at delay counter 0).

$WVU=\begin{bmatrix}1&1&0\\\ 0&0&1\end{bmatrix}$

Figure 5:  Example of $WVU$ for a network where delayed axons $A,2$, $B,0$ and
$B,1$ are skipped.

##  IV Results

For the tests on Loihi, we had available a Kapoho Bay USB stick with dual
Loihi chip 128 cores each, and remote access to a Nahuku board (32 chips) via
the Intel Neuromorphic Research Community (INRC). For power measurements on
Loihi, we used Intel’s cloud Loihi server farm, as it is currently the only
way to perform power measurements of neurosynaptic cores. We repeated all the
tests one hundred times and averaged the results to account for variance in
power measurements.

Imec’s Seneca is not taped out in ASIC yet, which is what allowed us to
integrate the delay acceleration circuit and evaluate it. We therefore provide
results from circuit-level simulations and estimate power estimations based on
a netlist provided by Imec, in a 22 nm process from Global Foundry. Energy and
area measurements are acquired using the Cadence Joules Xcelium at 500MHz and
Genus tools, respectively. The Joules tool provides accuracy within 15% of the
sign-off power. The Genus tool is used to estimate the area. Latency, memory,
and fidelity measurements are obtained from the hardware test bench
simulations.

###  IV-A Fidelity of delay models on neuromorphic hardware

The first aspect that we were concerned with verifying, was the fidelity in
terms of model performance, between the PyTorch-trained model (“mother model”)
and the fine-tuned models for the two neuromorphic accelerators. Table II
summarises the rather positive observations. Both quantized models running on
Loihi and Seneca were very close in behavior and final task performance to the
“mother model”. There is about 1% deviation in task accuracy between inference
in PyTorch and inference in the neuromorphic accelerators. Very importantly,
the predictions made by the hardware models were very consistent with those of
the “mother model”. This was well above 90% consistency across all classes,
for all models. A more detailed breakdown per class for the 700-48-48-20
network is shown in Fig 6. The accuracy of 48-48-20 Ax (axonal delay pruning)
is decreased (not the fidelity between software and hardware though) because
of the axon grouping constraint for pruning that penalizes axons containing
the 15 smallest weights (but which could contain some large weights too.
However, the goal is to show later the improvements in energy and latency,
when pruning entire axons.

Last and even more important is the fact that the spike traces and membrane
evolution traces inside the network are also very consistent between “mother
model” and the hardware executing models. This can be verified both in the
numbers reported Table II for the entire test-set and the three models, and
also visually in Fig 7 and 8 for one example data point. It means that the
software model can provide us with very reliable information about the
anticipated energy per inference and memory use on the neuromorphic platform
without even running the hardware model (since these traces are a proxy for
the number of synaptic operations).

TABLE II: Fidelity of Loihi/Seneca run models against the PyTorch trained “mother-model” Model | Pytorch | Loihi | Seneca
---|---|---|---
Model accuracy
700-48-48-20 | 87% | 87% | 86%
700-32-32-20 | 82% | 83% | 81%
700-24-24-20 | 83% | 81% | 82%
700-48-48-20 Ax | 76% | 75% | 76%
Prediction consistency against Pytorch
700-48-48-20 | 100% | 97% | 93%
700-32-32-20 | 100% | 95% | 97%
700-24-24-20 | 100% | 93% | 98%
700-48-48-20 Ax | 100% | 92% | 94%
Avg spike count per inference per layer
| h1 | h2 | h1 | h2 | h1 | h2
700-48-48-20 | 545.32 | 534.55 | 524.39 | 531.14 | 544.71 | 534.25
700-32-32-20 | 400.99 | 384.61 | 398.33 | 365.15 | 401.18 | 384.85
700-24-24-20 | 273.86 | 311.19 | 272.48 | 300.75 | 271.99 | 307.9
Figure 6: Confusion matrices for PyTorch trained “mother-model” and
Loihi/Seneca run models for the 700-48-48-20 network. Figure 7: Comparison of
spike traces between pytorch “mother-model” and the one executed on Seneca and
Loihi for SHD testset sample X. Figure 8: Comparison of Vmem trace between
pytorch “mother-model” and the one executed on Seneca and Loihi for SHD
testset sample X. Figure 9: Effect of weight quantization on final accuracy.
All test-set (2264 samples) are considered.

###  IV-B Power, Energy, Latency, Memory measurements

In Table III we report (average) hardware measurements per inference in Loihi,
in Seneca with Delay IP, and in Seneca without Delay IP (that is delays
implemented in software on the RISC-V controller). The power consumption
reported in the table includes only the total power of the neurosynaptic
cores, excluding the I/O and peripherals. Energy is calculated using dynamic
power consumption, to exclude the high 74.4 mW static power consumption of the
Lakemont x86 management cores of Loihi. The static power consumption of Seneca
is 462 $\mu W$. Comparing the middle and right columns justifies the circuit-
based implementation of SCDQ in Seneca as it improves energy efficiency and
latency by a significant amount. The energy efficiency increases between
$3.5\times$ (700-48-48-20) and $3.1\times$ (700-24-24-20). Similarly, latency
decreases between $4.3\times$ (700-48-48-20) and $3.5\times$ (700-24-24-20).
In other words, the benefits increase with the total activation volume (seen
in larger networks). For the axonal pruned network (700-48-48-20 Ax), both
energy efficiency and latency improve by approximately $1.4\times$ compared to
the per individual synapse pruned network (700-48-48-20). This is because the
activation sparsity is higher for 700-48-48-20 Ax than for 700-48-48-20.

As a proxy comparison for the two different hardware implementations of
synaptic delays, namely Ring Buffer in Loihi, versus SCDQ (improved shared
queue) in Seneca, the energy efficiency of Seneca (SCDQ) appears approximately
$1.2-1.9\times$ lower, but note that this involves 1 core in Loihi versus 3
cores on Seneca. But the gap is closing as the network size increases, which
reveals the better scalability of the SCDQ and/or the costly contribution of
the RISC-V controller in Seneca: the larger the network, the more compute work
gets allocated to the vector-pipeline of neuro co-processors (NPEs), compared
to the work the RISC-V controller has to do.

What is also very interesting is the effect of the accelerated synaptic delays
with SCDQs on the inference latency. On Seneca, both with the hardware
implementation and the RISC-V implementation of SCDQ, the latency decreases
with the network size (due to fewer activations), while it, surprisingly,
remains constant on Loihi’s Ring Buffers. And for the hardware accelerated
implementation, it is consistently less than $0.5\times$ that of Loihi,
despite the larger number of cores used and routing between them (i.e., longer
data path).

To make the comparison more equitable we performed an additional experiment
where the 700-48-48-20 network was distributed across three cores in Loihi
too. In this case (Table IV) energy consumption increases by 35% and memory
use by a factor of $1.15\times$.

In Seneca, the shared queues (SCDQs) contribute only 2% - 3% to its energy
consumption, with the remaining 97% - 98% coming from the cores processing (of
which 67% - 82% of this energy consumption is related to pre- and post-
processing events in the RISC-V controller of each core). Similarly, out of
the 3.3Mb memory consumption, RISC-V instructions take up 0.5Mb, while neural
processing operations use up 2.6Mb. It’s worth noting that the actual energy
and memory consumption of neural processing operations (14.6uJ/2.6Mb) are very
close to the estimates generated using the methodology introduced in [21]
(14.48uJ/2.2Mb). Fig 10, provides a more detailed breakdown of the energy
boxplots for the per-class data points in the test set for Seneca for the
network 700-24-24-20.

TABLE III: Average hardware measurements per inference, DIP = Delay IP, Energy calculated using dynamic power consumption (on Loihi this does not include the Lakemont cores.) Measurement | Loihi (1c) | Seneca (3c) w/ SCDQ | Seneca (3c) w/o SCDQ
---|---|---|---
Network: 700-48-48-20
Energy |  28.4 $\mu J$ |  43.6 $\mu J$ |  152 $\mu J$
Latency |  9.1 $ms$ |  4.25 $ms$ |  18.3 $ms$
Memory |  1.96 $Mb$ |  3.38 $Mb$ |  3.34 $Mb$
DIP energy | NA |  0.98 $\mu J$ |  0 $\mu J$
Network: 700-32-32-20
Energy |  18.3 $\mu J$ |  29.5 $\mu J$ |  92.4 $\mu J$
Latency |  9.1 $ms$ |  3.34 $ms$ |  13.6 $ms$
Memory |  1.48 $Mb$ |  2.33 $Mb$ |  2.29 $Mb$
DIP energy | NA |  0.77 $\mu J$ |  0 $\mu J$
Network: 700-24-24-20
Energy |  12.5 $\mu J$ |  23.8 $\mu J$ |  73.3 $\mu J$
Latency |  9.1 $ms$ |  2.81 $ms$ |  9.81 $ms$
Memory |  1.23 $Mb$ |  2.07 $Mb$ |  2.05 $Mb$
DIP energy | NA |  0.62 $\mu J$ |  0 $\mu J$
Network: 700-48-48-20 Ax
Energy |  25.2 $\mu J$ |  31.4 $\mu J$ | NA
Latency |  10.0 $ms$ |  3.03 $ms$ | NA
Memory |  1.96 $Mb$ |  3.36 $Mb$ | NA
DIP energy | NA |  0.72 $\mu J$ | NA
TABLE IV: Hardware measurements for executing inference with model 700-48-48-20 using 3 cores on Loihi and Seneca HW measurement | Loihi (3c) | Seneca (3c)
---|---|---
model: 700-48-48-20
Energy per inference | 38.4 $\mu J$ | 43.6 $\mu J$
Latency per inference | 9.1 $ms$ | 4.25 $ms$
Memory consumption | 4.2 $Mb$ | 3.38 $Mb$
Synaptic Delay energy | NA | 0.98 $\mu J$
Figure 10: Energy consumption per inference by class on Seneca.

###  IV-C Final accuracy and effect of reduced bit precision

We report the accuracy on the entire test set (2264 samples) and the effect of
quantizing with different bit precisions for the three base models implemented
on Loihi. As observed in Fig. 9 and consistent with the fidelity results, the
degradation in accuracy of the mapping form Pytorch to Loihi is negligible.
Interestingly, the effect of reducing the bit precision is, at most less than
3% percent for up to 4 bits, leading (potentially) to a further reduction of
the memory footprint with little cost. The maximum accuracy obtained in Loihi
for the 700-48-48-20 model is 89.04%

##  V Discussion

Regarding the cost of supporting synaptic delays in a neural accelerator,
there are two sources of overhead. First delay parameterization involves
extending the weight matrix structure from 2D to 3D (2D weight matrix for each
delay value). It has dimensions $D\times I\times J$, where $D$ is the delay
resolution (that is, the number of distinct discrete values), $I$ is the
number of pre-synaptic neurons, and $J$ is the number of post-synaptic
neurons. Pruning during training can serve to limit or reduce this overhead
(particularly when the weight matrix can be stored in compressed form).
Pruning an axon removes a set of delay synapses towards post-synaptic layer
neurons (reducing the cardinality of one of the dimensions of the weight
matrix), and pruning a dendritic branch alone removes an individual synaptic
connection between a pre-post neuron pair.

Second, in most neuromorphic architectures, delays are implemented as FIFO
queues or delay lines placed either at every neuron or shared among synaptic
connections. For example, in [5, 33, 25] a _Ring Buffer_ places a circular
FIFO queue placed at each postsynaptic neuron where dendritic weights
accumulate. Each _slot_ of the Ring Buffer accumulates weights for a different
timestep. At the end of a timestep, the slot corresponding to the current
timestep is added to the membrane potential of the corresponding postsynaptic
neuron. Subsequently, the Ring Buffer shifts to the next timestep, and the
slot from the current timestep becomes the slot for the maximum delay. The
number of delay levels is constrained by the size (number of slots) of the
Ring Buffer. With only one Ring Buffer per postynaptic neuron, the total
memory overhead is the product of the number of postynaptic neurons $J$ and
the number of delay levels $D$, scaling with $\mathcal{O}(J\cdot D)$ [16].

On the other hand, a _Shared Queue_ [2], of which SCQD is an extension, shares
a group of FIFOs in a linear cascade arrangement across the synapses
(presynaptic and postsynaptic neuron pairs of two layers). The number of FIFOs
in the cascade equals the maximum number of discrete delay levels $D$. Every
event triggered at a presynaptic neuron from an axon with a given delay,
enters the Shared Queue at the FIFO corresponding to the number of timesteps
it needs to wait before delivery. At the end of a timestep, all events in
every FIFO shift to the next FIFO in the cascade belonging to the next
relative timestep, and all events in the FIFO belonging to the current
timestep are transmitted to the postsynaptic neurons. The total memory usage
depends on the minimum activation sparsity of the network (which can be biased
through model training). Assuming a minimum activation sparsity of $\alpha$,
where $\alpha=1$ implies that every presynaptic neuron is activated and
$\alpha=0$ implies that none are activated, the total memory overhead is
calculated as $\alpha\cdot
I\cdot\left(\sum_{d=1}^{D}(D-d)\right)=\frac{1}{2}\cdot\alpha\cdot
I\cdot(D^{2}+D)$, where $I$ is the number of presynaptic neurons and $D$ is
the number of delay levels. This memory overhead scales as
$\mathcal{O}(\alpha\cdot I\cdot D^{2})$. In this synaptic delay model, only
axonal delays are supported and therefore an event enters and exits the Shared
Delay Queue only once.

The SCDQ introduced in this paper and employed in [3] is an evolution of the
Shared Queue in [2]. SCDQ has memory overhead of $\alpha\cdot I\cdot(2\cdot
D-1)$, scaling with $\mathcal{O}(\alpha\cdot I\cdot D)$. By reference to
TrueNorth’s[2] constraints of 16 timesteps of delay, 256 neurons, and for
sparsity $\alpha=1$ (no spasity), TrueNorth’s Shared Delay Queue needs queue
capacity for $34816$ events, while SCDQ only requires storage for $7936$
events. In the implementation of the SCDQ we used, each event has a bit width
of 16 bits. By comparison to a Ring Buffer structure using as a reference
Loihi’s[5] constraints of 64 delay time steps, 48 neurons, and 8 bits per
weight, the additional memory overhead of Loihi is only $24576$ bits, which is
less than the $97536$ bits of the Delay IP. However, this comparison assumes
no activation sparsity ($\alpha=1$), and the memory overhead of Ring Buffers
does not scale with activation sparsity. If $\alpha\leq 0.25$, the SCDQ has a
lower memory overhead than Loihi’s Ring Buffers. SpiNNaker[33] also uses Ring
Buffers and has a constraint of 16-time steps of delay, 256 neurons, and
16-bit weights per neuron, resulting in a memory overhead of $65536$ bits.
Assuming $\alpha=1$, the SCDQ has a memory overhead of $126976$ bits in this
case and when $\alpha\leq 0.5$, SCDQ is more memory efficient than SpiNNaker
too.

To illustrate how SCDQ improves upon the _vanilla_ Shared Delay Queue
structure [2], in Figure 11, we provide a worst-case estimate (assuming dense
activations and no delay pruning) between two fully connected layers. The
figure illustrates the buffer capacity required for both a Shared Delay Queue
and SCDQ, as the number of delay levels increases and as the number of
postsynaptic neurons increases.

Figure 11: Required memory for shared delay queue vs shared circular delay
queue

Finally, considering area overhead, in the initial implementation of SCDQ we
used flip-flops. To reduce the total area, flip-flop memory was later replaced
with a 2048-word 16-bit SRAM memory, with enough capacity for the observed
maximum of 1596 events in the queues. This resulted in an 81% reduction in
total area, with a total of 15463 $\mu m^{2}$ for the Delay IP (see Table V).
With this area improvement the area cost of SCDQ reduces from
$\frac{81624}{472400}=17\%$ of the area one Seneca core down to a mere
$\frac{15463}{472400}=3\%$ only.

TABLE V: Area Savings with SRAM Memory | Combinational | Flip-Flop | SRAM | Total
---|---|---|---|---
FF |  16885 $\mu m^{2}$ | 21% |  64739 $\mu m^{2}$ | 79% |  0 $\mu m^{2}$ | 0% |  81624 $\mu m^{2}$
SRAM |  2287 $\mu m^{2}$ | 15% |  4557 $\mu m^{2}$ | 29% |  8618 $\mu m^{2}$ | 56% |  15463 $\mu m^{2}$
Area saved | 81%

##  VI Conclusion

In this paper, we have proposed a framework for training and deploying highly
performing spiking neural network models (SNNs) with synaptic delays on
digital neuromorphic hardware. The framework co-optimizes both synaptic
weights and delays and takes hardware platform constraints into account. We
have also introduced a new hardware data structure, SCDQ, for memory- and
area-efficient acceleration of synaptic delays that combines the ideas of ring
buffers and shared queues. We evaluated our contributions with two
neuromorphic digital hardware platforms: Intel’s Loihi and Imec’s Seneca (in
which SCDQ was integrated). Our evaluation with several models of varying
sizes trained for the SHD classification task, affirms not only the efficacy
and hardware efficiency of synaptic delays but also our ability under the
proposed training framework to produce hardware models that perform on par
with their software counterparts on digital hardware accelerators.

This work demonstrates the first successful application of hardware-aware
models parameterized with synaptic delays on multi-core neuromorphic hardware
accelerators.

## Acknowledgments

This work was funded by EU Horizon grant 101070679 ”NimbeAI” and EU H2020
grant 871501 ”Memscales”.

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