# Analysis on One-Stage SSHC Rectifier for Piezoelectric Vibration Energy
Harvesting

Sijun Du The author is with the Department of Electrical Engineering and
Computer Sciences, University of California at Berkeley, Berkeley, CA, 94720,
USA.

###### Abstract

Conventional SSHI (synchronized switch harvesting on inductor) has been
believed to be one of the most efficient interface circuits for piezoelectric
vibration energy harvesting systems. It employs an inductor and the resulting
RLC loop to synchronously invert the charge across the piezoelectric material
to avoid charge and energy loss due to charging its internal capacitor
($C_{P}$). The performance of the SSHI circuit greatly depends on the inductor
and a large inductor is often needed; hence significantly increases the volume
of the system. An efficient interface circuit using a synchronous charge
inversion technique, named as SSHC, was proposed recently. The SSHC rectifier
utilizes capacitors, instead of inductors, to flip the voltage across the
harvester. For a one-stage SSHC rectifier, one single intermediate capacitor
($C_{T}$) is employed to temporarily store charge flowed from $C_{P}$ and
inversely charge $C_{P}$ to perform the charge inversion. In previous studies,
the voltage flip efficiency achieves 1/3 when $C_{T}=C_{P}$. This paper
presents that the voltage flip efficiency can be further increased to approach
1/2 if $C_{T}$ is chosen to be much larger than $C_{P}$.

##  I Introduction

Along with the development of Internet of Everything, wireless sensing
networks (WSN) act as essential roles interconnecting between the real world
and the Internet. Although electrochemical batteries have remained the primary
energy sources for such systems due to the high energy density, certain
sensors and sensor systems require to operate over significant periods of time
much longer than the lifetime of electrochemical batteries. Battery usage may
be both impractical and costly due to the requirement for periodic re-charging
and/or replacement [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19]. In order to address this challenge and extend the operational
lifetime of wireless sensors, there has been an emerging research interest on
harvesting ambient vibration energy.

Piezoelectric materials are widely used in vibration energy harvesters (VEH)
as mechanical-to-electrical transducers due to their relatively high power
density, scalability and compatibility with conventional integrated circuit
technologies [20, 21, 22, 23, 24]. MEMS technology is also widely used for
piezoelectric vibration energy harvesters and different kinds of resonant
sensors [25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
42, 43, 44, 45]. A typical piezoelectric VEH can provide a power density of
around 10 - 500 $\mathrm{\SIUnitSymbolMicro
W}\text{${}\cdot{}$}{\mathrm{cm}}^{-2}$, which sets a significant constraint
on designing the associated power conditioning interface circuit [46, 47, 48].
The interface circuit not only must consume ultra low power, but it also
should be able to recover the power as effectively as possible from the
piezoelectric transducer (PT). Full-bridge rectifiers are widely used in
commercial energy harvesting systems due to their simplicity and stability;
however, they set high threshold voltages for the generated energy to be
extracted by the circuit [49, 50, 51, 52, 53, 54, 55].

$V_{N}$$V_{P}$$I_{P}$$C_{P}$$R_{P}$$V_{D}$$C_{S}$$V_{PT}$$V_{S}$ ((a)) The
equivalent circuit of a piezoelectric VEH connected to a full-bridge rectifier

$I_{p}$$V_{PT}$$time$$time$$V_{S}+2V_{D}$$-(V_{S}+2V_{D})$ ((b))
Representative waveforms for the current ($I_{P}$) and voltage ($V_{PT}$)

Figure 1: Full-bridge rectifier for piezoelectric VEH and the associated
waveforms

Fig. 1 shows a full-bridge rectifier connected with a piezoelectric transducer
(PT) and the associated waveforms. While vibrating at or close to its
resonance, a piezoelectric VEH can be modeled as a current source $I_{P}$
connected in parallel with a plate capacitor $C_{P}$ and a resistor $R_{P}$.
In order to transfer the generated energy from the PT to the storage capacitor
$C_{S}$, the voltage across the PT $V_{PT}$ should attain $V_{S}+2V_{D}$ or
$-(V_{S}+2V_{D})$. Hence the energy used to charge the internal capacitor
$C_{P}$ from $V_{S}+2V_{D}$ to $-(V_{S}+2V_{D})$ (or vice-versa) is wasted.
The wasted charge in a half vibration cycle can be expressed as:

$\centering Q_{wasted}=2C_{P}(V_{S}+2V_{D})\@add@centering$ (1)

Therefore, the peak-to-peak open-circuit voltage generated by the PT,
$V_{pp(open)}$, should be greater than $2(V_{S}+2V_{D})$ to make sure that
there is remaining charge flowing into $C_{S}$ after $Q_{wasted}$ is wasted.
In large excitation levels, the charge loss $Q_{wasted}$ may take a small part
of the total charge generated by the PT. However, in small excitation levels
where $V_{pp(open)}$ is below or marginally higher than $2(V_{S}+2V_{D})$,
there will be no charge or very little charge can be transferred to $C_{S}$.
The waveforms in Fig. 1 illustrate the charge loss due to charging $C_{P}$
from $\pm(V_{S}+2V_{D})$ to $\mp(V_{S}+2V_{D})$.

##  II SSHC interface circuit

In order to improve the power efficiency and minimize the charge waste due to
charging $C_{P}$, many active interface circuits have been reported, including
MPPT (maximum power point tracking) [56, 57, 58, 59, 60, 61, 62, 63, 64, 65,
66, 67], active rectifications, etc [68, 69, 70, 71, 72, 73, 74, 75, 76].
Among all interface circuits for piezoelectric VEH, SSHI (Synchronized Switch
Harvesting on Inductor) rectifier, proposed by Badel et al [77], is one of the
most efficient circuits with nearly no charge waste (if the inductor is chosen
large enough). It performs synchronous charge inversion on $C_{P}$ through an
RLC system using an inductor controlled by synchronized switches. However, the
limitation of the SSHI rectifier is the need for a large off-chip inductor.
This section presents the design of a rectifier, named as synchronized switch
harvesting on capacitor (SSHC), which performs the energy extraction using
switched capacitors instead of inductors.

Fig. 2 shows the design of a one-stage SSHC rectifier where a temporary charge
storage switched capacitor $C_{T}$ is used to synchronously flip the voltage
$V_{PT}$ [56]. In order to perform the charge inversion, five analogue
switches driven by three pulse signals ($\phi_{p}$, $\phi_{0}$ and $\phi_{n}$)
are used. The three non-overlapping switching signals are synchronously
generated to turn ON the five switches sequentially in a given order. The
order of the three pulses depends on the polarization of the voltage $V_{PT}$.

$C_{P}$$I_{P}$$R_{P}$$V_{P}$$V_{N}$$V_{PT}$$V_{D}$$C_{S}$$+$$-$$V_{S}$$\phi_{0}$$\phi_{p}$$C_{T}$$+$$-$$V_{T}$$\phi_{p}$$\phi_{n}$$\phi_{n}$
Figure 2: Proposed interface circuit Figure 3: Working principle of proposed
SSHC rectifier to perform

Fig. 3 shows the working principle of the one-stage SSHC rectifier. Before
$I_{P}$ reaches zero-crossing point, the generated charge by the piezoelectric
transducer flows into the storage capacitor $C_{S}$, as shown in first sub-
figure. The polarization of voltage across the piezoelectric transducer is
assumed that $V_{PT}>0$; hence the top and the bottom diodes are conductive
and $V_{PT}=V_{S}+2V_{D}$ during this time. At the moment of $I_{P}$ zero-
crossing point, a pulse $\phi_{p}$ is generated to let some charge in $C_{P}$
flow into $C_{T}$. At the next phase, $\phi_{0}$ turns ON the switch across
the piezoelectric transducer and clears the remaining charge in $C_{P}$. At
the phase of $\phi_{n}$, $C_{T}$ is connected to the piezoelectric transducer
in an opposite sense, hence $V_{PT}$ goes to a negative value and a part of
charge is inverted as a result. After the phase $\phi_{n}$, the polarization
of $I_{P}$ changes and $V_{PT}$ goes to $-(V_{S}+2V_{D})$ until the middle two
diodes become conductive to start charging $C_{S}$ again. In the voltage
inversion process shown in Fig. 3, the order of the three signals is
$\phi_{p}\rightarrow\phi_{0}\rightarrow\phi_{n}$ because $V_{P}>V_{N}$ before
the zero-crossing moment and $V_{PT}$ is aimed to be inverted from
$V_{S}+2V_{D}$ to a negative value. While in the other case of $V_{P}<V_{N}$,
the order of the three signals should be
$\phi_{n}\rightarrow\phi_{0}\rightarrow\phi_{p}$.

((a)) Simulated waveforms of $V_{PT}$, $\phi_{p}$, $\phi_{0}$ and $\phi_{n}$

((b)) Zero-crossing moment while $V_{PT}$ is inverted from ‘+’ to ‘-’

((c)) Zero-crossing moment while $V_{PT}$ is inverted from ‘-’ to ‘+’

Figure 4: Simulated waveforms while $V_{PT}$ is being inverted

Fig. 4(a) shows the simulated waveforms of $V_{PT}$, $\phi_{p}$, $\phi_{0}$
and $\phi_{n}$ for five periods of $I_{P}$. For each zero-crossing moment, the
three pulse signals are generated sequentially and it can be seen that
$V_{PT}$ is partially inverted. Fig. 4(b) presents the voltage inversion in
more detail while $V_{PT}$ is inverted from positive to negative. In this
case, the switch $\phi_{p}$ is first turned ON and the capacitors, $C_{P}$ and
$C_{T}$ are connected in the same polarization. From the waveform of $V_{PT}$,
it can be seen that it goes down a little because the charge in $C_{P}$ is
shared between the $C_{P}$ and $C_{T}$. At the $\phi_{0}$ phase, $C_{P}$ is
shorted and the remaining charge in it is cleared; hence $V_{PT}$ goes to
$0\text{\,}\mathrm{V}$. At the $\phi_{n}$ phase, $C_{T}$ and $C_{P}$ are
connected in an polarization opposite to the phase $\phi_{p}$. At this state,
some charge in $C_{T}$ flows into $C_{P}$ until they have the same voltage
values across them and $V_{PT}$ goes to a negative value as a result. In the
simulation, $V_{PT}$ equals to $2.4\text{\,}\mathrm{V}$ before the zero-
crossing moment and it goes to $-0.8\text{\,}\mathrm{V}$ after the inversion
process. Fig. 4(c) shows waveforms while $V_{PT}$ is inverted from negative to
positive and the order that the three pulse signals to be generated is
$\phi_{n}\rightarrow\phi_{0}\rightarrow\phi_{p}$. In addition to the order,
the three signals should also be non-overlapping to avoid any unwanted charge
flow.

###  II-A Performance analysis with $C_{T}=C_{P}$

As discussed, the SSHC rectifier is able to invert some charge stored in
$C_{P}$ and it is useful to calculate how much charge is inverted and the
condition to achieve this performance. Before a zero-crossing moment, it is
assumed that $V_{PT}$ is positive and it equals to $V_{S}+2V_{D}$, noted as
$V_{0}=V_{S}+2V_{D}$ for simplicity. $C_{T}$ is assumed to have no charge at
the beginning hence $V_{T}=$0\text{\,}\mathrm{V}$$. At the first zero-crossing
moment of $I_{P}$, $\phi_{p}$ is first be turned ON because $V_{PT}$ is
positive. $C_{P}$ and $C_{T}$ are connected and the charge flows into $C_{T}$
until the voltages across the two capacitors are equal. As the total charge
keeps unchanged, the voltage across $C_{P}$ and $C_{T}$ at the end of the
first phase is:

$\centering V_{PT1}=V_{T1}=\frac{C_{P}}{C_{P}+C_{T}}V_{0}\@add@centering$ (2)

At the second phase, a pulse $\phi_{0}$ is generated. The remaining charge in
$C_{P}$ is cleared and the charge in $C_{T}$ is unchanged. Hence, the voltage
across $C_{P}$ and $C_{T}$ at the end of the second phase is:

$\centering\begin{split}V_{PT2}&=0\\\
V_{T2}&=V_{T1}=\frac{C_{P}}{C_{P}+C_{T}}V_{0}\end{split}\@add@centering$ (3)

At the phase $\phi_{n}$, $C_{T}$ is connected with $C_{P}$ again in an
opposite sense to charge $C_{P}$ to a negative voltage. As the total charge in
the two capacitors is the remaining charge in $C_{T}$ shown in (3), hence the
voltages of $V_{PT}$ and $V_{T}$ at the end of this phase are:

$\centering\begin{split}V_{PT3}=-V_{T3}=-\frac{C_{P}C_{T}}{(C_{P}+C_{T})^{2}}V_{0}\end{split}\@add@centering$
(4)

It can be seen that $V_{PT}$ is a negative value at the end of the zero-
crossing moment. By setting the derivative of the expression in (4) at 0, it
can be found that $V_{PT3}$ attains its minimum value while $C_{T}=C_{P}$.
Therefore, the minimum value of $V_{PT}$ at the end of the first charge
inversion is:

$\centering V_{PT3}=-V_{T3}=-\frac{1}{4}V_{0}\ \ \ \ (while\
C_{P}=C_{T})\@add@centering$ (5)

The resulting voltage in (5) is obtained after the first charge inversion and
the initial voltage across $C_{T}$ is assumed at $0\text{\,}\mathrm{V}$ at the
beginning. However, before the second zero-crossing moment, $V_{T}$ is no
longer $0\text{\,}\mathrm{V}$, but $\frac{1}{4}V_{0}$. $V_{PT}$ now equals to
$-V_{0}$ because it needs to inverted from negative to positive. Assuming
$C_{T}=C_{P}$ is chosen for future calculations, $V_{PT}$ and $V_{T}$ values
after each phase of $\phi_{n}$, $\phi_{0}$ and $\phi_{p}$ at the second charge
inversion stage are:

$\centering\begin{split}before\ \phi_{n}:\ \ &V_{PT}=-V_{0},\ \
V_{T}=\frac{1}{4}V_{0}\\\ \Rightarrow after\ \phi_{n}:\ \
&V_{PT}=-V_{T}=-(\frac{1}{4}+1)\frac{1}{2}V_{0}\\\ \Rightarrow after\
\phi_{0}:\ \ &V_{PT}=$0\text{\,}\mathrm{V}$,\ \
V_{T}=(\frac{1}{4}+1)\frac{1}{2}V_{0}\\\ \Rightarrow after\ \phi_{p}:\ \
&V_{PT}=V_{T}=(\frac{1}{4}+1)\frac{1}{4}V_{0}=((\frac{1}{4})^{2}+\frac{1}{4})V_{0}=\frac{5}{16}V_{0}\end{split}\@add@centering$
(6)

As $\frac{5}{16}>\frac{1}{4}$, more charge is inverted in the second zero-
crossing moment compared to the first one. Due to the accumulation of
remaining charge in $C_{T}$, the resulting $|V_{PT}|$ at the end of the
$n^{th}$ inversion stage is:

$\centering\begin{split}|V_{PT}|&=((\frac{1}{4})^{n}+\dots+(\frac{1}{4})^{2}+\frac{1}{4})V_{0}=\sum_{\begin{subarray}{c}1\leq
i\leq
n\end{subarray}}(\frac{1}{4})^{i}V_{0}=\frac{\frac{1}{4}-(\frac{1}{4})^{n}}{1-\frac{1}{4}}V_{0}\\\
\Rightarrow&\lim_{n\to\infty}|V_{PT}|=\frac{1}{3}V_{0}\end{split}\@add@centering$
(7)

While $n$ tends to infinity, $|V_{PT}|_{n\rightarrow\infty}=\frac{1}{3}V_{0}$,
which means one third of charge can be inverted theoretically while
$C_{T}=C_{P}$. Fig. 5 shows the simulated voltage flip efficiencies for the
first 10 flip cycles when $C_{T}=C_{P}$. It can be seen that the flip
efficiency goes fast to approach 1/3 after several cycles.

Figure 5: Voltage flip efficiency for the first 10 flip cycles when
$C_{T}=C_{P}$.

###  II-B Performance analysis with $C_{T}>>C_{P}$

Since $C_{T}$ is assumed to be off-chip implemented, it is possible to achieve
$C_{T}>>C_{P}$ with a tiny SMD capacitor for $C_{T}$ because $C_{P}$ is
usually as small as several nF. When $C_{T}>>C_{P}$, the charge stored in
$C_{T}$ will accumulate much slower. However, after sufficient number of flip
cycles, voltage across $C_{T}$ will approach half of the voltage across
$C_{P}$ before flipping starts. Since $C_{T}$ is very large, the voltage
across $C_{T}$ barely decreases after charge is dumped back from $C_{T}$ to
$C_{P}$ to finish voltage flipping. In this case, the remaining voltage across
$C_{P}$ keeps almost constant. Hence, the voltage flip efficiency can be as
high as 50% in this case.

Figure 6: Voltage flip efficiency for the first 300 flip cycles when
$C_{T}=100C_{P}$.

Fig. 6 shows the simulated voltage flip efficiencies for the first 300 flip
cycles when $C_{T}>>C_{P}$. In this simulation, $C_{T}=100C_{P}$ is used. From
this figure, it can be seen that the flip efficiency takes much more flip
cycles to achieve the optimal level compared to the Fig. 5. This is because
$C_{T}$ is much larger now and it needs more charge from $C_{P}$ to charge
$C_{T}$ to the sufficient level of voltage. The figure shows the voltage flip
efficiency approaches 50%, which is higher than 1/3, simulated for the case
$C_{T}=C_{P}$.

##  III Conclusion

An SSHC (synchronized switch harvesting on capacitor) rectifier with one
switched capacitor for piezoelectric vibration energy harvesters is analyzed
in this paper. Similar to most of other highly-efficient active rectifiers
(such as SSHI), it performs synchronous voltage inversion across the
piezoelectric transducer every half cycle to minimize energy loss due to
discharging and charging the internal capacitor. However, different from those
rectifiers, the SSHC rectifier does not employ any inductor to perform the
voltage inversion; it utilizes a capacitor instead. In previous studies, The
capacitance of the employed capacitor is suggested to be equal to the internal
capacitor of the piezoelectric transducer in order to achieve the performance
to invert 1/3 of charge. In this paper, the voltage flip efficiency is
simulated to be up to 50% when the capacitance of the switched capacitor
$C_{T}$ is much higher than the internal capacitor of the piezoelectric
transducer $C_{P}$.

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