# Reducing strain fluctuations in quantum dot devices by gate-layer stacking

Collin C. D. Frink  Department of Physics, University of Wisconsin-Madison,
Madison, Wisconsin 53706, USA  Benjamin D. Woods  Department of Physics,
University of Wisconsin-Madison, Madison, Wisconsin 53706, USA  Merritt P.
Losert  Department of Physics, University of Wisconsin-Madison, Madison,
Wisconsin 53706, USA  E. R. MacQuarrie  Department of Physics, University of
Wisconsin-Madison, Madison, Wisconsin 53706, USA  Mark Friesen  Department of
Physics, University of Wisconsin-Madison, Madison, Wisconsin 53706, USA  M. A.
Eriksson  Department of Physics, University of Wisconsin-Madison, Madison,
Wisconsin 53706, USA

###### Abstract

Nanofabricated metal gate electrodes are commonly used to confine and control
electrons in electrostatically defined quantum dots. However, these same gates
impart a complicated strain geometry that affects the confinement potential
and potentially impairs device functionality. Here we investigate strain-
induced fluctuations of the potential energy in Si/SiGe heterostructures,
caused by (i) lattice mismatch, (ii) materials-dependent thermal contraction,
and (iii) deposition stress in the metal gates. By simulating different gate
geometries, ranging from simple to realistically complicated, and including
features like overlapping metal and oxide layers, we can explain most observed
strain features. In particular, we show that strain-induced potential
fluctuations can be suppressed by employing overlapping gates that cover the
whole active region, when the oxide layers are thin. These results suggest
that strain effects should not present a serious challenge to qubit uniformity
when following simple design rules.

##  I Introduction

Gate-defined quantum dots in Si/SiGe quantum wells are a promising platform
for large-scale quantum computation [1, 2, 3], where recent demonstrations of
single and two qubit gates have exceeded error correction thresholds [4, 5,
6]. While these achievements represent important milestones, useful quantum
hardware will require vast arrays of reliable, low-error qubits. Scaling up
will require a level of qubit reproducibility and uniformity on par with
transistors in modern integrated circuits [7]. Such uniformity has been
achieved for certain dot properties like orbital and charging energies [8],
but remains a challenge for properties like the valley energy splitting [9,
10], due to the inherent atomistic disorder of the SiGe random alloy [11, 12].
Some types of non-uniformity are potentially reconfigurable, such as
interfacial trapped charge, which can modify the local electrostatics [13] and
cause the formation of accidental quantum dots [14, 15]. Other sources of
variability (e.g., valley splitting) are immutable, and are prescribed during
heterostructure growth or device fabrication.

Figure 1: Schematic illustration of strain fluctuation suppression by gate-
layer stacking. a Non-uniform strain in a Si/SiGe quantum well (blue/green) is
induced beneath a metallic wire (gray) upon cooling the device due to thermal
expansion mismatch between the materials. Red line indicates the plane of the
two-dimensional electron gas (2DEG). b Same as a with an additional metallic
wire placed transversely to the original wire. Provided the oxide layer (dark
gray) between the metallic wires is sufficiently thin, the addition of the top
wire suppresses the local strain fluctuations in the quantum well.

Local strain fields can significantly affect the in-plane confinement
potential of quantum dots [16]. These strains arise predominantly from the
structural or geometrical features of a device, such as metal electrodes or
etched regions, which are intentionally patterned atop the quantum well that
houses the qubits. Such structures are carefully designed to provide
electrostatic control of the qubit environment. However, the strains arising
from these gates can have a very different effect on the confinement potential
than the intended one, resulting in energy variations on the order of meV [17,
18], which is comparable to the electrostatic confinement. Such fluctuations
can cause accidental quantum dots [16], and can affect exchange interactions
between electrons in neighboring dots [3, 19, 20, 21]. Despite such compelling
arguments to treat the strain and electrostatics on equal footing, this is
seldom done in experiments or simulations.

In this work, we numerically investigate strain effects arising from three
main sources: (i) lattice mismatch between the Si in the quantum well and the
SiGe alloy of the barriers [22], (ii) unequal contractions of different
materials as the device is cooled [23], and (iii) deposition stress, which
occurs in a metal when it is deposited on a semiconductor or an oxide [24].
These strain calculations are used to estimate conduction-band energies in the
Si quantum well, as explained in Methods, from which we deduce the locally
varying confinement potential. (In the Supplementary Materials, we also
compute the corresponding electrostatic potential.) Beginning with simple gate
structures, we work our way up to realistic devices measured in qubit
experiments [25, 26]. Due to the long-range nature of the strain fields, our
simulations exhibit both short-range variations that mirror the locally
varying gate structure, as well as smoother, averaged behavior arising from
multiple gates, which is manifested (for example) as edge effects.

Figure 2: Strain simulations of a single-wire geometry. a,b 3D and cross-
sectional views, respectively. From bottom to top, the thicknesses of the
Si0.7Ge0.3 virtual substrate (green), Si quantum well (blue), Si0.7Ge0.3
spacer (green), and insulating Al2O3 (dark gray) layers are 2 $\mu$m, 9 nm, 30
nm, and 10 nm, respectively. A metal wire (light gray) of height 60 nm and
variable width $w$ is formed of Al or Pd. The wire is covered on the top and
sides by a thin 2 nm Al2O3 layer (dark gray; not shown in a, for clarity). All
strain and energy fluctuations in this work are evaluated on the horizontal
dashed line in b, corresponding to the plane of the 2DEG, which is taken to
lie 1.5 nm below the top quantum-well interface. c Diagonal strain components
$\varepsilon_{ii}$ ($i=x,y,z$). d,e Corresponding conduction-band energy
offsets $\Delta E_{c}$, for Al (d) or Pd (e) wires of width $w=80$ nm (shaded
region), with depositional strains as indicated. We also assume thermal
contractions for a temperature of 1 K, as described in Methods. The peak-to-
peak width $w^{*}$ and amplitude $A$ of the fluctuations are defined in d. f,g
Results for $w^{*}$ and $A$ are plotted as a function of the actual wire width
$w$. The dashed line in f corresponds to $w^{*}=w$. Closed triangles in g
correspond to Al wires, following the color scheme in d, while open circles
correspond to Pd, following the color scheme in e.

By exploring gate designs commonly used in experiments, we can draw some
practical conclusions for designing future experiments. Most importantly, we
note that undesirable strain fluctuations can be greatly suppressed by tightly
stacking multiple layers of gates. To illustrate this point, in Fig. 1a, we
observe a strong, locally varying strain in the plane of the quantum well,
directly below a narrow gate. In contrast, it is clear that a wide gate will
produce a relatively uniform strain in the quantum well below, except near the
edges of the gate. Now if we consider several closely space gates, or an
overlapping geometry like the one shown in Fig. 1b, the strain will be nearly
uniform, similar to the situation for a wide gate. We note that this result
cannot hold for a thick oxide layer, because the overlapping gate will be too
far away to have an effect, resulting in a strain response more similar to
Fig. 1a. We conclude that the oxide layer between the gates should be thin. In
the discussion that follows, we fill in the details for this intuitively
reasonable result, and provide further numerical analysis.

##  II Results

To study the physics of strain fluctuations under top gates, and particularly,
the effect of gate-layer stacking, we simulate four systems of varying
complexity. The first system consists of a single metal linear gate fabricated
atop an otherwise uniform Si/SiGe heterostructure, as shown in Fig. 2, which
serves as a minimal model for describing the effects of local strain. The
second system considers the effects of several closely spaced gates, with or
without a narrow crossing gate, as shown in Fig. 3. Figures 4 and 5 correspond
to the experimental devices in Refs. [25] and [26], respectively. Here, the
effects of gate-layer stacking are studied by including different subsets of
overlapping gates in the simulations. Figure 5 also demonstrates the
importance of oxide-layer thickness. All results shown here make use of the
Solid Mechanics module of COMSOL Multiphysics [27], as described in Methods.
The simulations incorporate all three sources of strain described above, using
the materials parameters mentioned in Methods. For the thermal contraction
simulations, we assume the devices are cooled from $T=293.15$ to
$1~{}\text{K}$.

###  II.1 Single wire

We first consider the simple wire geometry shown in Fig. 2a, where the wire is
uniform along the $\hat{y}$ direction. The corresponding cross section is
shown in Fig. 2b. From bottom to top, the heterostructure in our simulations
consists of a 2 $\mu$m layer of strain-relaxed Si$0.7$Ge$0.3$, a 9 nm Si
quantum well, another 30 nm spacer layer of Si$0.7$Ge$0.3$, and a 10 nm
insulating layer of Al2O3. We assume that all interfaces in this structure are
grown epitaxially, and that the quantum well is fully strained. The Si layer
therefore experiences biaxial tensile strain due to the larger bulk lattice
constant of SiGe. Except where noted (Fig. 5), we will use this same
heterostructure in all simulations reported below. Moreover the strain, and
the energy variations it causes, will always be evaluated in the plane of the
two-dimensional electron gas (2DEG), which we take to be 1.5 nm below the top
quantum-well interface.

We first simulate just the heterostructure geometry, without any top gate.
Here, the strain is caused by a combination of lattice mismatch and thermal
contraction, giving the following diagonal strain results in the plane of the
2DEG: $\varepsilon_{xx}=\varepsilon_{yy}=1.248\%$ and
$\varepsilon_{zz}=-1.01\%$. The strain causes an energy shift of the
conduction band, as described in Methods, which accounts (in part) for the
vertical confinement potential of the quantum well. We take as a reference
point the conduction-band minimum at a point far away from the region of
interest. Since the strain and the conduction-band minimum are both uniform in
this geometry, the energy shift compared to the reference point, $\Delta
E_{c}$, is zero across the whole sample.

For the wire geometry of Figs. 2a and 2b, we consider an Al metal wire formed
directly atop the oxide layer as shown, with a fixed height of 60 nm and a
variable width $w$. The wire causes local strain fluctuations, due to a
combination of depositional stress and thermal contractions, with results
shown in Fig. 2c. Here all three diagonal strain-tensor components are plotted
($\varepsilon_{xx}$, $\varepsilon_{yy}$, and $\varepsilon_{zz}$). The
corresponding conduction-band energy shifts are shown in Fig. 2d, for cases
with and without depositional stress, as indicated. Similarly, Fig. 2e shows
results for a Pd wire. In this case, different values (and signs) of the
depositional stress are reported in the literature; we therefore consider two
different values, as well the case of no depositional stress. (The latter
results differ from those in the Al wire because of the different thermal
contractions.) For both sets of simulations, the energy shift converges to its
asymptotic value far from the wire, such that $\Delta E_{c}=0$. Near the
gates, $\Delta E_{c}$ has strong variations on the scale of several meV. For
the Al wire, the deposition stress is low, and we see that its contribution to
$\Delta E_{c}$ is very small. For the Pd wire, the opposite is true, and the
deposition stress is seen to dominate over the thermal stress. Here, $\Delta
E_{c}$ changes sign for the case of depositional tensile stress
($560~{}\text{MPa}$) vs compressive stress ($-890~{}\text{MPa}$).
Supplementary Fig. S1 provides further insight into the specific shape of the
strain profiles.

The dependence of strain effects on wire width are shown in Figs. 2f and 2g.
We now introduce two parameters to characterize the $\Delta E_{c}$ variations,
as defined in Fig. 2d: the peak-to-peak width $w^{*}$ and the trough-to-peak
amplitude $A$. These two parameters are plotted in Figs. 2f and 2g,
respectively. The width parameter $w^{*}$ is found to be essentially
universal, with no significant dependence on the materials or strain
parameters. Interestingly, $w^{*}$ asymptotes to a nonzero value for small
$w$, and to $w+w_{0}$, for large $w$. Both effects can be understood in terms
of an approximate “45∘ rule,” in which the strain fields extend out at an
angle from the gates, with details depending slightly on the wire width. We
note that there is no contradiction that $w^{*}$ remains nonzero when
$w\rightarrow 0$, since $A\rightarrow 0$ in this limit. However, there is also
an interesting dependence of $A$ on the strain parameters and on $w$. We see
that $A$ initially follows a linear dependence on $w$ in all cases. For the Pd
wire, this behavior changes at around $w=80$-90 nm, where $A$ begins to
plateau as the two edges of the wire no longer affect each other’s local
strain field. Such plateaus are generally expected for large $w$.

###  II.2 Parallel wires

We now study how the single-wire picture is modified in the presence of
additional wires, spaced closely enough that their strain fields overlap. We
consider the geometries shown in Figs. 3a and 3b, comprising five parallel Al
wires of width $80~{}\text{nm}$ and height $70~{}\text{nm}$, with gaps of
$40~{}\text{nm}$ between the wires, representing a typical gate pitch for
quantum-dot qubits [25]). In addition to these five gates, the first device
also includes a crossing gate with the same cross-section dimensions, oriented
perpendicular the wires. We assume the crossing gate covers the parallel gates
conformally, and is separated from those gates by a 2 nm insulating layer of
Al2O3. The second device has a $100~{}\text{nm}$ gap in place of the crossing
gate, but also includes a 2 nm conformal oxide layer covering the whole
surface. All the wires in these simulations are taken to be very long, to
suppress potential edge effects. The strains are computed, as described above,
and the resulting conduction-band minima are plotted as a function of lateral
position in Figs. 3c and 3d. Several cuts are taken in the plane of the 2DEG,
along the indicated lines, yielding the results shown in Figs. 3e and 3f.

Figure 3: Strain simulations of a parallel-wire geometry, with a crossing-wire
or a gap at $y=0$, fabricated on the same heterostructure as Fig. 2. a 3D view
of five parallel Al wires ($80~{}\text{nm}$ wide, $70~{}\text{nm}$ tall, with
$40~{}\text{nm}$ gaps between them) with a perpendicular crossing wire of the
same dimensions. All gates are The lower set of gates is cover by a 2 nm layer
of Al2O3, separating it from the crossing wire. b Same as a, except that the
crossing wire is replaced by a gap of width $100~{}\text{nm}$. In both a and
b, the uppermost 2 nm oxide layer is not shown, for clarity. c,d Conduction-
band energy modulations $\Delta E_{c}$, for the geometries shown in a and b,
respectively. e,f Line cuts from c and d, respectively. We highlight our main
result here, that the energy fluctuations are strongly suppressed below the
crossing wire (c) or the gap (d).

In these multigate devices, $\Delta E_{c}$ exhibits short-range variations
that mirror the local gate structure, and a slowly varying envelope arising
from long-range strain fields. $\Delta E_{c}$ differs in interesting ways for
the two geometries, especially near the crossing regions ($Y\approx 0$). The
trough-to-peak amplitudes are similar to those observed in Fig. 2, indicating
that the short-range features are mainly governed by the gate structure right
above the 2DEG. It is important to note that the amplitudes of these
oscillations are large enough to produce unintentional dots. For example, the
series of dips along the gray dashed line in Fig. 3d are 3 meV deep, compared
to orbital excitation energies of 1-3 meV in typical dots. Such potential
fluctuations are also large enough to affect exchange interactions, which are
used to construct two-qubit gates. For example, it has been shown that useful
a exchange interaction of strength $J\approx 10~{}\text{MHz}$ requires having
a tunnel barrier between two Si/SiGe dots with a height less than 1 meV [3].
If necessary, such strain-induced variations could potentially be compensated
electrostatically; however for complicated gate geometries, the competition
between short- and long-range strain features could make this challenging. A
desirable approach is therefore to compensate some of the fluctuation through
gate design, as discussed below. Finally we note that the envelope of the
potential variations can also vary by several meV, even across a series of
identical wires. This is particularly evident in the dot-dashed linecuts of
Figs. 3e and 3f, where the roughly 1 meV difference in $\Delta E_{c}$ between
neighboring wires can be viewed as an effective detuning shift.

We now study the effect of overlapping gates in Fig. 3e by comparing results
directly underneath the crossing gate (solid-black line) to those far away
from the gate (dot-dashed gray line). While the envelopes of the two curves
appear similar, the amplitudes of their short-range oscillations differ by a
factor of six. Moreover, the oscillations are seen to have opposite sign.

One would like to understand and potentially predict such interesting
behavior. Indeed, for simple geometries, with only a few materials layers
(e.g., Fig. 2, or the dot-dashed line in Fig. 3c), this is often possible.
However more-complicated geometries, particularly those with nontrivial three-
dimensional (3D) features, can give rise to unexpected behavior, like the sign
change of the short-range oscillations. In Methods, we note that $\Delta
E_{c}$ is dominated by the $z$ component of the strain, $\varepsilon_{zz}$,
which depends on multiple factors, such as locally varying interface profiles,
the specific values of thermal expansion coefficients, and the various layer
thicknesses. In fact, in Sec. II.4 below, we study a geometry where simply
changing the oxide thickness, keeping everything else fixed, causes a similar
sign change in the short-range oscillations. Notwithstanding these challenges,
we can make some general observations. For example, in Fig. 3e, the
oscillation sign change, moving from the dot-dashed to the solid linecut,
indicates that a different linecut, somewhere between these two lines, should
provide more-strongly suppressed oscillations. Similarly, modifying the gate
geometry could also reduce the oscillation amplitude. For example, narrower
crossing gates, or more-closely spaced parallel gates could both have the
desired smoothing effect. These results demonstrate that gate-layer stacking
can provide an effective strategy for reducing short-range strain variations.

An alternative scheme for suppressing short-range oscillations is simply to
remove the top gates (solid black line in Figs. 3d and 3f). In this case, the
strain fields are mainly long-range, as desired; however, as a result, short-
range electrostatic control is also sacrificed. While relatively smooth
potentials can be achieved along the $Y=0$ lines of both geometries of Fig. 3,
we note that their qualitative behaviors differ. The dip features in $\Delta
E_{c}$ along the gray dashed line in Fig. 3f are especially prominent,
indicating that edge effects (e.g., caused by the terminal ends of wires) have
a particularly strong effect on both short- and long-range behaviors.

Figure 4:  Strain simulations of the quadruple-quantum-dot device of Ref.
[25], for several configurations of stacked Al gates fabricated on the same
heterostructure as Fig. 2. a A reduced gate set, including only screening
gates ($30~{}\text{nm}$ thick, maroon) and plunger gates ($50~{}\text{nm}$
thick, blue). b Full gate geometry, including the gate layers in a, side-
reservoir gates (shown in blue because they are formed in the same layer as
the blue gates in a), and tunnel-barrier gates ($70~{}\text{nm}$ thick,
yellow). Two additional gate configurations are considered in Fig. S2. In each
case, every gate layer is covered by 2 nm of Al2O3 (not picture, for clarity).
c,d Strain-induced fluctuations of $\Delta E_{c}$ in the plane of the 2DEG,
for the geometries shown in a and b, respectively. e Line cuts along the
horizontal lines in c (dot-dashed gray curve) and d (solid black curve), which
pass through the centers of the lower four dots. Again we highlight our main
result, that energy fluctuations in the fully covered geometry (solid black
curve) are strongly suppressed compared to gates separated by gaps. f Vertical
line cuts taken from d. Note the emergence of a strain-induced double-well
potential.

###  II.3 Quadruple-quantum-dot device

We now consider gate-layer stacking in more conventional overlapping gate
geometries, like the quadruple-quantum-dot shown in Fig. 4 [25]. For the
simulations, we assume the same heterostructure as in Fig. 2 — now with three
overlapping layers of Al metal gates. From bottom to top, these correspond to
screening gates (maroon), plunger or reservoir gates (blue), and tunnel-
barrier gates (yellow). We also include 2 nm Al2O3 insulating layers between
each of the metal layers. In the lower portion of the image, the plunger gates
define four quantum dots and two 2DEG reservoirs, on either side of the dots.
In the upper portion of the image, the plungers define two charge-sensing
dots, surrounded by three 2DEG reservoirs. To avoid edge effects, we use a
full simulation cell of size $18\times 18$ $\mu$m2 in the $x$-$y$ plane and 2
$\mu$m in the $z$ direction. Again, we have checked that this system size
yields converged results.

To disentangle the effects of the different gate layers in our simulations, we
begin with a smaller set of gates, and progressively add more gates until
reaching a complete set. Figure 4 show $\Delta E_{c}$ results for the
geometries shown in panels a and b. (For two additional cases, see Fig. S2 in
the Supplementary Information.) Figure 4a includes only the screening,
plunger, and upper-middle reservoir gates, while Fig. 4b includes all the
gates. The linecuts indicated in Figs. 4c and 4d are plotted in Figs. 4e and
4f. The effectiveness of gate-layer stacking is seen most clearly by comparing
the horizontal lines in Figs. 4c and 4d. In Fig. 4c, this cut crosses just the
four plunger gates, which are separated by gaps. In Fig. 4d, the gaps are all
filled by overlapping tunnel barrier gates, and reservoir gates are also
present on either side, such that the whole cut is covered by metal. As
consistent with Fig. 3, the case with gaps between the gates (dot-dashed-gray
line in Fig. 4e) has short-range oscillations of about 3 meV. Moreover, in the
fully covered case (solid-black line), the short-range oscillations are
suppressed by a factor of three, in this case. However, the oscillations have
the same sign for these two geometries, in contrast with results observed in
Fig. 3d. A notable difference between these two devices is that the crossing
gate in Fig. 3a covers the parallel gates _globally_ , as opposed to the
tunnel-barrier gates in Fig. 4b, which just fill in the gaps, locally, between
the plunger gates.

The oscillation envelopes in Fig. 4f also show interesting behavior. We
observe that neighboring dots can have confinement potentials of different
depths, corresponding to built-in, fixed detuning parameters on the order of
0.25-0.35 meV. Moreover, the envelopes for the two geometries have opposite
curvature, which we attribute to the presence of side-reservoir gates for the
full-gate geometry. The curvature sign change suggests that alternative gate
geometries could be used to reduce the detuning shifts, for example, by moving
the side-reservoir gates further away from the dots.

Finally, we note that strain from the screening gates can have unexpected
effects on quantum-dot confinement in the $Y$ direction, as demonstrated in
Fig. 4g. Here the combination of screening and plunger gates produces a
double-dip feature on either side of the dot, which is weakly affected by the
presence of the tunnel-barrier or reservoir gates. The peak between the dips
has the opposite sign as the electrostatic dot confinement. To estimate its
effect, we fit the peak to the upside-down confinement potential
$-m_{t}\omega_{y}^{2}y^{2}/2$ yields characteristic orbital energy of
$\hbar\omega_{y}\approx 1.3$ meV, where $m_{t}$ is the transverse effective
mass of silicon. Comparing this with typical dot orbital energies of
$\hbar\omega=1$-3 meV (see Supplementary Fig. S3) suggests that the strain-
induced effect is not likely to produce a double-dot along $Y$; however it can
strongly affect the dot shape — effectively flattening and widening the bottom
of the confinement potential. For weaker electrostatic confinements, the
strain-induced effect will eventually dominate.

###  II.4 Effect of oxide-layer thickness

In the final set of simulations, we also study gate-layer stacking, while
showing how using thicker oxides modifies our main conclusions. The device we
consider is based on Ref. [26], with the two variations shown in Figs. 5a and
5b. Here the heterostructure consists of a 1.2 $\mu$m strain-relaxed Si0.7O0.3
buffer layer, an 8 nm Si quantum well, a 30 nm Si0.7O0.3 spacer, a 1 nm Si
cap, a thin Al2O3 oxide layer, a 20 nm Al metal gate, and another thin Al2O3
layer. To study the effects of oxide thickness, we consider two different
oxide thicknesses: 7 nm (consistent with the device in [26]) and 2 nm
(consistent with the device in [25]). This geometry is shown in Fig. 5a, while
Fig. 5b also includes a 40 nm Al global accumulation gate. Results for $\Delta
E_{c}$ are shown in Figs. 5c-5f, for the four different combinations of oxide
thicknesses and gate geometries, with corresponding linecuts shown in Figs. 5g
and 5h.

Figure 5:  Strain simulations of the two-dot device in [26], for two
configurations of stacked Al gates, and two oxide thicknesses. From bottom to
top, the thicknesses of the Si0.7Ge0.3 virtual substrate, Si quantum well,
Si0.7Ge0.3 spacer, and Si cap are 1.2 $\mu$m, 8 nm, 30 nm, and 1 nm,
respectively. a A reduced gate set, including only the lower layer of gates
(20 nm thick), is shown in red. We also include Al2O3 layers of variable
thickness, below and above the gate layer (top layer not shown, for clarity).
b Same as a, but including a global top gate (turquoise) of thickness 40 nm.
c,d Strain-induced fluctuations of $\Delta E_{c}$ in the plane of the 2DEG,
for the geometries shown in a and b, respectively, where all oxide layers have
a thickness of 7 nm. e,f Same as c and d, except the oxide layers have a
thickness of 2 nm. In c-f, approximate dot locations are indicated by green
stars, and we have normalized the energy scale such that $\Delta E_{c}=0$ at
the dot centers. g Horizontal line cuts from panels c-f, with appropriate
color codings. We again highlight our main result, that energy fluctuations in
the covered geometry (dashed gray curve) are strongly suppressed, but only for
the case of a narrow oxide. h Vertical line cuts from panels d and f, with
appropriate color codings.

We begin by confirming the effect of gate-layer stacking, by comparing Figs.
5e and 5f. For these two simulations, the oxide thickness is the same as in
the previous subsections (2 nm), and the only difference in the geometries is
the global accumulation gate. The linecut with no global top gate (solid-
purple curve) shows strong short-range fluctuations, with similar amplitude
and shape as previous simulations, while the stacked global gate (dashed-gray
curve) has strongly suppressed fluctuations. A more surprising result is
observed in the dashed-black linecut, which has the same accumulation-gate
geometry, but a thicker (7 nm) oxide layer. Here, the short-range oscillations
have the opposite sign compared to the solid-purple curve. This behavior is
reminiscent of Fig. 3e; indeed, in both cases, the stacked gates responsible
for this behavior cover the plungers _globally_. Interestingly, the amplitude
of the oscillations for the thin-oxide device (dashed-black curve) is strongly
enhanced compared to the thick oxide (dashed-gray curve), as if the thicker
oxide were amplifying the oscillations. We attribute this behavior to three-
dimensional aspects of the gate geometry, whose effects are difficult to
predict. For completeness, we also show results for a thick oxide with no
global top gate (solid-orange curve), in which the oscillations are strongly
suppressed, with features coincidentally similar to the gray-dashed curve.

Finally, in Fig. 5h, we consider linecuts along the $y$ axis that pass through
the nominal centers of the quantum dots (green stars). Here, we consider only
the full gate geometry, which includes the global accumulation gate. Similar
to linecuts along $\hat{x}$, these results confirm that stronger short-range
fluctuations are obtained in the case of thicker oxides (gray curves). We also
note the slight differences between results in the left- and right-hand dots
in Fig. 5h (solid vs dashed curves), caused by long-range strain fields and
the asymmetry of the top-gate configuration.

##  III Discussion

We have investigated local strain fluctuations in realistic Si/SiGe quantum
dot devices, arising from inhomogeneous materials layers, and in particular,
from the metal top gates. For these gates, we include effects from both
thermal contraction and depositional stress, finding that the former dominates
for Al gates, while the latter dominates for Pd gates. Focusing on Al gates,
we note that strain along the $z$ axis ($\varepsilon_{zz}$) mainly determines
the variations of the conduction-band minimum ($\Delta E_{c}$), and is
strongly affected by nontrivial 3D features such as the vertical layer
stacking and the 3D gate geometry, resulting in behavior that is not always
intuitive.

Despite these challenges, we can draw some general conclusions. First, we note
that $\Delta E_{c}$ exhibits both short-range variations that mirror the shape
of the top gates, and long-range variations that produce slowly varying
envelopes that modulate the fast oscillations. The amplitude of the short-
range fluctuations is comparable, but often smaller, than typical
electrostatic fluctuations produced by the top gates; however, unlike
electrostatic fluctuations, strain-induced effects cannot be modified after
fabrication. In some cases, the potential fluctuations can have a considerable
effect on the shape of the dot, as in Figs. 4(g) and S3. Indeed, dot
localization effects that were previously attributed to trapped charge [14,
15] could potentially be explained, in full or in part, by strain effects. The
long-range fluctuations cause potential shifts below neighboring plunger gates
that act like a built-in detuning potential between the dots, which must be
electrostatically compensated for proper gate operation.

The most important result reported in this work is that the tight stacking of
gate layers provides a key tool for overcoming strain-induced potential
fluctuations. Such stacked gates can be seen as largely reproducing the
behavior of a uniform metal top gate. However, unexpected 3D effects can still
occur, for example, when employing a thicker oxide layer between the metal
gates, which can have the effect of _amplifying_ the short-range potential
fluctuations. Similarly, different styles of gate stacking can yield different
potential profiles; for example, a globally spanning top gate (Fig. 5) is seen
to cause very different behavior than a local tunnel-barrier gate filling the
gap between two plunger gates (Fig. 4), as evidenced by short-range
oscillations with opposite signs.

In future work, as arrays of qubits are scaled up, and every aspect of qubit
functionality is tightly controlled, it will be increasingly important to
account for strain-induced confinement effects, which can compete with
electrostatic confinement. The simplest approach to avoiding strain-induced
behavior is to specially design gate geometries to suppress these
fluctuations. Clearly, gate-layer stacking is a key tool in this approach.
However, other design tools, such as modifying the lateral positions of gate
electrodes, the thicknesses of oxide layers, or other 3D features of the gate
geometry, could also serve this purpose. Generally, we anticipate that strain
engineering will play an important role in future qubit technologies.

## Methods

We calculate strain profiles using the Solid Mechanics module of COMSOL
Multiphysics [27]. To perform these calculations, we must specify the Young’s
modulus $E$, Poisson’s ratio $\nu$, and coefficients of thermal expansion
(CTE) $\alpha$, for each material. Note that each of these parameters varies
with temperature, but COMSOL assumes temperature-independent values. $E$ and
$\nu$ only weakly depend on the temperature, so we are justified in simply
using the room-temperature values in the COMSOL parameter library. To account
for the temperature dependence of the CTEs, we use temperature-averaged CTEs
$\bar{\alpha}$ defined by
$\bar{\alpha}=(T_{i}-T_{f})^{-1}\int_{T_{f}}^{T_{i}}\alpha(T)\,dT$, where
$T_{i}$ and $T_{f}$ are the initial and final temperatures, respectively. We
approximate these integrals using the temperature-dependent CTE data in Refs.
[28, 29, 30, 31, 32, 33]. For the SiGe alloy, we use data for Si and Ge in
combination with Vegard’s law to evaluate its CTE. The temperature-averaged
CTEs are then found to be
$\\{\bar{\alpha}_{\text{Si}},\bar{\alpha}_{\text{Si}_{0.7}\text{Ge}_{0.3}},\bar{\alpha}_{\text{Al}},\bar{\alpha}_{\text{Pd}},\bar{\alpha}_{\text{Al}_{2}\text{O}_{3}}\\}=\\{0.76,1.52,14.16,8.86,3.30\\}$
$(\times 10^{-6}\text{~{}K}^{-1})$. The biaxial strain from lattice mismatch
is imposed through the initial-strain parameters
$\varepsilon_{xx}=\varepsilon_{yy}=1.24\%$ and $\varepsilon_{zz}=-1.01\%$.
Where specified, depositional stress in the metallic gates is imposed as an
intrinsic stress. Finally, free boundary conditions are enforced on every
surface, except for the bottom surface, where we enforce contraction that
matches the bulk thermal contraction of Si, to emulate the presence of a large
Si substrate.

The calculated strain profile can then be related to an offset $\Delta E_{c}$
of the conduction band of the Si quantum well by the relation [16]

$\Delta
E_{c}=E_{0}+\Xi_{u}\varepsilon_{zz}+\Xi_{d}(\varepsilon_{xx}+\varepsilon_{yy}+\varepsilon_{zz}),$
(1)

where $\Xi_{u}=10.5$ eV and $\Xi_{d}=1.1$ eV are deformation potential
coefficients [34] whose difference is a consequence of the anisotropy of the
$z$ valleys, which are the low-energy points of the conduction band in
momentum space, for the strained Si/SiGe quantum well [2]. As a result, strain
effects in $\Delta E_{c}$ are dominated by the $z$ component of the strain
tensor, $\varepsilon_{zz}$, as can be seen by comparing Figs. 2c and 2d. When
computing energy fluctuations in Eq. (1), we use the strain evaluated in the
2DEG plane, assumed to lie $1.5~{}\text{nm}$ below the top interface of the
quantum well, where the low-energy electronic wave functions of the quantum
well are concentrated. Finally, unless otherwise specified, $E_{0}$ is
adjusted in each calculation such that its asymptotic value of $\Delta E_{c}$
far from the active region (containing the gates) is zero.

## Acknowledgments

We are grateful to Menno Veldhorst and Gertjan Eenink for sharing fabrication
and gate designs from Ref. [26]. We also thank Hudaiba Soomro for important
clarifications related to the simulations. This research was sponsored in part
by the Army Research Office under Awards No. W911NF-23-1-0110,
W911NF-22-1-0090, and W911NF-17-1-0274. The views, conclusions, and
recommendations contained in this document are those of the authors and are
not necessarily endorsed by nor should they be interpreted as representing the
official policies, either expressed or implied, of the Army Research Office or
the U.S. Government. The U.S. Government is authorized to reproduce and
distribute reprints for U.S. Government purposes notwithstanding any copyright
notation herein.

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## Supplementary Information

Figure S1: Propagation of strain in single wire geometry. a In-plane tensile
stress deforms the unstrained square (black) into rectangle (red) elongated
and compressed in horizontal and vertical directions, respectively. b Same as
a except for in-plane compressive stress. c Horizontal strain
$\varepsilon_{xx}$ profile in the case of a Pd wire with $560~{}\text{MPa}$ of
tensile depositional stress. Three different color scales are used due to
large strain differences between materials. Green boxes and arrows illustrate
the propagation of strain in the SiGe and oxide layers. Pd wire induces a
large in-plane compressive stress in the region directly below the wire,
producing a deformation like b. This, in turn, provides an in-plane tensile
stress in the regions directly outside of the wire’s edges, as indicated by
the upper arrow, leading to a deformation like a. Similar considerations lead
to the deformations shown in the lower boxes. d Same as c, except the Pd wire
has $890~{}\text{MPa}$ of compressive depositional stress, leading to a
reversal in the strain pattern compared to c. e, f Vertical strain
$\varepsilon_{zz}$ profiles corresponding to c and d, respectively. Figure S2:
Additional strain simulations of the six-dot device in Fig. 4, where each row
shows results for the gate layout shown in the leftmost schematic. The second
column shows $\Delta E_{c}$ profile in the plane $1.5~{}\text{nm}$ below the
top Si/SiGe interface. The third and fourth columns show horizontal and
vertical cuts, respectively, with the colors and line styles corresponding to
those shown in b. The vertical cuts run through the third and fourth dots. a
The gate set only includes screening gates (30 nm thick, maroon). b, c, d The
regions directly beneath the screening gates tend to act as potential wells,
while the regions between the gates act as potential barriers, consistent with
the results in Fig. 3. e Gate geometry matching Fig. 4a. f, g, h The potential
beneath the central screening gate changes from $\Delta E_{c}<0$ (as shown in
b) to $\Delta E_{c}>0$ in the region of the newly added plunger gates (blue),
illustrating a non-trivial interaction between gate layers. i Same as e with
the addition of side-reservoir gates. Comparing k and g, we see that the
addition of the reservoir gates cause $\Delta E_{c}$ of the outer dots to
shift above $\Delta E_{c}$ in the inner gates. This indicates that by
adjusting the distance between reservoir and plunger gates, it is possible to
remove the strain-induced energy detuning between the outer and inner dots. m
Gate geometry matching Fig. 4b, where barrier gates (yellow) and an uppermost
layer of Al2O3 (gray, 2 nm) have be added. n, o, p The addition of the barrier
gates suppresses $\Delta E_{c}$ oscillations in the regions below the barrier
gates, as can be seen mostly easily by comparing o to k. This illustrates the
effectiveness of gate-layer stacking in reducing strain fluctuations. Figure
S3: Electrostatic and strain contributions to quantum dot potential energy
landscape. a Electrostatic potential energy -$e\phi$ in the absence of strain
of an inner dot in the device shown in Fig. 4. The electrostatic potential is
calculated in the Thomas-Fermi approximation using COMSOL Multiphysics [27],
where gate voltages are adjusted to achieve the single-electron regime in one
inner dot with the other dots depleted. The dot is nearly circular with
confinement energies of
$\\{\hbar\omega_{x},\hbar\omega_{y}\\}=\\{2.480,2.599\\}$ (meV). b, c, d Same
as a except also adding in strain-induced $\Delta E_{c}$ in the cases of Al
gates (60 MPa), Pd gates (-890 MPa), and Pd gates (560 MPa), respectively,
where the pressures indicate the depositional strain in the gates. In each
case, the electrostatic potential contribution dominates over the strain
contribution, as can be seen by the small changes in confinement energies
$\hbar\omega_{j}$, implies that the strain does not inhibit dot formation.
However, note that in devices with dots with smaller electrostatic confinement
energies $\hbar\omega_{j}\sim 1~{}\text{meV}$ (larger radii), this calculation
suggests that the strain contribution $\Delta E_{c}$ to the potential energy
landscape can be comparable to the electrostatic contribution, possibility
interfering with dot formation.