# Building programable integrated circuits through disordered Chern insulators

Bing-Lan Wu  School of Physical Science and Technology, Soochow University,
Suzhou, 215006, China  Zi-Bo Wang  College of Physics and Electronic
Engineering, Sichuan Normal University, Sichuan, 215006, China  Zhi-Qiang
Zhang<EMAIL_ADDRESS>School of Physical Science and Technology,
Soochow University, Suzhou, 215006, China  Hua Jiang<EMAIL_ADDRESS>School of Physical Science and Technology, Soochow University, Suzhou, 215006,
China  Institute for Advanced Study, Soochow University, Suzhou 215006, China

###### Abstract

We study the construction of programable integrated circuits with the help of
disordered Chern insulators (CIs) in this letter. Specifically, the schemes
for low dissipation logic devices and connecting wires are proposed. We use
the external-gate-induced step voltage to construct spatially adjustable
channels, where these channels take the place of the conventional wires. Our
numerical calculation manifests that the external gates can be adopted to
program the arbitrary number of wires ($n$-to-$m$ connections). We find that
their electron transport is dissipationless and robust against gate voltage
fluctuation and disorder strength. Furthermore, seven basic logic gates
distinct from the conventional structures are proposed. Our proposal has
potential applications in low power integrated circuits and enlightens the
building of integrated circuits in topological materials.

###### keywords:

Programable wires logic gates disordered Chern Insulators

##  1 Introduction

The integrated circuits made up of metallic wires and logic devices have
significantly improved information processing efficiency and dramatically
rebuilt our lifestyle 1, 2, 3. However, the power dissipation for such devices
is one of the most focused challenges, where lots of energy is wasted due to
the existence of resistance. In conventional printed circuit boards [see Fig.
1(a)], the connections between electronic components are exclusively
determined by conductor pattern (metallic wires), in which electron transport
is inevitably dissipated 4, 5, 6. Furthermore, the complicated structure of
logic devices also suffers from heavy joule heat, which also induces
overheating troubles 7, 8. In order to overcome those problems, topological
insulators have attracted great interest over the past decades 9, 10, 11, 12,
13, 14, 15, 16. These systems are predicted to possess the dissipationless
topological edge states and are considered as candidates of ideal wires in
integrated circuits 17, 18. Nevertheless, the edge state always sits at the
boundary, and its shape is only determined by the geometry of the sample,
which limits its applications.

Fortunately, the conducting channels also emerge at the interfaces between two
topologically distinct materials 19, 20, 21. Especially at the interfaces
between quantum anomalous Hall phases with different Chern numbers, the one-
dimensional chiral states with dissipationless transport are available 22, 23.
Compared to the topological edge states, the interface states exhibit higher
tunability, engineered spatially. Recently, we proposed the existence of a
chiral interface state with quantized transport in disordered CIs 24.
Generally, the Hall conductivity $\sigma_{xy}$ for a disordered CI is
$e^{2}/h$ inside the mobility gap, while sharply jumps to $0$ at two mobility
edges since all the bulk states are localized by Anderson disorder 24, 25, 26,
27, 28, 29, 30. When a step potential is adopted by an external gate, the
Chern number of two adjacent areas (separated by external gates) can be zero
and one, respectively. Hence, the dissipationless chiral channels, which are
spatially adjustable by external gates, emerge at the interface 24.

Figure 1: (Color online). (a) Schematic plot of a conventional printed circuit
board. The orange areas are the background. The solid green lines are the
wires, and the logic devices are marked in yellow circles. (b) Schematic plot
of a programmable integrated circuit based on disordered-CIs. The central
region is divided into several cyan and gray blocks. The red arrows denote the
current directions.

In this letter, we show that the interface channels with arbitrary
trajectories can be constructed by controlling the external gates in
disordered CIs, and its robustness against backscattering is also preserved.
Utilizing such perfect transport properties, we propose a programable circuit
board. As shown in Fig. 1(b), the central region of the sample is divided into
several blocks, among which appropriate gate voltage arrangements are
considered to program the required wires to connect the corresponding devices.
Our numerical results manifest that the partition of current can also be
realized in this programable circuit, and the number of branch wires can be
adjusted by external gate voltage manipulation. Significantly, the programable
chiral interface channels can also be adopted to construct all seven basic
logic gates31, 32, 33, 34. These structure-simplified logic gates are
compatible with wires, which take full advantage of disordered CIs’
topological nature. Our proposal of dissipationless wires and basic logic
gates provide a route to build integrated circuits in topological systems.

##  2 Result

Our investigation is based on Qi-Wu-Zhang CI model 35, and the Hamiltonian in
the square lattice reads:

$\displaystyle\begin{split}H=&\sum_{i}[c_{i}^{\dagger}(\frac{t\sigma_{z}}{2}-iv\sigma_{y})c_{i+\hat{x}}+c_{i}^{\dagger}(\frac{t\sigma_{z}}{2}-iv\sigma_{x})c_{i+\hat{y}}+h.c.]\\\
&+\sum_{i}[c_{i}^{\dagger}(m-2t)\sigma_{z}c_{i}+c_{i}^{\dagger}(V_{i}+W_{i})\sigma_{z}c_{i}]\end{split}$
(1)

where $c_{i}^{\dagger}$ ($c_{i}$) is the creation (annihilation) operator on
site $i$. $\sigma_{x,y,z}$ are Pauli matrices and $\sigma_{0}$ is the $2\times
2$ identity matrix. The parameters are fixed at $v=0.5t$, $m=t$, where $v$,
$m$ and $t$ are Fermi velocity, mass and hopping energy, respectively. $V_{i}$
shows the profile of the gate-induced potential, and $W_{i}$ is the Anderson
disorder uniformly distributed within $[-\frac{W}{2},\frac{W}{2}]$. $W$ is the
disorder strength.

Figure 2: (Color online). (a) Schematic of programable circuit device. The
central region is divided into $6\times 6$ blocks with size $100a\times 100a$,
where $a$ is lattice constant. (b)(d)(g) Local current density distribution
corresponding to (a) with disorder strength $W=3.5t$ under different gate
voltage configuration. Here, the gate voltage on white and blue blocks are
$V_{a}$ and $V_{b}$, which take the standard values $V_{a}=-2.8t$, $V_{b}=0$
if not specified. The red arrows denote the chiral interface channels. (c)
Differential conductances $G$ of case (b) versus $W$ under different $V_{a}$.
(e)-(f) and (h)-(i) are similar to those in (c), except $G$ for cases (d) and
(g), respectively.

The wires and the logic gates are basic building blocks for conventional
integrated circuits. We first propose the realization of programable ‘wires’
with the help of disordered CIs. The transport properties of a typical device
are studied as illustrated in Fig. 2(a). The central region is divided into
$6\times 6$ little blocks, where each block is attached with an external gate.
The blocks’ potential can be manipulated by the corresponding gates
independently. To simulate the typical cases in printed circuits boards, the
gate voltage takes two discrete standard values $V_{a}$ and $V_{b}$ for white
and blue blocks, respectively. Furthermore, 12 logic devices are considered,
which are labeled as ($U_{1},U_{2},U_{3}$), ($D_{1},D_{2},D_{3}$),
($L_{1},L_{2},L_{3}$), and ($R_{1},R_{2},R_{3}$) connecting up, down, left and
right boundary, respectively.

Figure 3: (Color online). (a) and (e) Schematic of programable circuit
devices, which have two and three chiral interface channels, respectively. (b)
and (f) Local current density distribution corresponding to cases (a) and (e)
with gate voltage $V_{a}=-2.8t$, $V_{b}=0$ and disorder strength $W=3.5t$.
(c)$-$(d) and (g)$-$(h) Conductances $G$ $vs$ $W$ for different $V_{a}$ and
$V_{b}$, respectively.

Three cases are investigated to illuminate the highly programable wires based
on the dissipationless chiral-interface states. For simplicity, the standard
gate voltage for the white (blue) blocks are chosen as $V_{a}=-2.8t$
($V_{b}=0$, if exists) with the Chern number $C=0$ ($C=1$) 24. In the first
case, all gate voltages in blocks are set as $V_{a}$ [see Fig. 2(b)]. The
entire sample belongs to the Anderson insulator with $C=0$. One can see from
the typical local current density distribution (Fig. 2(b)) and the conductance
$G=0$ (Figs. 2(c)), all logic devices in the circuit board are completely
disconnected due to Anderson localization. In the second and the third cases,
the gate voltages of blocks are programmed as configurations in Figs. 2(d) and
(g). The Chern number is $C=1$ in the blue blocks with $V_{b}=0$, and their
difference between blue and white blocks guarantees the emergence of chiral
interface channels labeled by the solid red lines with arrows. As shown in
Fig. 2(d) and (g), channel connecting device $L3$ ($L2$) and $R2$ ($D2$) is
obtained. Therefore, it is appropriate to summarize that any two devices of a
circuit can be switched into ‘on’ and ‘off’ by properly arranging the gate
voltage $V_{a},V_{b}$.

In realistic samples, the disorder strength $W$ and gate voltage $V_{a}/V_{b}$
may deviate from the standard values because of the immature fabricating
processes. To examine the robustness of wires in the programable circuit
boards, we investigate the differential conductance $G$ versus $W$ for
different $V_{a}/V_{b}$. As shown in Fig. 2(c), the localization behaviors for
states in Fig. 2(b) are insensitive to the variation of $V_{a}$ and $W$. The
plots in Fig. 2(e)-(f) and (h)-(i) correspond to the configurations in Fig.
2(d) and (g), respectively. The quantized $G=e^{2}/h$ plateau exists for
different gate voltages and a wide range of disorder strength, indicating the
transport of these interface channels are robust against the variation of gate
voltages and disorder strength. To be specific, when $V_{a}$ ($V_{b}$) takes
the standard value $-2.8t$ ($0t$), $G=e^{2}/h$ plateau holds within a wide
disorder strength range $W\in[2.4t,\,4.4t]$. When the gate voltages on blue
and white blocks deviate from the standard value, the plateau width shrinks
slightly. Nevertheless, it is worth to note that as long as
$V_{a}\in[-3t,\,-2.6t]$ and $V_{b}\in[-0.4t,\,0]$, one can always achieve the
quantized $G=e^{2}/h$ plateau with disorder strength $W\in[2.4t,\,3.6t]$. This
phenomenon indicates that the dissipationless programable circuit ‘wires’ has
a high fault tolerance feature for both gate voltage and disorder.

Figure 4: (Color online). (a)(d) The schematic diagram of gate voltage
configuration to realize 2 and 3 branches of current in intergrated circuits
devices, respectively. The blue circles denote bifurcation points of current.
(b) and (e) Local current density distribution corresponding to (a) and (d),
respectively, with $V_{a}=0$, $V_{b}=-2.8t$ and disorder strength $W=3.5t$.
(c) and (f) The branch conductance $G_{R1,L2}$, $G_{R2,L2}$, $G_{R3,L2}$ and
the total conductance $G$ $vs$ $V_{b}$ with $V_{a}=0$ and $W=3.5t$.

Furthermore, we also study the gate voltage configurations shown in Fig. 3(a)
and (e). These two gate voltage configurations enable the simultaneous
connection of two and three sets of devices [i.e., (L1-R2/L2-R3) in Fig. 3(b)
and (L1-R1/L2-R2/L3-R3) in (f)]. Figures 3(c)-(d) and (g)-(h) manifest that
the quantized $G$ capture the double ($G=2e^{2}/h$) and triple ($G=3e^{2}/h$)
disspationless channels, respectively. Comparing to those in Fig. 2, the
parameter regions of $W$ and $V_{a}/V_{b}$ for quantized plateaus $2e^{2}/h$
($3e^{2}/h$) are nearly unchanged. It means that parameters optimization is
not needed when the single-wire is replaced by the multiple-wire. Hence, such
disordered-CIs-based programable wires possess fantastic potential
applications due to their flexibility for device connection ($V$-tunable) and
the robustness against parameter variation.

One can also program the chiral interface channels as current splitters,
leading to a one-to-many connection between devices. Such a connection
requires a more careful arrangement of gate voltages. For example, as shown in
Fig. 4(a) and (d), one-to-two and one-to-three connections are obtained. The
corresponding local current density distributions [see Fig. 4(b) and (e)]
agree with the current flowing in the directions marked by red arrows.

To quantitatively study one-to-many wire connections, we pay more attention to
the dependence of the current partition on the gate voltage $V_{b}$ [see Fig.
4(c) and (f)]. The differential conductance between different devices are
studied, where $G_{Ri,L2}$ signals the currents partitioned into device $Ri$
from device $L2$. And the summation $G=\sum_{i\in{[1,2,3]}}G_{Ri,L2}$ gives
the total conductance. From Fig. 4(c) and (f), one find that $G$ still holds
the quantized value $e^{2}/h$ with $G_{Ri,L2}$ unquantized for
$V_{b}\in[-0.4t,\,0.4t]$. Specially, when $V_{b}$ takes the standard gate
voltage ($V_{b}=0t$), all $G_{Ri,L2}$ take the large values. It means that
each branch wire is well connected. Furthermore, the conductance $G_{Ri,L2}$
varies with $V_{b}$, which provides a possible way to manipulate the current
partition relations between branches. It’s noteworthy that the quantized total
conductance $G=e^{2}/h$ still manifests the dissipationless features of
circuit boards in this case. According to all configurations studied in this
section, one concludes that the external gates can be adopted to program the
wires with arbitrary ($n-$to$-m$) connections in disordered CIs.

Figure 5: (Color online). (a)-(g) The schematic diagram of seven basic logic
gates and the corresponding truth tables. The central region is divided into
one, two or three blocks labelled by $S1$, $S2$ or $S3$, respectively. $A$ and
$B$ denote voltage input terminals, connected to the gate on the corresponding
block $S1$, $S2$ or $S3$. $Y$ denotes voltage output terminal. $V_{dd}$ and
$V_{ss}$ represent supply and source voltage. $L1$ and $L2$ or $L3$ represent
the left and right terminals connected to the central region. When the voltage
signal $V_{A}=V_{B}=0$, the initial Fermi energy in the blue block is
$E_{f}=0$ (i.e., the CI with Chern number $C=1$), and in the white block is
$E_{f}=-2.8t$ (i.e., the Anderson insulator with $C=0$).

Apart from being used as programable dissipationless wire, disordered CIs also
have a promising application in designing logic devices. Generally, the logic
devices are constructed by seven basic logic gates. At present, the
conventional logic gates have relatively complicated structures. Taking the
CMOS-based logic gate AND gate as an example, it is constructed by the
combination of NAND gate and NOT gate. The NAND gate requires two pairs of
PMOS and NMOS , while the NOT gate requires one pair of PMOS and NMOS.
Comparing with the conventional logic gates, the structures of disordered-CIs-
based logic gates are greatly simplified by taking advantage of gate-voltage-
programable chiral edge and interface states.

Figures 5(a)-(g) illustrate the construction schemes of seven basic logic
gates and the corresponding truth tables. Each of these seven logic gates has
a central region, divided into several blocks. $A$ and $B$ denote two input
terminals with voltage signals $V_{A}$ and $V_{B}$. $V_{dd}$ and $V_{ss}$ are
supply and source voltages, respectively. The initial Fermi energy in the blue
block is $E_{f}=0$ (i.e., the Chern number $C=1$) and in the white block is
$E_{f}=-2.8t$ (i.e., the Anderson insulator with $C=0$).For clarity, the Fermi
energy $E_{S1}$ ($E_{S2}$ and $E_{S3}$) and Chern number $C_{S1}$ ($C_{S2}$
and $C_{S3}$) for block $S1$ ($S2$ and $S3$) are shown in the truth table. The
corresponding logic gate for different cases of voltage input are
$V_{A},V_{B}$. Importantly, we set $V_{A/B}=V_{dd}=2.8t$ as the rated high
level (i.e., logical ‘1’) and $V_{A/B}=V_{ss}=0t$ as the rated low level
(i.e., logical ‘0’).

Here, we take two of these seven logic gates as examples for a detailed
analysis. Figure 5(d) illustrate how the OR gate works. When $V_{A}=V_{B}=0t$,
$S1$ and $S2$ have the Fermi energy $E_{S1}=E_{S2}=-2.8t$, and the
corresponding Chern number is $C_{S1}=C_{S2}=0$. Thus, there is no current
flowing into $L2$, and one has $V_{Y}=V_{ss}$ (i.e., the logical operation:
$0+0=0$). When $V_{A}=2.8t$, $V_{B}=0t$, the Chern number of $S1$ becomes
$C_{S1}=1$ ($C_{S2}$ remains 0). The chiral interface channel emerges between
$S1$ and $S2$. The current input from $L1$ will flow into $L2$ along this
channel, and thus $V_{Y}=V_{dd}$ (i.e., $1+0=1$). For the last two cases
$V_{A}=0t$, $V_{B}=2.8t$ (i.e., $C_{S1}=0$, $C_{S2}=1$) or $V_{A}=V_{B}=2.8t$
(i.e., $C_{S1}=C_{S2}=1$), the current will flow into $L2$ along the lower
edge of $S1$, and thus $V_{Y}=V_{dd}$ (i.e., $0+1=1$ and $1+1=1$ ).

Similarly, Figure 5(g) illustrates how the XOR gate works. The central region
is divided into three blocks $S1$, $S2$ and $S3$. Signal input terminal $A$ is
connected to the gates on both $S1$ and $S3$, $B$ is connected to the gate on
$S2$. In the case of $V_{A}=V_{B}=0t$, the whole central region is an Anderson
insulator ($C_{S1}=C_{S2}=C_{S3}=0$) with no current flowing through it (i.e.,
$\bar{0}\cdot 0+0\cdot\bar{0}=0$). When $V_{A}=V_{B}=2.8t$, the Chern number
of the whole central region is $1$ ($C_{S1}=C_{S2}=C_{S3}=1$), the current
will flow into $L3$ along the lower edge of region $S3$, rather than $L2$.
Thus, $L2$ is always switched off for both cases with $V_{Y}=V_{ss}$ (i.e.,
$\bar{1}\cdot 1+1\cdot\bar{1}=0$). However, when $V_{A}=2.8t$, $V_{B}=0t$
($V_{A}=0t$, $V_{B}=2.8t$), the Chern number for $S2$ always differs by $1$
compared to those for $S1$ and $S3$. The chiral interface channel emerges
between $S1$ and $S2$ ($S2$ and $S3$). Generally, the current will flow into
$L2$ along the interface channel between $S1$ and $S2$ or between $S2$ and
$S3$ with $V_{Y}=V_{dd}$ (i.e., $\bar{1}\cdot 0+1\cdot\bar{0}=1$ or
$\bar{0}\cdot 1+0\cdot\bar{1}=1$). The rest of other logic gates can be
analyzed in a similar manner.

Here, the feasibility of our logic gates proposal also originates from the
spatial programable of chiral interface states. Compared to the conventional
logic gates, the dissipationless transport features of chiral interface states
can, in principle, significantly lower the power of logic gates in our cases.
Specifically, we also analyze the logical operation of OR gate by
investigating the conductance $vs.$ disorder strength in the supplementary.
The numerical results show that the logical operation is dissipationless and
immune to disorder. Finally, the wires are compatible with the logic gates
because they can be built based on one disordered CI sample. It will greatly
simplify the integrated circuits fabricating process.

##  3 Conclusion and Discussion

In summary, we studied the realization of a programable integrated circuit
based on disordered CIs. Due to the localization features, we propose the
chiral interface channels as ideal wires. Significantly, dissipationless
wires, which connect the arbitrary required devices, can be obtained by
programming samples’ gate voltage arrays. In addition to the wires, the
disordered CIs can be utilized to construct the basic logic gates. Compared to
the conventional counterparts, the simplified logic gates’ structures will
greatly promote the compaction of integrated circuits. Moreover, combined with
the dissipationless characteristics of the wires as well as the logic devices,
our proposal will enable circuits with lower power consumption, higher
integration, and reliability.

Notably, since the Anderson phase transition is basic and only determined by
the system’s dimension and symmetry ensemble, our results apply to all 2D CIs
that exhibit a direct transition from the CI to the normal insulator.
Furthermore, to construct such a programable integrated circuit, one only
needs two discrete standard gate voltages ($V_{a}$ and $V_{b}$) corresponding
to the topologically nontrivial insulator and the normal insulator,
respectively. The proposal is still available if $V$ can drive the transition
from CI to a band insulator in some systems36, 37. This also means that it
does not matter if there exists a metallic phase during the Anderson
transition, since one can skip the voltage windows corresponding to the
metallic phase 38. Therefore the CIs can be further broadened to other
topological nontrivial systems such as the QSHE, etc. 39, 40, 41. Finally, we
discuss the scaling of the integrated circuits, which is limited by the size
of gate blocks. For a typical QAH system with Fermi velocity $\nu_{F}\approx
5\times 10^{5}m/s$ and energy gap $\Delta\approx 20meV$, the decay length is
$\lambda\approx\frac{\hbar\nu_{F}}{\Delta}\sim 50nm$. The limited scaling can
be smaller than $0.5\mu m$, since the gate block will work well if the size is
one order of magnitude larger than $\lambda$. Experimentally, our proposal
only depends on the size scale for the Anderson transition in CIs.
Fortunately, the Anderson localization has been recently observed in
$MnBi_{2}Te_{4}$ samples of $20\mu m\times 20\mu m$ 15, 42, indicating the
proposed integrated circuits are feasible under the state-of-the-art
experimental techniques.

##  4 Method

The non-equilibrium Green’s function method 43, 44 is adopted to simulate the
transport properties with
$G_{pq}=\frac{e^{2}}{h}Tr[\Gamma_{p}G^{r}\Gamma_{q}G^{a}]$ the conductance
between terminals $p$ and $q$. $G^{r/a}=[E_{F}\pm
i0^{+}-H-\sum_{p}\Sigma_{p}]^{-1}$ are the retarded$/$advanced Green’s
function, and $\Gamma_{p}=i[\Sigma_{p}-\Sigma_{p}^{\dagger}]$ is a linewidth
function with $\Sigma_{p}$ the self-energy of terminal $p$. The local current
flow vector is calculated by:

$\textbf{J}_{i\rightarrow
j}=\frac{2e^{2}V}{h}Im[H_{i,j}(G^{r}\Gamma_{L}G^{a})_{j,i}].$ (2)

$H_{i,j}$ is the coupling matrix between $i$ and $j$ sites. The local current
flow vector for site $i$ is $\textbf{J}_{i}=[\textbf{J}_{i\rightarrow
i+\hat{x}}+\textbf{J}_{i\rightarrow i+\hat{y}}]$.

##  5 Additional Information

The Supplementary Information for this paper is available at http://xxxxx.

Logical operation for OR gate.

##  6 Author Contributions

J. H initialed the ideal from the discussion with Z. B. W and integrated the
research. B.L.W and Z. Q. Z performed the calculations. B. L. W, Z. Q. Z and
H. J wrote the manuscript. All authors have given approval to the final
version of the manuscript.

##  7 Notes

The authors declare no competing financial interest.

##  8 Acknowledgement

We are grateful to Chui-Zhen Chen, Rui-Chun Xiao, and Jinsong Zhang for
helpful discussion. This work was supported by National Basic Research Program
of China (Grant No. 2019YFA0308403), NSFC under Grant No. 11822407, and a
Project Funded by the Priority Academic Program Development of Jiangsu Higher
Education Institutions.

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##  9 Supplementary Material: LOGICAL OPERATION OF $OR$ $GATE$

We take _OR gate_ as an example and calculate the conductance $G$ versus
disorder strength $W$ for four cases of voltage input ($V_{A}$, $V_{B}$), as
shown in Fig. S1. When the output level is logical ‘1’ [i.e., (i)
$V_{A}=2.8t$, $V_{B}=0t$; (ii) $V_{A}=0t$, $V_{B}=2.8t$; (iii) $V_{A}=2.8t$,
$V_{B}=2.8t$], the quantized $G=e^{2}/h$ plateau exists within a wide range of
disorder strength $W\in[2.4t,4.4t]$. When the output level is logical ‘0’
(i.e., $V_{A}=0t$, $V_{B}=0t$), $G=0$ for the same disorder region. It means
that the logical operations of _OR gate_ are dissipationless and robust
against disorder.

Figure S1: (Color online). Differential conductances $G$ versus disorder
strength $W$ for _OR gate_.


11institutetext: 1California Institute of Technology, Pasadena, CA 91125, USA;
11email<EMAIL_ADDRESS>
2Jet Propulsion Laboratory, California Istitute of Technology, Pasadena, CA
91109, USA
3University of Illinois at Urbana-Champaign, Urbana IL 61801, USA
4University of Pennsylvania, Philadelphia, PA 19104 USA
5Arizona State University, Tempe, AZ 85281, USA
6University of Arizona, Tucson, AZ 85721, USA
7Intuitive Optical Design Lab LLC, Tucson, AZ 85701, USA

# Design of The Kinetic Inductance Detector Based Focal Plane Assembly for The
Terahertz Intensity Mapper

L.-J. Liu1 R.M.J. Janssen1,2 C.M. Bradford1,2 S. Hailey-Dunsheath1,2 J. Fu3
J.P. Filippini3 J.E. Aguirre4 J.S. Bracks4 A.J. Corso4 C. Groppi5 J. Hoh5 R.P.
Keenan6 I.N. Lowe6 D.P. Marrone6 P. Mauskopf5 R. Nie3 J. Redford1 I. Trumper7
J.D. Vieira3

###### Abstract

We report on the kinetic inductance detector (KID) array focal plane assembly
design for the Terahertz Intensity Mapper (TIM). Each of the 2 arrays consists
of 4 wafer-sized dies (quadrants), and the overall assembly must satisfy
thermal and mechanical requirements, while maintaining high optical efficiency
and a suitable electromagnetic environment for the KIDs. In particular, our
design manages to strictly maintain a 50 $\mathrm{\mu m}$ air gap between the
array and the horn block. We have prototyped and are now testing a sub-scale
assembly which houses a single quadrant for characterization before
integration into the full array. The initial test result shows a $>$95% yield,
indicating a good performance of our TIM detector packaging design.

###### Keywords:

Astronomy, balloon, spectroscopy, line intensity mapping, kinetic inductance
detector, aluminum.

††journal: Journal of Low Temperature Physics

##  1 Introduction

More than half of the star formation history of the Universe has taken place
in dust-obscured regions [1, 2]. In these dusty galaxies, radiation of stars
is absorbed by dust and re-radiated in infrared (IR) wavelengths. Therefore,
studying the IR universe is crucial to discover the abundance of information
dust obscured galaxies can provide on the nature of star formation and galaxy
evolution.

The Terahertz Intensity Mapper (TIM) is a balloon-borne line intensity mapping
experiment designed to unravel the formation and evolution of galaxies around
the peak of cosmic star formation (0.5$<$z$<$1.7) [3]. TIM will perform
spectroscopic measurements of redshifted far-IR spectral lines, most
importantly the redshifted 158 $\mathrm{\mu m}$ line of singly ionized carbon
([CII]), to provide an unbiased dust-immune census of star formation history.
TIM will apply line intensity mapping to measure the total line intensity of
all galaxies in the volume set by its spectral and spatial resolution [4].
This novel methodology will enable TIM to determine the three-dimensional
structure of our star forming universe.

##  2 TIM Instrument

The TIM payload will be mounted on a balloon, whose flight is planned to be in
Antarctica at an altitude of 37 km. The TIM telescope design is lightweight
and compact, with low overall emissivity [3]. A 2-meter mirror is fabricated
as the primary of the entire TIM optics. TIM employs two R $\sim 250$ long-
slit grating spectrometers covering $240-317$ $\mathrm{\mu m}$ (short
wavelength band; SW) and $317-420$ $\mathrm{\mu m}$ (long wavelength band;
LW). Each band is equipped with a focal plane unit containing 4 wafer-sized
subarrays (termed quadrants) of aluminum kinetic inductance detectors (KIDs).
The entire array focal plane packages are cooled to 250 mK using a multi-stage
liquid 3He sorption fridge (so called He-10 fridge).

##  3 Design of Individual Detectors

KIDs are thin-film superconducting resonators which absorb incident radiation
and respond by a change in their resonance frequency and quality factor [5,
6]. TIM implements a lumped-element KID design made from 30 nm aluminum, where
each micro-resonator consists of an inductive absorber and an interdigitated
capacitor. The capacitor’s geometry can be tuned to give each detector on the
chip a unique resonance frequency, and so it naturally provides the advantage
of frequency-division multiplexing. Every KID is capacitively coupled to the
microstrip feed line. Such a lumped-element KID design enables a large array
of detectors to be read out on a single RF/microwave circuit [3]. These
detectors are designed to be photon-noise-limited under an optical loading of
100 fW at an operational temperature of 250 mK. A detailed description of the
individual KID design as well as a measurement of KIDs’ optical sensitivity
can be found in Janssen et al. [7].

Figure 1: Left: Layout of the LW TIM detector wafers. The 2 unique quadrant
designs are named as main array ($96.3\times 82.01$ mm) and secondary array
($76.3\times 86.34$ mm), each of which is present twice in the full array.
Right: The picture of one fabricated LW main array. From bottom left to right,
the zooms show a unit cell of 16 pixels, the full inductive absorber, and the
“chain-link” absorber unit cell design from which the inductor is built up.

In every wafer-sized quadrant subarray of the full array, the KIDs are hex-
packed with 2.3 mm spacing and optically coupled via a matching arrays of
direct-machined feedhorns in an aluminum horn block. The geometry of each
KID’s interdigitated capacitor is tuned to assign a unique resonance
frequency, and together all KIDs are able to fill the entire 0.5 GHz readout
bandwidth. This enables the quadrant to be read out using a ROACH2-based
readout system. Fig. 1 (right) demonstrates this fabricated LW quadrant wafer
with zooms on the details of detector design.

High absorption efficiency in the far-IR requires (1) a proper design of the
absorber geometry and (2) a small and steady gap between the array chip and
the feedhorn horn block to minimize optical crosstalk. For the first
requirement, we implement a novel “chain-link” (CL) absorber design that
offers excellent performance. The bottom right zoom of Fig. 1 demonstrates
this novel CL design. We conduct a simulation project using ANSYS-
HFSS111https://www.ansys.com/products/electronics/ansys-hfss, and the
optimization result indicates that this CL design reaches an in-band
absorption efficiency over $\sim 90\%$ in both linear polarization modes [8].
In order to embrace the second aspect, we first quantify the optical crosstalk
in various air gaps. The HFSS simulation on the TIM’s first-generation
absorber design demonstrates the increase of the air gap from 40 $\mathrm{\mu
m}$ to 80 $\mathrm{\mu m}$ causes the radiation leakage to increase by $\sim
10$ times and significantly increases the optical crosstalk with neighbor
pixels [9]. A detailed description of these simulations and optimizations are
presented in Nie et al. [8, 9]. Our design approach therefore requires a well-
controlled 50 $\mathrm{\mu m}$ spacing between the array chip and the horn
block in a package that must survive thermal cycling. As a result, this
architecture utilizes the horn block surface facing the silicon as the ground
of the microstrip readout line.

##  4 Full Array Detector Packaging Design

Figure 2: Left: The solid model of the LW full array detector packaging. Note
that the optical filters are mounted above the horn block and shown as pink,
transparent parallelograms. Right: A detailed description of the detector
wafer mount inside the package. Bottom right: A 50 $\mathrm{\mu m}$ boss is
located on the detector wafer (highlighted in the black rectangle) and a
matching spring-loaded pin pushes against the wafer.

We present the LW focal plane unit design as representative, and note that the
SW design will be nearly identical. Fig. 2 (left) shows the solid model of the
LW full array packaging. From top to bottom, the components are (1) a filter
assembly which allows stacking 2 optical filters (shown as pink, transparent
parallelograms), (2) a cap-lid which presses down the wire bond section of
wafer using spring-loaded pins, (3) a horn block with feedhorns for all 4
quadrant subarrays, and (4) a bottom housing which mounts the same type of
spring-loaded pins as well as 2 sets of 4 SMA connectors on 2 sides. Each TIM
focal plane unit contains 4 quadrants using 2 unique designs that together
cover the 64 spectral by 51 spatial pixels of the full array. As shown in Fig.
1 (left), the quadrants are positioned so that the necessary gaps between
quadrants are staggered and no spatial position or spectral channel is lost
for the full array. Through-holes etched in the wafer provide in-plane
alignment via matching guide pins in the horn block.

We enable a steady 50 $\mathrm{\mu m}$ air gap with an array of spring-loaded
pins pushing the chip against a matching array of precision-machined bosses on
the bottom of the horn block. Details of this scheme are demonstrated in Fig.
2 (right), where one example is shown in the bottom right picture. This
approach offers compliance to thermal deformations on cooldown, while avoiding
any front-side circuitry. Specifically, the positions and patterning of these
bosses are arranged so that none of them will damage the detectors and
microstrip line due to the position shift caused by the differential thermal
contraction between the aluminum and the silicon during cooldown. Also, this
“clamping” scheme spans the full array to provide even forces to all 4
quadrants.

Figure 3: The setup of an electromagnetic simulation project using commercial
software SONNET to determine the feasibility of the microstrip line
transitioning out from under the horn block. The top left part shows the
medium around microstrip line, and the bottom part shows the configuration of
the line transition. Figure 4: Left: The change of readout line width with
respect to the air gap for matching a $50\text{\,}\mathrm{\SIUnitSymbolOhm}$
impedance. Below the horn block is 50 $\mathrm{\mu m}$ gap, and so our SONNET
simulation indicates a 91 $\mathrm{\mu m}$ line width. The value of microstrip
line width saturates at 444 $\mathrm{\mu m}$, indicating that this particular
line width should match $50\text{\,}\mathrm{\SIUnitSymbolOhm}$ in the bonding
region. Right: Study of the signal loss in the transition structure using the
SONNET setup shown in Fig. 3. The exact location of the transition is varied
across the taper as indicated by the blue, red, and black lines in both
figures. The simulation result shows that in any case the loss in this
transition is $<0.1$ dB.

Due to the proximity of the horn block it will be the dominant ground plane
within its covered region. Therefore, we should determine the geometry of the
microstrip line for impedance matching. We have performed SONNET
simulations222https://www.sonnetsoftware.com/ to determine the required line
widths to achieve a $Z_{0}=$ $50\text{\,}\mathrm{\SIUnitSymbolOhm}$ feedline.
The simulation consists of a 2 by 2 mm box with walls, ceiling and bottom made
from a perfect electric conductor. From bottom to top the simulated layers
consist of 675 $\mathrm{\mu m}$ of intrinsic silicon (set by the wafer
thickness), superconducting aluminum $(L_{s}=1$ pH/sq; $R_{dc}=R_{rf}=$
$0\text{\,}\mathrm{\SIUnitSymbolOhm}$) and a vacuum layer of which the height
is varied between 20 and 2500 $\mathrm{\mu m}$. The width of the line in the
aluminum is varied in steps of 5 $\mathrm{\mu m}$. Fig. 4 (left) shows the
line width for which a $50\text{\,}\mathrm{\SIUnitSymbolOhm}$ impedance is
achieved as a function of the air gap height. For the 50 $\mathrm{\mu m}$ air
gap the optimal width is 91 $\mathrm{\mu m}$. It is worth noting the impedance
of the line is robust against variations in both the air gap height and line
width; a deviation of $\sim 10$% in either results in $\sim 5$% change in
$Z_{0}$. At large air gaps, representative of the bonding section, the ground
of the microstrip is the bottom of the wafer (where the aluminum of the
backshort is present) and the optimum line width saturates at 444 $\mathrm{\mu
m}$.

As the readout line microstrip emerges from the optically-active region, the
stripline widens to transition smoothly from being grounded by the horn block
to being grounded through the silicon to the bottom of the chip. A key feature
of the packaging design, this transition not only involves a sharp change in
the air gap, but also a change in the location of the dominant ground. Fig. 3
demonstrates the setup in SONNET used to simulate this transition. The
feedline is tapered over a length of 2 mm, narrowing from 444 to 90
$\mathrm{\mu m}$. Fig. 4 (right) shows the transmission across the transition,
for 3 locations of the air gap step (black, red, blue – colors matched to the
locations indicated in Fig. 3). In addition, one simulation has been done in
which a 90 degree bend with an inner radius of 1 mm is placed 10 mm after the
transition, shown in Fig. 4 (right, green line), as is common in the full
array design. For reference, Fig. 4 (right) also shows the loss of a single
444 (dashed magenta line) or 90 $\mathrm{\mu m}$ (dashed cyan line) wide line
with appropriate air gap over the 23 mm distance used in the transition
simulation. Even though the transition increases the transmission loss
somewhat, at an absolute value of $<0.1$ dB should still be fully negligible
and the transition is not expected to be an issue during operation.

##  5 Assembly and First Test of Quadrant Array Packaging

Figure 5: The full array packaging design is scaled down as a quadrant package
for testing individual quadrant array chip. Left: an array of spring-loaded
pins are glued on the bottom housing using silver epoxy H20E. Right: The first
step of assembling the focal plane unit. Two alignment pins are epoxied at the
back side of a dummy horn block, as highlighted in red circles. We face the
aluminum side of wafer to 50 $\mathrm{\mu m}$ bosses (hidden here), and then
we gently slide the chip through pins and rest it on the bosses.

We will initially test and characterize the quadrant chips individually before
integration into the full array. Fig. 5 shows 2 parts in the quadrant assembly
we have built, using the same microstrip architecture as will be used in the
full array. The left panel shows an array of spring loaded pins bonded on the
bottom housing using silver epoxy H20E, and the right part shows a quadrant
array chip resting on the back of horn block with its location constrained by
2 alignment pins (highlighted in red circles) interfacing with a pin and slot
in the silicon. Initial cryogenic tests and measurements with this system are
underway now. This test uses a pulse-tube pre-cooled triple-stage He sorption
cooler with a base temperature of 213 mK.

Figure 6: The VNA sweep of the 864 pixel LW quadrant array from 360 MHz to 800
MHz and a zoom picture of a segment of resonator responses at $\sim 580$ MHz.
We discover 823 resonators across the readout frequency band, and so over 95%
of the total detectors are present.

We are conducting the dark measurement for the initial test, and so the horn
block is replaced with a solid lid without any feedhorns, but stress-relieved
and with the carefully-machined 50 $\mathrm{\mu m}$ bosses. Fig. 6 shows a
preliminary vector network analyzer (VNA) scan of this system. We identify 823
resonators out of 864 designed, indicating a high yield (95.25%). The
resonator frequencies are within range of their design values, and the quality
factors are set by the coupling as designed ($Q_{c}\sim 10^{5}$ ), indicating
that our electromagnetic design of the system is realistic, and that the
mechanical architecture is robust.

##  6 Summary and Future Prospects

We have designed the full KID array package for TIM, which utilizes a novel
approach to (1) maintain the 50 $\mathrm{\mu m}$ air gap accurately and
reliably, (2) provide compliance to thermal deformations on cooldown, as well
as (3) smoothly transit the ground along the microstrip readout line. The
quadrant-level package which demonstrates this novel approach is built and
under test now. A preliminary VNA test has demonstrated a $>95\%$ yield of the
864 pixel quadrant chip, which validates the viability of the packaging
design. This yield will provide excellent performance when deployed in TIM,
which is a spatial-spectral multiplexing instrument for which the science
degrades gracefully as pixels are removed. We are conducting further
measurements to unambiguously identify each resonance with a cryogenic LED
array, allowing us to eliminate collisions via capacitor trimming [10].
Subsequently, we will confirm that the responsivity and sensitivity in this
864-pixel quadrant array match that found in the small subarrays (Janssen et
al. [7]).

###### Acknowledgements.

TIM is supported by NASA under grant 80NSSC19K1242, issued through the Science
Mission Directorate. R.M.J. Janssen is supported by an appointment to the NASA
Postdoctoral Program at the NASA Jet Propulsion Laboratory, administered by
Oak Ridge Associated Universities under contract with NASA. Part of this
research was carried out at the Jet Propulsion Laboratory, California
Institute of Technology, under a contract with the National Aeronautics and
Space Administration (80NM0018D0004).

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