# A 2D quantum dot array in planar Si/SiGe

F.K. Unseld  M. Meyer  These authors contributed equally  QuTech and Kavli
Institute of Nanoscience, Delft University of Technology, Lorentzweg 1,2628 CJ
Delft, The Netherlands  M.T. Mądzik  F. Borsoi  S.L. de Snoo  QuTech and Kavli
Institute of Nanoscience, Delft University of Technology, Lorentzweg 1,2628 CJ
Delft, The Netherlands  S.V. Amitonov  QuTech and Kavli Institute of
Nanoscience, Delft University of Technology, Lorentzweg 1,2628 CJ Delft, The
Netherlands  QuTech and Netherlands Organization for Applied Scientific
Research (TNO), Stieltjesweg 1, 2628 CK Delft, Netherlands  A. Sammak  QuTech
and Netherlands Organization for Applied Scientific Research (TNO),
Stieltjesweg 1, 2628 CK Delft, Netherlands  G. Scappucci  M. Veldhorst  L.M.K.
Vandersypen  QuTech and Kavli Institute of Nanoscience, Delft University of
Technology, Lorentzweg 1,2628 CJ Delft, The Netherlands

###### Abstract

Semiconductor spin qubits have gained increasing attention as a possible
platform to host a fault-tolerant quantum computer. First demonstrations of
spin qubit arrays have been shown in a wide variety of semiconductor
materials. The highest performance for spin qubit logic has been realized in
silicon, but scaling silicon quantum dot arrays in two dimensions has proven
to be challenging. By taking advantage of high-quality heterostructures and
carefully designed gate patterns, we are able to form a tunnel coupled 2
$\times$ 2 quantum dot array in a Si/SiGe heterostructure. We are able to load
a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge
state. Furthermore we characterise and control the tunnel coupling between all
pairs of dots by measuring polarisation lines over a wide range of barrier
gate voltages. Tunnel couplings can be tuned from about $30~{}\rm\mu eV$ up to
approximately $400~{}\rm\mu eV$. These experiments provide a first step toward
the operation of spin qubits in Si/SiGe quantum dots in two dimensions.

††preprint: AIP/123-QED

##  I Introduction

Since the original proposal for quantum computation with semiconductor quantum
dots Loss and DiVincenzo (1998), remarkable developments have been made.
Quantum dot qubits are small in size, compatible with semiconductor
manufacturing, and can be be operated with single-qubit gate fidelities and
two-qubit gate fidelities above $99.9~{}\%$ Yoneda  _et al._ (2017) and
$99~{}\%$ Xue  _et al._ (2022); Noiri  _et al._ (2022); Mills  _et al._ (2022)
respectively.

The implementation of two-dimensional qubit arrays will allow this technology
platform to fully utilize its advantages. In GaAs heterostructures 2x2 and 3x3
quantum dot arrays have already been demonstrated Dehollain  _et al._ (2020);
Mortemousque  _et al._ (2021); Fedele  _et al._ (2021). However, hyperfine
interaction leads to short dephasing times, preventing high-fidelity operation
of qubit arrays. In contrast, group IV materials benefit from nuclear spin-
free isotopes, such that quantum coherence can be maintained over much longer
times Stano and Loss (2022).

In recent years, hole quantum dots in Ge/SiGe heterostructures progressed from
a single quantum dot to a $4\times 4$ quantum dot array with shared gate
control Hendrickx  _et al._ (2021); van Riggelen  _et al._ (2022); Borsoi  _et
al._ (2022). Parallel to that also silicon based devices have been pushed
towards 2D arrays. Using quantum dots confined in the corners of silicon
nanowires, several $2\times\rm{N}$ quantum dot arrays have been demonstrated,
albeit not simultaneously at the single-electron occupancy Gilbert  _et al._
(2020); Chanrion  _et al._ (2020). Furthermore, these devices did not contain
separate gates for independent control of the tunnel barriers between
neighbouring dots. This limits the controllability for quantum simulations and
prevents sweet-spot operation Martins  _et al._ (2016); Reed  _et al._ (2016)
of exchange-based quantum gates.

In this work, we present a 2D quantum dot array in gated planar 28Si/SiGe with
barrier gates to control inter-dot tunnel couplings. Four quantum dots in a
$2\times 2$ configuration are formed with occupations controlled down to the
last electron. Furthermore, all inter-dot tunnel couplings are characterized
as a function of all barrier gate voltages. We demonstrate adequate tunnel
coupling control and provide suggestions for future scalable gate designs.

##  II Results

The $2\times 2$ quantum dot array investigated in this work is fabricated on a
28Si/Si70Ge30 heterostructure (see supplementary material). Figure 1a shows a
false-coloured scanning electron micrograph (SEM) image of a nominally
identical device, highlighting the three gate layers of the multi-layer gate
stackLawrie  _et al._ (2020). The screening gates in the first layer (purple)
define an active area, reduce the formation of spurious dots and prohibit
accumulation of a two-dimensional electron gas (2DEG) in the gate fan-out
region. The second layer (yellow) consists of plunger (P) and accumulation
gates. Barrier gates (B) are fabricated in the third layer (red). On top of
the gate stack sits a micro magnet. The SEM image in Figure 1a is taken before
its deposition to highlight the quantum dot gate pattern.

The gate stack defines four quantum dots in a $2\times 2$ grid (labeled
clockwise 1-4) and two single-electron transistors (SETs) (S1 and S2). The two
SETs serve as charge detectors and act as electron reservoirs for the quantum
dots in the $2\times 2$ array. Off-chip NbTiN inductors connected to the SET
reservoirs and parasitic capacitances form a tank circuit that enables radio
frequency (RF) reflectrometry readout, allowing for fast and accurate
detection of the charge occupation of all four quantum dots.

Figure 1: a) False colored SEM image of a nominally identical device to the
one used in the measurements. The four quantum dots in the center are labeled
clockwise 1-4 with one sensor on each side marked as S1 and S2. Dashed lines
mark the boundaries of the screening gates in the first gate layer. b) Charge
stability diagrams of nearest-neighbour quantum dots. Colored circles indicate
the quantum dots of the swept virtual plunger gates while the quantum dots
corresponding to the white circles remained with one electron each. All four
scans thus show the (1,1,1,1) charge state where four quantum dots are
occupied with one electron each. At $\Delta v{\rm P}_{i}=0$ mV, the
corresponding physical voltages on the gates are set to 2566 mV, 1831 mV, 3173
mV, 2487 mV for plungers 1-4, respectively.

During the device tune-up, we measure the cross-capacitive coupling of all
gates to all dots and virtualise them as described in Volk  _et al._ (2019)
with vPi (vBij) denoting the virtualised plunger (barrier) gates. The chosen
virtual gates compensate the cross-talk onto all dot potentials and maintain
the operation point of the charge sensors. The cross-capacitive coupling
matrix $\mathbb{M}$, translating the real gate space to the virtual gate space
via $\vec{V}^{\rm virt}=\mathbb{M}\vec{V}^{\rm real}$, is provided in the
supplementary material.

To show control over the charge occupation of the entire $2\times 2$ array, we
measure four charge stability diagrams as depicted in Figure 1b. We acquire
this data by sweeping the voltages on adjacent virtual plungers gates vPi and
vP${}_{(i~{}\text{mod}~{}4)+1}$ while monitoring the response of the charge
sensors. The colored circles in the top right corner of each charge stability
diagram indicate the position of the quantum dots corresponding to the swept
plunger gates.

A honeycomb pattern characteristic of double-dot behavior is observed for all
four plunger pairs. We identify the first electron in the four quantum dots by
the absence of any more charge transitions in the lower left corner. Thus we
can controllably access the $(N_{1},N_{2},N_{3},N_{4})=(1,1,1,1)$ charge
state, where $N_{i}$ denotes the charge occupation of quantum dot $\rm
QD_{i}$, and isolate a single spin per quantum dot. The honeycomb patterns in
Figure 1b also show that all four quantum dots are capacitively coupled to
each other.

We note that there are apparent differences in the separation between the
consecutive charge transition lines as well as in the slopes of successive
charge transition lines. These could be caused by inherent differences and
gate-voltage dependent variations in size, position or lever arm of the four
intended quantum dots. Alternatively, they might be the charging signature of
additional quantum dots in the close vicinity. While we cannot fully rule out
the presence of such stray dots at higher occupations, we can reliably reach
the (1,1,1,1) charge state in the $2\times 2$ configuration of the array.

Next to the expected charge transitions, we observe additional diagonal
features in Figure 1b, which we associate with spurious defects in our system.
These defects capacitively couple to the charge sensor but there is no
indication of capacitive interaction with the four intentional quantum dots of
the $2\times 2$ array.

Besides a well-defined charge state, controlled inter-dot tunnel couplings are
essential for the implementation of robust exchange-based quantum gates or the
execution of analog quantum simulation. Therefore, we probe the system
evolution as a function of the voltage applied to the virtual barrier gates
${\rm vB}_{ij}$ located between the plunger gates of quantum dot $\rm QD_{i}$
and $\rm QD_{j}$ with $j=(i~{}\text{mod}~{}4)+1$. The tunnel coupling
diagonally between $\rm QD_{1}$ and $\rm QD_{3}$ and anti-diagonally between
$\rm QD_{2}$ and $\rm QD_{4}$ has no dedicated barrier gate and thus is not
independently controllable. The influence of other barrier gates on the
(anti-)diagonal tunnel coupling is presented below.

Figure 2: Response of the charge stability diagram of $\rm QD_{\rm 2}$ and
$\rm QD_{\rm 3}$ to changes of virtual barrier voltage ${\rm vB}_{23}$, as
indicated by the arrow on top. From panel I to IV, we observe a gradual
increase in the both the capacitive and tunnel coupling between the two dots.
Similar data were taken for all other nearest-neighbouring pairs and are
displayed in the supplementary material.

Figure 2 shows the evolution of the charge stability diagram of $\rm QD_{2}$
and $\rm QD_{3}$ while changing the virtual barrier gate voltage ${\rm
vB}_{23}$. The sequence of panels allows us to qualitatively asses the
influence of the barrier on the capacitive coupling and tunnel coupling
between the involved quantum dots. From panel I through IV, we observe that
the separation between the triple points increases, which indicates an
increase in the capacitive coupling between the dots. In addition, we observe
that the interdot charge transition is increasingly blurred (see the circled
transitions) and the boundaries of the charge stability diagram are
increasingly rounded. Both are indicative of an increased interdot tunnel
coupling. In panel IV, for transition lines with $N_{2}+N_{3}\geq 4$ the
rounding is so strong that the quantum dots have mostly merged into a single
large dot.

To quantitatively determine the effect of the barrier voltage on the tunnel
coupling, we measure polarisation lines along the detuning axis
$\epsilon_{ij}/\alpha_{\epsilon ij}=\text{vP}_{i}-\text{vP}_{j}$, with
$\alpha_{\epsilon ij}$ denoting the lever arm, across the
$(N_{i},N_{j})=(1,0)$ to $(0,1)$ interdot transition, as shown in Figure 3a.
Scanning along this detuning axis moves the electron from dot 2 to dot 3,
resulting in a step response in the sensor signal as seen in figure 3b. This
step response is broadened by both the electron temperature $T_{e}\leq 78.5\pm
2.2~{}\rm~{}mK$ and the tunnel coupling $t$, and can be fitted using $S_{\rm
Sig}=\frac{\epsilon}{\Omega}\tanh{\frac{\Omega}{2{k_{b}T_{e}}}}$ with
$\Omega=\sqrt{\epsilon^{2}+4t^{2}}$ and $\epsilon$ the detuning between the
two quantum dots DiCarlo  _et al._ (2004). Additional slopes and offsets of
the sensor signal caused by imperfect virtualisation or drifts are taken into
account in the used fitting procedure van Diepen  _et al._ (2018).

We systematically extract the dependency of the inter-dot tunnel couplings
$t_{n,m}$ between all dot pairs $({\rm QD}_{n},{\rm QD}_{m})$ with respect to
all barrier voltages ${\rm vB}_{ij}$. Figure 3c shows the resulting tunnel
couplings $t_{n,m}$ grouped by barrier gates ${\rm vB}_{ij}$. We observe that
changing the barrier voltage ${\rm vB}_{ij}$ affects only the corresponding
tunnel couplings $t_{ij}$ significantly, while keeping the other tunnel
couplings largely constant. Note that the virtual gate matrix compensates for
cross-talk of the barrier gates onto all dot potentials, but does not account
for possible cross-talk on the tunnel couplings.

We furthermore find that below a given voltage (which is different for each
${\rm vB}_{ij}$), the influence of the barrier gate voltage on the
corresponding tunnel coupling vanishes and a residual tunnel coupling remains.
Across all four neighbouring dot pairs, the residual tunnel coupling is in the
range between $30~{}\rm\mu eV$ and $200~{}\rm\mu eV$.

We extend this characterisation to the (anti-)diagonal tunnel couplings.
Figure 3d presents the influence of the four barrier gates on the diagonal and
anti-diagonal tunnel coupling respectively. While the anti-diagonal tunnel
coupling $t_{2,4}$ is elevated and can be modulated using ${\rm vB}_{12}$ in
particular, the diagonal tunnel coupling $t_{1,3}$ is not systematically
influenced by any barrier gate and remains in many cases lower than all other
tunnel couplings, albeit far from zero.

Figure 3: a) Exemplary charge stability diagram around the (1,0) to (0,1)
transition for $\rm QD_{2}$ and $\rm QD_{3}$ as a function of the interdot
detuning $\epsilon_{23}$ and
$U_{23}/\alpha_{U23}=\text{vP}_{2}+\text{vP}_{3}$. The dashed line indicates
the detuning axis used to measure polarisation lines. b) Example of a measured
(dots) and fitted (solid line) polarisation line for $\rm QD_{2}$ and $\rm
QD_{3}$. c) Dependence of the tunnel couplings extracted from polarization
lines between neighbouring quantum dots on each of the four virtual barrier
gate voltages. The plots are ordered to follow the physical position of the
barrier gate e.g. barrier $\rm vB_{41}$ situated in the top left corner of the
quantum dot array is depicted in the top left plot. The legend for symbols and
colors is shown above panels a) and b). We note that the dc voltages of
barriers $\rm vB_{12}$ ($\rm vB_{23}$) and $\rm vB_{34}$ ($\rm vB_{41}$) are
of comparable values, which is consistent with the symmetries of the gate
pattern. Between scans we adjusted gate voltages of uninvolved gates to retain
a high visibility. These adjustments were done in such a way that all
uninvolved barrier gates remained in the small (residual) tunnel coupling
regime. On several occasions, insufficient contrast between the (1,0) and
(0,1) charge states limited the data we were able to reliably fit. These data
points are thus not available. d) Diagonal tunnel coupling and anti-diagonal
tunnel coupling as a function of all four virtual barrier gate voltages. The
physical gate voltages used at $\Delta\rm vB=0$ mV varies between data sets,
as the voltages were slightly adjusted. As in c) uninvolved barrier gates
remained in the residual tunnel coupling regime. Note also that in c) and d)
the charge states vary between scans, depending on which dots each
polarization line connects.

##  III Discussion

We demonstrated the first 2D quantum dot array in a planar silicon technology
and operated the four quantum dots in the single electron regime, consistently
achieving the $(1,1,1,1)$ charge state. Furthermore, the barrier gates allow
us to independently control the interdot tunnel couplings. However, the
residual tunnel couplings observed in this sample are higher than the typical
tunnel coupling of 1-10 $\mu$eV used in spin qubit experiments Knapp  _et al._
(2016). Presumably the close proximity of the screening gates to the center of
the plunger gates compresses the quantum dots towards the center of the
$2\times 2$ array and hence towards each other, leading to rather large tunnel
couplings. Furthermore, we see in Fig. 3 that at low tunnel coupling values,
the tunnel coupling barely responds to the barrier gate voltages anymore. The
compressed position of the quantum dots in the center region enhances also the
diagonal coupling between them. While analog quantum simulation and quantum
computation can benefit from diagonal tunnel coupling, the lack of dedicated
control over magnitude and directionality i.e. diagonal versus anti-diagonal,
also poses limitations. Suppressing any diagonal coupling with a center gate
as demonstrated in a GaAs $2\times 2$ array could be a suitable way to
circumvent this issue Mukhopadhyay  _et al._ (2018).

The encountered challenges help to identify possible improvements in the
design of planar $2\times 2$ Si/SiGe quantum dot arrays. Specifically, moving
the screening gates away from the center of the array is expected to yield
lower tunnel couplings, as the electrons are not squeezed towards each other
as much. The experiments also offer relevant learnings for scaling to larger
arrays. For instance, changing the device architecture from a square array to
a triangular array will alleviate the issues regarding undesired diagonal
tunnel couplings. Furthermore, in order to maintain control of individual
tunnel couplings, either more sophisticated patterning techniques must be
applied to route gates to the inside of a larger array Ha  _et al._ (2021), or
crossbar addressing must be employed Veldhorst  _et al._ (2017); Li  _et al._
(2018); Borsoi  _et al._ (2022). In both cases, the observations made for the
present device provide guidance for suitable plunger and barrier gate pitches
and dimensions.

###### Acknowledgements.

We acknowledge funding by Intel Corporation and fruitful discussions provided
by everyone in the Veldhorst Lab and Vandersypen Lab.

## Conflict of Interest

The authors have no conflicts to disclose.

## Author Contributions

F.K.U. and M.M. conducted the measurements. M.M. analysed the data and created
the figures. M.T.M. assisted with the tuning of tested devices and made
improvements to measurements and the set up. F.B. took part in data analysis
and implemented with S.L.dS. and M.M. code to largely automate the tunnel
coupling measurements. S.V.A. and F.K.U. fabricated the samples on a
heterostructure designed and grown by A.S. in the lab of G.S. F.K.U. and
L.M.K.V. wrote the manuscript with input from all authors. The project was
conceived and supervised by M.V. and L.M.K.V.

## Data Availability Statement

Data and analysis scripts supporting this work are available in the Zenodo
repository, under the DOI: 10.5281/zenodo.7957631.

##  Appendix A Device fabrication and screening

This device is fabricated on a 28Si/Si70Ge30 heterostructure. A $2.5~{}\rm\mu
m$ strain relaxed Si70Ge30 buffer layer makes the foundation. On top of it the
isotopically enriched 28Si quantum well is grown. It has a residual 29Si
concentration of 0.08% and was measured to be $9.0\pm 0.5~{}\rm nm$ thick.
Afterwards a $30~{}\rm nm$ thick Si70Ge30 spacer is grown to reduce strain
relaxation in the quantum well and separate it from the gate dielectric. The
heterostructure is finalized with a $1~{}\rm nm$ silicon cap Esposti  _et al._
(2022). The gate stack is separated from the heterostructure by $10~{}\rm nm$
Al2O3, formed by atomic-layer deposition (ALD) at 300 ∘C. The three gate
layers of the gate stack are made from Ti:Pd with thicknesses of 3:17, 3:27
and 3:27 nm and are patterned using electron beam lithography, electron beam
evaporation and lift off. Each layer is electrically isolated from the
previous layer by a $5~{}\rm nm$ Al2O3 dielectric grown by ALD. Above the
three gate layers a micro magnet is fabricated from Ti:Co (5:200 nm).

After fabrication every device was screened by measuring turn-on curves and
testing for gate leakage or shorted gates at $4.2~{}\rm K$ with a dipstick in
liquid helium. This high turnaround testing allows to verify the basic
functionality of the device and quickly filter out defective devices. After
verifying the functionality of all gates, NbTiN inductors are added to the
ohmic contacts to enable RF-readout. To address electrostatic discharge
concerns during rebonding, we screen the device a second time in liquid helium
to verify that no damage has been done. Then we cool down the devices in a
Bluefors LD400 dilution refrigerator to its base temperature of around
$10~{}\rm mK$.

##  Appendix B Setup

The room-temperature control electronics to operate this device are separated
into ac electronics in one rack and dc electronics in a second one. In the
latter, several in-house built Serial Peripheral Interface (SPI) racks host
$18\rm~{}bit$ Digital to Analog Converter (DAC) modules which provide the
required dc voltages. Voltage dividers were used to apply an accurate source-
drain bias when needed. The currents are measured with a Keithley 2000
Multimeter (placed in the ac rack) via an in-house developed transconductance
amplifier. The dc rack is powered by batteries which are continuously charged
via gyrators and filters.

The ac rack comprises the host computer, a Keysight chassis (M9019A) and an
additional dedicated RF SPI rack. The circuitry for RF reflectometroy
measurements consists of two in-house built RF sources, a combiner (Mini-
Circuits ZFSC-2-5-S+), a $15\rm~{}dB$ coupler (Mini-Circuits ZEDC-15-2B) at
the mixing chamber stage, a cryo-amplifier at the 4K stage (Cosmic Microwave
Technology Inc. CITLF3), a room temperature amplifier, two IQ-mixers and a
Keysight digitizer (M3102A). The coaxial lines from 4 K to the mixing chamber
flange are made from NbTiN to ensure a high signal quality and low thermal
conductance. From 4 K to room temperature, SCuNi-CuNi cables are used.
Discrete attenuators with a total attenuation of $23\rm~{}dB$ are distributed
over the various temperature stages on the downward path.

Next to the digitizer, several Keysight AWG modules (M3202A) are situated in
the same chassis and connected via a PCIe connection to a host computer.
SCuNi-CuNi $0.86\rm~{}mm$ coaxial cables are used from room temperature to the
mixing chamber plate. Also on these lines discrete attenuators are mounted,
with a total attenuation ranging from $12\rm~{}dB$ to $20\rm~{}dB$ (typically
we equip the barrier gates with lower attenuation than the plunger gates).
From the mixing chamber flange to the sample printed circuit board (PCB),
hand-formable 0.086" coaxial cables were used to route both RF and AWG
signals. Bias tees on the sample PCB combine the ac pulses and dc voltages.
Ferrite cores and dc blocks were installed at room temperature to suppress
$50\rm~{}Hz$ noise.

##  Appendix C Virtual Gate Matrix

The virtual gate matrix defining the virtual gates in the charge stability
diagrams of Fig. 1 is displayed in Fig. 4. Note that we constantly adapted the
virtual gate matrices throughout the measurements to improve the compensation
of cross capacitive effects on the plunger gates of the quantum dots and SETs.

Figure 4: Virtual gate matrix ($\mathbb{M}^{-1}$) during the recording of the
charge stability diagrams of Fig. 1

##  Appendix D Qualitative Tunnel Coupling Control

Figure 5 shows the influence of all barrier gates on the charge stability
diagrams of their neighbouring quantum dots. Figure 5b is replicated from
Figure 2. All barriers show similar influence on the charge stability diagram
as discussed by way of example for barrier ${\rm vB}_{23}$ in the main text.

Figure 5: Charge stability diagrams for all four quantum dot pairs for several
values of the voltage on the barrier gate between the respective dots.
Pictograms on the left indicate the quantum dot pair used in the respective
row. To ensure comparability every scan is around the (1,1,1,1) regime as
indicated.

##  Appendix E Electron Temperature and Detuning Lever Arm Calculation

To estimate the electron temperature, we measure the thermal broadening of
Coulomb peaks of SET S1 using the equations provided by Petit  _et al._
(2018). We sweep gate $\rm B_{1}$ as it has a smaller lever arm compared to
the SET plunger gate and therefore allows us to sweep across a Coulomb peak
with a much finer resolution, improving the fit quality. Figure 6a shows the
Coulomb diamonds that were used to calculate the lever arm of gate B1. We
combine the slopes $m_{S}$ and $m_{D}$ of the Coulomb diamonds to compute the
lever arm $\alpha_{B1}$ with
$\alpha_{B1}=\lvert\frac{m_{s}m_{D}}{m_{s}-m_{D}}\rvert$. The horizontal trace
at $V_{\rm SD}\approx-1150~{}\rm\mu V$ shown in Fig. 6c was used to upper
bound the electron temperature to $\rm T_{e}\leq 80~{}\rm~{}mK$.

Figure 6: a) Coulomb diamonds used to extract the lever arm of gate B1. White
dashed lines indicate the used slopes. b) High resolution interdot transition
of sensing dot S1 and $\rm QD_{2}$ showing the manual fit (dashed line) to
determine the lever arm ratio between the respective plunger gates. c)
Measured (dots) and fitted (solid line) Coulomb peak used to estimate the
electron temperature. The Coulomb peak is the smallest measured peak at the
effective zero bias voltage.

Furthermore we require the lever arms of the plunger gates to convert the
detuning axis $\epsilon_{ij}$ from gate voltage to energy. Due to the high
tunnel coupling, photon-assisted tunneling measurements with the available
microwave source were unsuccessful. Instead we estimate the lever arms of the
quantum dots via the slope of their interdot transitions.

Using Coulomb diamond measurements (see Fig 6a) we extract the lever arm of
gate $\rm B_{1}$. We convert the lever arm of gate $\rm vB_{1}$ to the lever
arm of virtual plunger gate $\rm vS_{1}$ from the ratio of the SET Coulomb
peak spacing. From here we can successively use the angle of the interdot
transitions to calculate the lever arm ratio between all other gates. For
example, Fig. 6b shows the manually fitted interdot transition used to
calculate the lever arm ratio of plunger gate of $\rm vS_{1}$ and $\rm
vP_{2}$.

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