# Enabling Full-Stack Quantum Computing with Changeable Error-Corrected Qubits

Anbang Wu
<EMAIL_ADDRESS>
UC  Santa Barbara  Keyi Yin
<EMAIL_ADDRESS>
UC  Santa Barbara  Andrew W. Cross
<EMAIL_ADDRESS>
IBM T.J Watson Research Center  Ang Li
<EMAIL_ADDRESS>
Pacific Northwest National Laboratory  Yufei Ding
<EMAIL_ADDRESS>
UC  Santa Barbara

###### Abstract

Executing quantum applications with quantum error correction (QEC) faces the
gate non-universality problem imposed by the Eastin-Knill theorem. As one
resource-time-efficient solution, code switching changes the encoding of
logical qubits to implement universal logical gates. Unfortunately, it is
still unclear how to perform full-stack fault-tolerant quantum computing
(FTQC) based on the changeable logical qubit. Specifically, three critical
problems remain unsolved: a) how to implement the dynamic logical qubit on
hardware; b) how to determine the appropriate timing for logical qubit
varying; c) how to improve the overall system performance for programs of
different features. To overcome those design problems, We propose CECQ, to
explore the large design space for FTQC based on changeable logical qubits.
Experiments on various quantum programs demonstrate the effectiveness of CECQ.

##  1 Introduction

Quantum computing suffers from device noise which greatly limits the problem
size a quantum device can address with a low failure rate [1]. Quantum error
correction (QEC) codes are widely studied to mitigate quantum noises and
enable fault-tolerant quantum computing (FTQC) [2]. QEC encodes a high-
fidelity logical qubit with a group of unreliable physical qubits (named data
qubits) and corrects potential errors on the logical qubit based on error
information extracted from data qubits. Experiments demonstrate the
reliability of quantum architectures based on QEC and the enablement of QEC on
realistic hardware has witnessed a series of breakthroughs recently [3, 4, 5,
6, 7, 8, 9, 10, 11]. Executing quantum applications upon any QEC code faces
the unique problem of gate nontransversality imposed by the Eastin-Knill
theorem [12], which indicates that not all logical gates in a universal gate
set (e.g., Clifford+T [2]) can be implemented transversely, i.e., by applying
physical gates where each acts on exactly one data qubit of the logical qubit.
For instance, the logical T gate $T_{L}$ is not a transverse gate of the
Steane code [13]. To build a universal gate set to accommodate any programs,
various protocols, e.g., magic distillation and code switching, are proposed
to implement non-transverse logical gates. Among them, code switching stands
out for its potentially smaller resource and time overhead [14] on future less
error-prone quantum hardware. The code switching protocol allows the
implementation of non-transverse logical gates by encoding the logical qubit
in different QEC codes along the time dimension. For instance, to implement
$T_{L}$ on a logical qubit of the Steane code, one potential code switching is
to transform the logical qubit to the Reed-Muller (RM) code which supports
transverse $T_{L}$. After $T_{L}$ is executed, we can then use another code
switching to transform the logical qubit back into the Steane code. Existing
efforts on code switching only consider implementing specific logical gates,
e.g., $T_{L}$. It is unclear how we can implement QEC with code switching (in
short, QEC-CS) on quantum hardware. Indeed, we discover a unique and
unexplored design space for implementing the QEC-CS architecture. Firstly, we
claim that each implemented logical qubit of QEC-CS should support a
changeable data qubit layout to allow two QEC code types. When the logical
qubit is switched from one code to the other code, the underlying data qubits
and error detection circuits will be changed accordingly. Secondly, we observe
that the data qubit layout optimization of the QEC-CS logical qubit involves
more factors. Compared to the single-typed QEC architecture [15], besides
error detection circuits, the layout of the QEC-CS logical qubit also affects
the reliability of code switching. Finally, considering the importance of
logical gates, the design of the QEC-CS architecture should balance the
performance of error detection, code switching, and logical gates
simultaneously. We should not only optimize the data qubit layout of one
logical qubit but also the placement of multiple QEC-CS logical qubits.
Overall, the architectural design space of QEC-CS identified by our paper is
far beyond the scope of existing works that map QEC to hardware [3, 4, 5, 6].
Existing works focus on the implementation of one single-typed logical qubit
and their optimization goal is only to reduce the error detection overhead of
the single-typed logical qubit. Besides the lack of efforts on architectural
design, we further observe that existing software support for FTQC [15, 16,
17, 18] misses unique compiler optimization opportunities in the QEC-CS
architecture. Conventionally, to adapt a general program to QEC architectures,
existing QEC compilers [15, 16] decompose the program into the Clifford+T
basis, map each program qubit to a logical qubit, and then execute the
resulting logical circuit in a similar way to treating quantum circuits
without QEC. We argue that this simple compilation support does not unveil the
computational potential of QEC-CS. Code switching, as the most important
enabler of the QEC-CS architecture, is an expensive QEC operation. Code
switching requires a series of noisy and time-consuming physical operations
between data qubits in one logical qubit [14]. Reducing the utilization of
code switching is critical for minimizing the space-time overhead and error
rate of quantum programs on the QEC-CS architecture. Unfortunately, code
switching still remains unoptimized in existing QEC compilers. Overall, to
efficiently utilize the QEC-CS architecture, it is critical to optimize the
code switching usage, rather than sticking to the conventional QEC compilers.
In this paper, we propose the first full-stack framework, named CECQ, to
provide architecture and software support for FTQC based on QEC-CS. Firstly,
we present a comprehensive architectural design for the QEC-CS logical qubit,
accounting for the data qubit layout changeability and the interplay of error
detection, code switching, and logical quantum gates. We observe that those
three QEC operations have different impacts on the architecture reliability
and space overhead. Their hardware implementation may even conflict with each
other. To address those problems and enable effective exploration of the large
architecture design space, we propose using the profiling data (e.g., impact
on logical operation error rates, consumed physical qubits) and structural
information (e.g., data qubit locations in an error detection circuit) of
those QEC operations to guide the search priority and circumvent
implementation conflicts. Experiments demonstrate the effectiveness of our
architectural design over the large search space. Secondly, we present a
compiler design that supports the efficient execution of quantum programs on
the QEC-CS architecture. On the one hand, we observe that a pair of code
switching operations can be used to execute more than the logical T gate
depending on the program context, saving program latency and improving
fidelity. On the other hand, we observe that executing too many logical gates
between a pair of code switching operations may instead hurt the program
fidelity considering the different error correction capabilities of the two
QEC codes being switched. Our compiler achieves a good balance for this unique
trade-off in the QEC-CS architecture and far surpasses existing QEC compilers
in reducing the space-time overhead of quantum programs, as demonstrated by
our experiments. Finally, we present a co-design of QEC-CS architecture and
compiler to further promote the computational potential of QEC-CS. We observe
that, for compiled quantum programs of distinguished features, regarding
different optimization metrics, it is better to use different connectivity
between logical qubits and place QEC-CS logical qubits accordingly. This is
the first co-design study of FTQC since existing works [3, 4, 5, 6] only
consider the simulation of one logical qubit. Our evaluation shows that the
co-design can further improve the performance of specific quantum programs in
particular metrics, e.g., the space-time overhead and the program fidelity.

##  2 Background

In this section, we would introduce three critical protocols for FTQC: QEC,
logical quantum gates, and the specific protocol that helps implement logical
gates, i.e., code switching in the paper. We would also introduce the
necessary background knowledge to implement QEC codes on quantum hardware.

###  2.1 Fault-tolerant Quantum Computing

-5pt -8pt

Figure 1: Error detection circuits to detect Pauli X errors from data qubits
$a,b,c,d$. R, I, and M are reset, identity gate, and measurement respectively.
Red X denotes Pauli X error.

The first enabler of FTQC is the QEC code, which is proposed by theorists to
eliminate quantum hardware noise. QEC codes encode a logical qubit with many
noisy physical qubits which are named data qubits in the QEC context. With
this redundancy, QEC codes can detect potential errors in data qubits of a
logical qubit by using error detection circuits. Figure 1 shows the circuit
used to measure the weight-four stabilizer operator $Z_{a}Z_{b}Z_{c}Z_{d}$, to
detect Pauli X errors that occurred on four data qubits $\\{a,b,c,d\\}$ (blue
dots). Likewise, the stabilizer operator $X_{a}X_{b}X_{c}X_{d}$ detects Pauli
Z errors on $\\{a,b,c,d\\}$. In error detection circuits, the error
information of data qubits is aggregated to the parity qubit $s$ (red dots) by
physical CX gates. For instance, in Figure 1, the X error on qubit $a$ at time
$t_{0}$ would lead to the X error on $s$ at $t_{1}$ and flip the result of the
following measurement operation. After error detection, the measurement result
will be fed into a QEC decoder to identify the erroneous qubit and suggest the
best error correction operations.

-10pt

Figure 2: Code conversion from the Steane code to the RM code [14]. Dotted
lines denote physical CX gates. EC means error detection and correction.

The second enabler of FTQC is fault-tolerant logical gates. For each
underlying physical gate of the fault-tolerant logical gate, if it induces
physical errors on data qubits, the induced errors should be detectable and
correctable in the current QEC code. Fortunately, transverse logical gates are
naturally fault-tolerant. Being transverse implies it is constructed by posing
exactly one physical gate on each data qubit of the logical qubit. For
instance, on a logical qubit $\bar{q}$ of the Steane code (in short, Steane
logical qubit) with data qubits $q_{1},q_{2},\cdots,q_{7}$, the logical H gate
($H_{L}$) is transversal and is defined by
$H_{L}\bar{q}=\otimes_{i=1}^{7}Hq_{i}$. Logical CX ($CX_{L}$) is also
transverse and is defined by
$CX_{L}\bar{q}_{0}\bar{q}_{1}=\otimes_{i=1}^{7}CXq_{0i}q_{1i}$. For transverse
logical gates, one physical gate error at most induces one data qubit error
per logical qubit, which is correctable for any QEC codes of code distance
$\geq$3 (e.g., Steane code) by definition (of code distance [2]).
Unfortunately, not all logical gates of one QEC code have a transverse
implementation, according to the Eastin-Knill theorem [12]. For instance, the
logical T gate is transversal in the 15-qubit Reed-Muller (RM) code (defined
as $T_{L}\bar{q}=\otimes_{i=1}^{15}T^{\dagger}q_{i}$) but is non-transverse in
the Steane code. Likewise, the logical H gate is non-transverse in the RM
code. To achieve universal FTQC with the Clifford+T basis, various schemes
(e.g., magic distillation [19] and code switching [20]) are proposed to
provide fault-tolerant implementations for non-transverse logical gates. Among
these schemes, code switching stands out for its potentially smaller resource-
time overhead [14] on future less erroneous hardware. For FTQC based on QEC-
CS, the third enabler is the code switching protocol. To implement non-
transverse logical gate fault-tolerantly, code switching encodes the logical
qubit in different QEC codes along the time dimension, e.g., switching between
the Steane and the RM code, which is widely studied in existing works [20,
14]. Commonly, to implement the logical T gate on a Steane logical qubit, we
would transform the logical qubit to the RM code. After the logical T gate is
transversely executed, we would then use one more code switching operation to
transform the logical qubit back into the Steane code. Figure 2 shows the code
switching from the Steane code to the RM code, which converts the Steane
logical qubit state into an RM logical qubit state. In the figure, one RM
logical qubit contains two Steane logical qubits, with $q_{15}$ used to
establish the connection between the two Steane logical qubits. The whole code
switching process in Figure 2 contains one logical qubit between two Steane
logical qubits, three physical CX gates, three Steane error detection rounds,
and one RM error detection round. The code switching from the RM code to the
Steane code is just the reverse of the process in Figure 2.

###  2.2 Enforcing QEC on Hardware

In many quantum devices (e.g., superconducting [21] and neutral atom hardware
[22]), the connectivity between physical logical qubits may be limited. In
such a case, the physical CX gate in error detection circuits, logical CX, and
code switching may be on non-neighboring physical qubits. To consider the
topology constraints, in case the parity qubit is not directly linked to data
qubits, we use the widely-used flag-bridge circuit [5, 3](see Figure 3) rather
than the SWAP approach for efficiency and high error detection accuracy [3].
In Figure 3, data qubits $\\{c,d\\}$ are not in the neighborhood of the parity
qubit $s$, which means we cannot apply CX gates between those data qubits and
$s$. The flag qubits $f$ (orange dots) neighboring $s$ would then be used to
help gather error information from those data qubits. The parity information
collected by $f$ would be propagated to $s$ by physical CX gates between them.
The flag-bridge circuit guarantees the fault tolerance of error detection. For
example in Figure 3, the Z error on $f$ may lead to correlated Z errors on
data qubit $\\{c,d\\}$. Fortunately, the Z error on $f$ would flip measurement
result on $f$, making the correlated Z errors on $\\{c,d\\}$ detectable and
correctable.

For logical CX and code switching, to perform physical CX gates between data
qubits that are not physically coupled, we use a GHZ-state based approach (see
Figure 4) rather than SWAP for low cost, as practiced widely by existing works
[23]. In Figure 4, we build a GHZ state using $\\{q_{i},\cdots,q_{i+k}\\}$ and
the remote CX gate between $q_{1}$ and $q_{0}$ is implemented by using the
prepared GHZ state. For simplicity, we say that qubits in the state
preparation part of Figure 4 (i.e., $q_{i},\cdots,q_{i+k}$) form a GHZ path to
connect two data qubits.

-5pt -2pt

Figure 3: The flag-bridge circuit to detect Pauli X errors from data qubits
$a,b,c,d$. R, H, I, and M are reset, Hadamard gate, identity gate, and
measurement respectively. Red Z indicates Pauli Z error.

-5pt -8pt

Figure 4: Remote CX between $q_{1}$ and $q_{0}$ using the GHZ state.

##  3 Design Considerations

In this paper, our major objective is to improve the overall fidelity as well
as reduce the space-time overhead of running quantum programs on the QEC-CS
architecture by orchestrating the architecture and software design. In this
section, we highlight the considerations and observations to achieve our
design objectives.

###  3.1 Problem Setting

In our architecture design for QEC-CS, we assume that the underlying quantum
hardware has enough qubits to accommodate logical qubits of the QEC code,
which is a common assumption for FTQC. We explicitly study the QEC-CS
architecture design with code switching between the Steane and RM code, but
our design is not limited to them and can be extended to general 2D color code
and 3D stabilizer color code. Further, we use the flag-bridge circuit in
Figure 3 for error detection and the GHZ-state-based method in Figure 4 for
the CX gate between non-neighboring physical qubits.

###  3.2 Architectural design for QEC-CS

Generally, to enforce QEC support on quantum hardware, we need to map data
qubits and error detection circuits of logical qubits to the hardware [3].
However, for the QEC-CS logical qubit design, we should further support
dynamic code switching between two QEC codes. Overall, when placing data
qubits of a QEC-CS logical qubit on hardware, we expect the overhead (e.g.,
involved qubit/gate count, latency) of executing error detection, logical CX,
and code switching on data qubits to be as small as possible. A QEC-CS logical
qubit with lower overhead is more reliable because using more qubits and more
gates would induce more error locations [2].

-8pt -5pt

Figure 5: An example data qubit layout for QEC-CS logical qubits, which only
minimizes the error detection cost.

Unfortunately, the overhead optimization of error detection differs from the
optimization of code switching, and logical gates. The error detection circuit
requires data qubits to be close to the parity qubit as much as possible so
that we can use fewer qubit resources (e.g., flag qubits) to gather error
information from data qubits that are not in the neighborhood of the parity
qubit. However, placing data qubits too close would hinder the implementation
of the logical CX gate as well as code switching. Figure 5 shows an example of
the data qubit layout that tries to minimize the qubit resource overhead of
error detection circuits. Below both code switching and logical CX, we need to
execute many physical CX gates between data qubits that are often not
neighbors. For example, for code switching in QEC-CS logical qubit
$\bar{q}_{i}$ in Figure 5(a), we need to execute a physical CX gate between
$q_{i2}$ and $q_{i9}$. To perform the CX gate on two non-neighboring data
qubits, we need a GHZ path to connect them, as shown in Figure 5. As we can
see, for code switching, the shortest GHZ path connecting data qubit $q_{i2}$
and $q_{i9}$ is blocked by $q_{i4}$; for logical CX, the shortest GHZ path
connecting $q_{i2}$ and $q_{j2}$ is also blocked by both $q_{i4}$. This means
placing data qubits too close may increase the overhead (e.g., the length of
GHZ paths) of implementing code switching and logical CX.

Similarly, the overhead optimization of code switching differs from the
optimization of the logical CX gate. For code switching, the logical CX is
between two Steane logical qubits that together form an RM logical qubit. All
data qubits and logical gates involved in the code switching are within one
logical qubit of QEC-CS. To reduce the space overhead of code switching, we
would make data qubits involved in the logical CX between two ‘interior’
Steane logical qubits as close as possible to reduce the length of GHZ paths.
However, this optimization may increase the overhead of the logical CX between
two QEC-CS logical qubits, similar to the discussion above. For example, in
Figure 5, the shortest GHZ path between $q_{i2}$ and $q_{j2}$ is blocked by
$q_{i9}$, which is involved in a physical CX gate of the code switching.
Overall, it remains unclear how to design the interior layout of a logical
qubit so that we can guarantee low overhead and good reliability for error
detection circuits, code switching, and logical gates, simultaneously. To make
good choices for the QEC-CS logical qubit design, we believe it is critical to
gather quantitative data showing the impacts of the three types of operations
on the reliability of the architecture based on QEC-CS.

Table 1: Pseudo-threshold of the Steane logical CX gate for different # flag
qubit, and GHZ path length (averaged for all pairs of data qubits).

-3.5pt# flag qubit -3.5pt GHZ path length | 0 | 1 | 2 | 3 | 4
---|---|---|---|---|---
1 | 0.0034 | 0.0022 | 0.0016 | 0.0012 | 0.0009
2 | 0.0017 | 0.0013 | 0.0010 | 0.0008 | 0.0006
3 | 0.0010 | 0.00081 | 0.00066 | 0.00054 | 0.00046

-5pt

Table 1 shows the profiling data for the logical error rate of the Steane
logical CX gate based on different design options for error detection and the
logical CX gate. In Table 1, the device noise follows the circuit noise model
[24], and the decoder for the Steane code is the look-up table decoder [25].
We observe that it is more critical to reduce the overhead of error detection.
One more flag qubit in the error detection circuit would decrease the pseudo-
threshold of the logical CX more than having one more edge in the GHZ path
between data qubits. This is because the error correction following the
logical CX gate could largely mitigate the negative effect of longer GHZ
paths. Further, increasing the overhead of error detection would also hurt the
fidelity of other logical operations, e.g., code switching and single-logical-
qubit gates. Further, we observe that the logical CX gate should be optimized
before code switching. This is because the logical CX gate may appear more
frequently in quantum programs. For example, quantum arithmetic circuits are
based on the Toffoli gate. In the fully-connected qubit layout, the decomposed
Toffoli gate has seven T gates and six CX gates [2]. Thus, a Toffoli gate at
most requires fourteen code switching operations as each logical T gate
requires two code switching operations. However, for a connectivity-limited
qubit layout, the overall CX count (i.e., 15) would surpass the amount of code
switching required, as long as each CX gate requires 0.5 SWAP gates for
routing. Note than this condition neglects the opportunity of reducing code
switching operations by compiler optimizations.

Observation 1: a good data qubit layout for a QEC-CS logical qubit should
first ensure the reliability of error detection, then improve the logical CX,
and finally optimize overhead of code switching by fine-tuning the data qubit
layout.

After the design of one QEC-CS logical qubit, the next step is to design the
layout of multiple QEC-CS logical qubits for running quantum programs. There
are two major design goals of placing multiple logical qubits. The first one
is to reduce the latency and resource overhead (i.e., GHZ path length) of
logical CX gates. The second one is to design the ‘logical’ connectivity
between logical qubits so that we can reduce the error rate/latency of quantum
programs by reducing the (logical) SWAP gates caused by routing. The placement
of multiple QEC-CS logical qubits has a direct impact on the overhead of the
logical CX gate. On the one hand, if we leave sufficient space between two
logical qubit blocks, there would be enough physical qubits for parallel GHZ
paths, thus reducing the latency of the logical CX gate. On the other hand,
placing logical qubits farther away would increase the GHZ path length between
two logical qubits thus decreasing the logical CX fidelity. Moreover, having
more ancillary physical qubits between logical qubits would increase the qubit
overhead of the overall logical qubit layout, which may instead cause the
increase of the space-time overhead of quantum programs. We argue that it is
more advantageous to place logical qubits close as the latency reduction by
the sparse logical qubit layout may not cancel out the physical qubit
overhead, in terms of the space-time overhead of quantum programs. The
placement of multiple QEC-CS logical qubits also directly affects the
‘logical’ connectivity between logical qubits. The relative location of
logical qubits affects whether it is worth enabling more direct logical CX
gates for better connectivity. On the one hand, higher logical connectivity
reduces the SWAP gate for routing thus improving program fidelity. On the
other hand, the long GHZ path of the logical CX gate between distant logical
qubits would affect the parallelism between logical CX gates since two
parallel logical CX gates cannot have intersected GHZ paths. That is, higher
logical connectivity may hurt the latency. For any input program, we can use
the QEC-CS compiler to predict the overhead of running a specific program on
QEC-CS architectures with different logical connectivity. With these data
obtained, we can then tune the logical qubit layout design accordingly to
achieve a lower error rate or space-time overhead for the considered program.

Observation 2: The placement of logical qubits affects the performance of
logical CX gates and the ‘logical’ connectivity. By co-designing the logical
qubit layout design and the compiler design, we may further improve the
fidelity or reduce the latency of specific programs.

###  3.3 Compiler design for QEC-CS

Different implementations of non-Clifford gates (e.g., T gate) often induce
different designs for compiling quantum programs on QEC architectures.
Unfortunately, existing QEC compilers cannot enable efficient quantum
computing on QEC-CS. They do not support the optimization of code switching,
which is the critical difference between QEC-CS to other QEC architectures. To
reduce the amount of code switching required by a quantum program, we need to
address two important problems. The first problem is determining the logical
gates we expect to execute with code switching. From the perspective of Steane
code, the nontransverse logical gate is $T_{L}$ and it should be executed by
using code switching. From the perspective of the RM code, we should execute
the nontransverse $H_{L}$ by using code switching. The second problem is
determining the number of logical gates we expect to execute after one
invocation of code switching. The Steane code and RM code share many
transverse logical gates, e.g., $CX_{L}$, $X_{L}$. If we are going to perform
a code switching from the Steane code mode to the RM code mode for $T_{L}$, it
is unclear whether we should switch back to the Steane code directly after the
$T_{L}$ executed or perform more transverse logical gates (e.g., $CX_{L}$) in
the RM code before switching back. To answer the first question, we argue that
most logical gates should be executed in the Steane code mode and use code
switching for $T_{L}$. The insight is that the logical gate of the Steane code
is more reliable than the ones of the RM code since there are fewer error
locations (e.g., gates in the error detection circuit) in the Steane code,
though being of the same distance as the RM code [26]. Thus, we should avoid
executing too many logical gates on the RM code mode of QEC-CS logical qubits.
While using code switching for $T_{L}$ is better than $H_{L}$, it does not
mean it is optimal to execute only one $T_{L}$ gate between a pair of code
switching operations (i.e., Steane$\to$RM$\to$Steane). As shown in Figure 2,
the code switching operation contains a Steane logical CX gate, three physical
gates between $q_{15}$ and other data qubits, and several ($\geq 5$) error
detection rounds, making it far more time-consuming and error-prone than
logical gates of the Steane code. Executing more logical gates in the RM code
may increase error rates, but it may also reduce the count of code switching,
thus improving fidelity, especially reducing latency. We observe that it may
be more advantageous to execute more than one $T_{L}$ gate after one code
switching operation, depending on the program context. To give an example
where executing more than one $T_{L}$ after code switching may be more
advantageous, let us consider the gate sequence in Equation 1:

$T_{L}\ q_{0};T_{L}\ q_{1};CX_{L}\ q_{0}\,q_{1};T_{L}\ q_{1},$ (1)

which is frequently appeared in various quantum programs [27] (e.g, arithmetic
circuits, Grover). Two logical qubits ($\bar{q}_{0}$ and $\bar{q}_{1}$) are
first switched from the Steane code to the RM code to perform the first two
$T_{L}$ gates. If we switch the two logical qubits back to the Steane code
after the two $T_{L}$ are executed, we would need another two code switching
to perform the last $T_{L}$ on $\bar{q}_{1}$. However, if we delay the
switching of two logical qubits behind the last $T_{L}\ \bar{q}_{1}$ executed,
then we can save two code switching on $\bar{q}_{1}$. Such a delay of code
switching is of merit, as long as the error rate/latency of two code switching
is larger than the error rate/latency difference between the RM CX and the
Steane CX. Indeed, this condition always holds as shown in Section 5. However,
we are not going to delay all code switching since having too many logical
gates executed in the RM code may hurt overall program fidelity as discussed
before. We can achieve a good balance by inspecting the program context (e.g.,
the gate sequence in Equation 1) and determining whether to delay code
switching according to fidelity/latency gain.

Observation 3: Most logical gates should be executed in the Steane mode of
QEC-CS logical qubits while the code switching should be applied in a context-
aware way to promote the computational benefit of the QEC-CS architecture.

##  4 Our Framework

In this section, we introduce the detailed implementation of the QEC-CS
architecture and compiler based on considerations and observations outlined in
Section 3.

###  4.1 The QEC-CS architecture

-8pt -8pt

Figure 6: Optimizing the data qubit layout of one QEC-CS logical qubit with
knowledge from error detection, code switching, and the logical CX.

-4pt

(a) (b) (c) (d) -8pt -8pt

Figure 7: Examples of placing multiple logical qubits. Green arrows denote
logical CX directions. (a) connectivity 4. (b) connectivity 4 rotated. (c)
connectivity 6. (d) connectivity 8.

####  4.1.1 Implementing one QEC-CS logical qubit

-11pt

In this section, we search for the data qubit layout of one QEC-CS logical
qubit according to Observation 1. The first step of the search is to guarantee
minimal overhead of error detection circuits. When implementing the error
detection circuit of any QEC code, to guarantee full-distance error
detection/correction [28], it is inevitable to use the flag-bridge circuit
shown in Figure 1. Besides the parity qubit, we need to use at least one flag
qubit for the weight-four stabilizer in the Steane code and RM code, and at
least three flag qubits for the weight-eight stabilizer in the RM code. Under
the requirement, the goal of this optimization step is to reduce the physical
gate overhead of error detection circuits since more gates in error detection
circuits indicate more error locations. Because of the potential connectivity
limitation of the underlying hardware, we may use ancillary qubits to help
build the error detection circuits [5]. In this section, we use the search of
the QEC-CS logical qubit based on the Steane code and RM code as an example.
Our strategy can be extended to find the layout for general 2D color codes
[14]. We first search for the physical qubit layout of the Steane code mode of
a QEC-CS logical qubit. Since the RM code is almost doubling the Steane code
(see Figure 2), determining the layout of the Steane code mode could simplify
the successive search for the RM code mode. The insight of searching for the
data qubit layout is to use the geometrical shape of stabilizer operators. As
shown in Figure 2, there are spatial relations between data qubits of the
Steane code, e.g., $q_{2}$ is on the bottom left of $q_{1}$. With those
spatial relations, we are able to find an initial data qubit layout for the
Steane code by placing data qubits according to the spatial relation, as shown
in Figure 6(a). With the data qubit layout of the Steane code mode found, the
next step is to determine the layout of the RM code mode. An initial layout of
the RM code mode can be found by mirroring the layout of the Steane code mode,
as shown in Figure 6(b). This initialization can reduce the overhead of some
error detection circuits, e.g., the one that measures
$Z_{5}Z_{6}Z_{12}Z_{13}$. We further fine-tune the data qubit layout for
smaller overhead of error detection circuits according to Equation 2:

$\small\forall s\in
S,\min_{ts\in\\{\uparrow,\downarrow,\leftarrow,\rightarrow,nop\\}}TOT\\_CX(\\{ts_{i}(q_{i}),\cdots\\}),\quad\\{q_{i},\cdots\\}\text{:
qb of }s$ (2)

The function $TOT\\_CX$ is computed as the total edge count of the smallest
bridge tree that connects all data qubits in an error detection circuit $s$.
The overall set of error detection circuits $S$ is organized by first weight-
eight stabilizers and then weight-four stabilizers. The optimization by
Equation 2 would be repeated several times (< 3) for a smaller overhead of
error detection. Figure 6(c) shows the optimized layout of the RM code mode of
the QEC-CS logical qubit. Further, we should reduce the cost of the logical CX
gate and the code switching operation. For these two operations, the source of
overhead is the GHZ path length between non-neighboring data qubits. The goal
of this step is thus to reduce the total lengths of GHZ paths while still
guaranteeing a small overhead of error detection. The insight for this step is
that to support remote CX between vertically distant data qubits, there should
be a vertical line of unoccupied physical qubits as the communication channel
(see Figure 6(d)). Likewise, for horizontally distant data qubits, there
should be a horizontal line of unoccupied physical qubits as the communication
channel. Such communication channels can be guaranteed by trying to move each
data qubit along a horizontal or vertical direction at most one step,
according to Equation 4.1.1 (‘EC’: error detection circuits): -10pt

$\displaystyle\min_{ts\in\\{\uparrow,\downarrow,\leftarrow,\rightarrow,nop\\}}\sum_{i}GHZ\\_LEN(ts_{i}(q_{i}),ts_{i}(q^{h}_{i}))+GHZ\\_LEN(ts_{i}(q_{i}),$
$\displaystyle ts_{i}(q^{v}_{i}))+TOT\\_CX(Steane\ EC+RM\ EC)$ (3)

-15pt

The function $GHZ\\_LEN$ is computed as the length of the shortest
uninterrupted GHZ path between data qubits. $q^{h}_{i}$ and $q^{v}_{i}$ denote
the qubits of the horizontal and vertical logical qubit neighbors,
respectively. Figure 6(d) shows the resulting layout for the QEC-CS logical
qubit. This small tweaking of the data qubit layout will not greatly influence
the overhead of error detection. The optimization for the logical CX gate
would also provide sufficient communication channels for the ‘interior’
logical CX of the code switching operation. Thus, to reduce the overhead of
remote physical CX in code switching, we would find the best location of
$q_{15}$ according to Equation 4 (‘CS’: code switching):

$\small\min_{loc(q_{15})}TOT\\_GHZ\\_LEN(CS)+TOT\\_CX(Steane\ EC+RM\ EC)$ (4)

Overall, the tuned layout of the QEC-CS logical qubit is shown in Figure 6(e).

####  4.1.2 Placing multiple QEC-CS logical qubits

-11pt

Table 2: Performance of logical CX gates for different logical qubit
placement. The error rate of logical CX is computed when the device error rate
is $10^{-6}$. The latency is normalized to the physical CX count.

Logical CX gates |  Connect-ivity-4 |  Connectivity-4 rotated |  Connect-ivity-6 |  Connect-ivity-8
---|---|---|---|---
Horizontal | Latency | 72.1 | — | 72.1 | 72.1
-3ptSteane CX | Error Rate | $3.9*10^{-9}$ | — | $3.9*10^{-9}$ | $3.9*10^{-9}$
Vertical | Latency | 20.6 | — | — | 20.6
-3ptSteane CX | Error Rate | $3.3*10^{-9}$ | — | — | $3.3*10^{-9}$
Diagonal | Latency | — | 30.9 | 30.9 | 72.1
-3ptSteane CX | Error Rate | — | $3.8*10^{-9}$ | $3.8*10^{-9}$ | $5.3*10^{-9}$
Horizontal | Latency | 82.4 | — | 82.4 | 82.4
-3ptRM CX | Error Rate | $3.7*10^{-8}$ | — | $3.7*10^{-8}$ | $3.7*10^{-8}$
Vertical | Latency | 41.2 | — | — | 41.2
-3ptRM CX | Error Rate | $2.7*10^{-8}$ | — | — | $2.7*10^{-8}$
Diagonal | Latency | — | 51.5 | 51.5 | 154.5
-3ptRM CX | Error Rate | — | $3.0*10^{-8}$ | $3.0*10^{-8}$ | $3.9*10^{-8}$

-8pt

There is a large amount of freedom when placing logical qubits. We can tile
logical qubits along horizontal, vertical, or diagonal directions, as shown in
Figure 7, where logical qubit layouts with different connectivity are
demonstrated. Table 2 shows the latency and fidelity of logical CX gates on
different layouts. The data are obtained by simulating the QEC code under the
circuit noise model. Layouts with different connectivity have their own
advantages. Higher-connectivity layouts usually induce fewer SWAP gates than
lower-connectivity layouts, thus can produce more reliable program outcomes.
For example, for the connectivity-4 layout, if we perform a (Steane) logical
CX gate along the diagonal direction, we need one logical SWAP gate along the
vertical direction plus one horizontal logical CX gate, leading to an error
rate of $1.4*10^{-8}$ when the device error rate is $10^{-6}$ (see Table 2).
In contrast, on the connectivity-8 layout, the diagonal (Steane) logical CX
gate is directly executable, with a lower error rate at $5.3*10^{-9}$ (see
Table 2). Thus, establishing direct logical CX gates between distant logical
qubits to increase connectivity may boost the reliability of the resulting
QEC-CS layout. However, higher connectivity of the layout may instead hurt the
parallelism in logical CX gates. For two logical CX gates, if their
communication channels (green dots in Figure 6) intersect with each other,
then these two logical CX gates cannot be executed at the same time. For
example, on the connectivity-8 layout, for a logical qubit $q_{i}$, denoting
its upper left, upper, left logical qubits as $q_{i+1},q_{i+2},q_{i+3}$,
$CX_{L}q_{i}q_{i+1}$ and $CX_{L}q_{i+2}q_{i+3}$ cannot be concurrently
executed, though these qubits are neighboring to each other in the layout.
Generally, the larger distance of two logical qubits of one logical CX gate
is, the more logical CX gates may lag behind. Moreover, the communication
channels of data qubits in the same logical qubit may also interfere with each
other. As shown in Table 2, in the connectivity-8 layout, the latency of
diagonal logical CX gates is far longer than the vertical logical CX gates.
Different layouts may fit programs of different features and thus provide
opportunities for architecture-compiler co-design. For example, if one
compiled program does not have much parallelism between logical CX gates,
e.g., the UCCSD benchmark, using the connectivity-8 layout may be better than
other layouts in terms of fidelity and latency of executed logical CX gates.
On the other hand, for the compiled program without many global and long-
distance logical CX gates, using the connectivity-4 (rotated) layout may
reduce the space-time overhead of the program while still maintaining the same
level of fidelity. Therefore, we can pick the best layout for a compiled
program according to its logical CX feature. This co-design can further
promote the computational potential of fault-tolerant quantum computing based
on code switching. Overall, in Section 5, we have provided more quantified
performance data for qubit layouts in Figure 7 and demonstrated the benefits
of architecture-compiler co-design.

###  4.2 Compiler for QEC-CS

Table 3: Operations of the logical qubit in Figure 6(e). The normalization
stays the same for $p_{e}<10^{-4}$. EC: error detection and correction.

Logical op | RM CX | RM 1q gate | Steane CX | Steane 1q gate | Code switching
---|---|---|---|---|---
Normalized Infidelity |  $\sim$8.8 Steane CX |  $\sim$2.6 Steane CX |  1.0 Steane CX |  $\sim$0.2 Steane CX |  $\sim$4.1 Steane CX
Normalized Latency |  $\sim$5.5 Steane EC |  $\sim$3.0 Steane EC |  $\sim$2.9 Steane EC |  $\sim$1.0 Steane EC |  $\sim$9.1 Steane EC

-8pt

To provide program compilation support for the QEC-CS architecture, we need to
address two major tasks: QEC-CS architecture abstraction and code switching
optimization.

##### QEC-CS architecture abstraction.

The first task is to abstract the QEC-CS architecture. For comprehensive
compiler optimization, this abstraction should expose the logical qubit
topology and basic operations (i.e., the ISA) of the QEC-CS architecture. The
coupling graph of logical qubits can be directly extracted from the given QEC-
CS architecture. As for the ISA of the QEC-CS architecture, we would expose
two more instructions besides Clifford+T logical gates. The first instruction
is EC which means to perform error detection and correction at the current
time point. The instruction is helpful for quantum computing involving many
logical qubits where the independence of error correction on each logical
qubit is demanded. The second instruction is CS which means to perform the
code switching process at the current time point. Since the resource and time
overhead of switching Steane code to RM code and switching RM code to Steane
code is almost the same, one instruction for the code switching process is
enough. The CS instruction provides the compiler with the ability to control
code switching and unveil the computational advantage of the QEC-CS
architecture, as discussed in Section 3. Further, to achieve a fine-grained
compilation, it is important to obtain the fidelity and latency data of each
instruction of the QEC-CS architecture. The fidelity of the CS instruction and
logical gates (e.g., $CX_{L}$, $H_{L}$, $T_{L}$) is simulated by our QEC
simulator that adopts the circuit noise model, the stabilizer tableau
representation [24] and the lookup table decoder. Note that when simulating
the fidelity of the logical gate, we assume there is one EC instruction
following the logical gate. For the QEC-CS architecture, the fidelity of the
logical CX gate may not be uniform since the GHZ path length of the logical CX
gate may vary. We would label each edge in the coupling graph of logical
qubits with the fidelity of the logical CX related to the edge. The
quantification of the non-uniformity of logical CX gates provides the compiler
with the ability to perform fidelity-aware routing. As for the instruction
latency, the time overhead of the CS and EC operations can be directly
estimated from their specific implementations in the QEC-CS architecture. The
latency of single-logical-qubit gates is almost equivalent to the latency of
one physical single-qubit gate. The latency of logical CX contains two parts:
the GHZ state preparation, and the remote CX gate protocol based on the GHZ
state, as shown in Figure 4. Since the preparation of the GHZ state is to
perform two rounds of CX gates between neighboring physical qubits, the
latency of GHZ preparation is not related to the GHZ path length. Thus, all
logical CX gates have the same latency data and can be estimated from Figure
4.

Overall, with the proposed abstraction of the QEC-CS architecture, we can
adapt existing Clifford+T compilers to provide initial optimizations (e.g.,
reducing T gate counts, and communication routing) for quantum programs on the
QEC-CS architecture. However, existing compilers are far from optimal for the
QEC-CS architecture since they do not optimize the code switching operation
which is critical for the QEC-CS architecture.

##### Optimization of Code Switching.

The second task is to reduce the usage of the code switching which is
necessary but has a negative impact on the fidelity and time overhead of
compiled programs. Conventionally, we would use two code switching operations
for a logical T gate with one before it and one behind it. Here, we propose a
novel compiler pass that reduces the amount of the code switching operations
required by a quantum program in a context- and fidelity-aware way, as
discussed in Section 3.3 (Observation 3). We describe our compiler pass for
code switching optimization with the following steps.

Step 1: Blocking. For a given circuit, we search for the next (logical) T
gate. Assuming the program qubit associated with this T gate is $q_{0}$, we
create a new block $blk$ that contains the T gate. We denote the current qubit
list of $blk$ by $qlist$. For $q_{i}$ in $qlist$, we would also add other
gates that are close to $blk$ and are applied on $q_{i}$ to $blk$ until the
new gate on $q_{i}$ is H gate. We will update $qlist$ in this process since CX
gates may have been added to $blk$. We would continue to add new gates to
$blk$ until $qlist$ is not changed. This block represents the largest scope of
the code switching on $q_{0}$.

Step 2: Gate reordering. In this step, will try to move the CX, X, and Z gates
of $blk$ outside this block by circuit writing. Note that the $X$ and $Z$ can
always be moved out with commuting rules in [29]. This step is to remove
unnecessary gates outside the scope of the code switching on $q_{0}$. In this
way, we can keep most gates executed in the Steane code mode of QEC-CS logical
qubits, and only execute necessary gates in the RM code mode. This step can
reduce the latency and improve the fidelity of executing $blk$ with code
switching.

Step 3: Block refining. For each CX gate $g$ in $blk$, computing the fidelity
of $blk$ if we mark $g$ to be executed by the Steane code mode. If the
fidelity is improved, we would split $blk$ into two parts, each part
representing a new scope of the code switching on $q_{0}$. We will repeat this
step until no splitting is possible. The goal of this step is to find the
largest scope for the code switching on $q_{0}$ where no fidelity loss is
caused by executing logical gates in the RM code mode. We will repeat the
above three steps until no new blocks are found. Finally, we would add the CS
instructions at the start and end of each refined block. The start and end of
each refined block in Step 3 represent the optimized timing of applying code
switching on related logical qubits. In many cases, the refined block in Step
3 contains more than one logical T gate, which enables more efficient
utilization of code switching.

-5pt -5pt

Figure 8: An circuit (decomposed Toffoli gate) for illustrating code switching
optimization.

As an example of the proposed code switching optimization, let us consider the
circuit in Figure 8. Without code switching optimization, for the logical
qubit in Table 3, the code switching count, infidelity (normalized to # Steane
CX), and latency (normalized to # Steane EC) for the example circuit are 14,
82.0, and 167.8, respectively. With the proposed code switching optimization,
the block found is highlighted with dotted lines in Figure 8. Then, the code
switching count, infidelity, and latency for the example circuit are reduced
to 6 (by 57.1%), 80.4 (by 2.0%), and 105.4 (by 37.2%), respectively.

##  5 Evaluation

In this section, we first evaluate the logical qubit design and then evaluate
the optimization of code switching as well as the co-design between
architecture and compiler.

###  5.1 Experiment Setup

##### Benchmark programs

We consider two categories of benchmark programs obtained from [30], as shown
in Table 5. The first category of benchmarks focuses on implementing
arithmetic functions. These quantum programs are subroutines of large quantum
applications. The second category of benchmarks aims to solve practical
problems, e.g., Grover’s algorithm, quantum walking, and Unitary Coupled
Cluster ansatzes (UCCSD). For quantum walking, we specifically select the
Binary Welded Tree (BWT) algorithm. For UCCSD, we simulate the $\text{CH}_{4}$
molecule. All programs are decomposed into the Clifford+T gate basis.

##### Baseline

We are the first full-stack framework for QEC-CS. Different baselines here are
designed to unveil the huge space of architecture and compiler optimization
and provide an in-depth analysis of our design. For architecture design, four
schemes for generating QEC-CS logical qubits are evaluated. The first one,
named OECF, optimizes the resource overhead of error detection circuits as the
first priority. OECF is the layout design proposed in this paper. The second
one, named OCSF, optimizes the resource overhead of the code switching
operation as the first priority. The third one, named OLCF, optimizes the
resource overhead of the logical CX gate as the first priority. The fourth
one, named OEL, evenly places data qubits of a logical qubit respecting the
underlying architecture. It first allocates the location of data qubits and
then permutes the location of these data qubits for the best error correction
capability, cheapest logical CX gates, and code switching in turn. Figure 9
shows logical qubit layouts generated by the four schemes.

-6pt -8pt

Figure 9: QEC-CS logical qubits by four different schemes.

For compiler optimizations for code switching, we evaluate two schemes. The
first one, named AgnosticCS, is context-agnostic which always uses two code
switching operations for a logical T gate (Steane mode $\to$ RM mode $\to$
Steane mode). AgnosticCS is the common strategy of using code switching in
existing works. The second one, named AwareCS, is context-aware which executes
usually more than one logical gate in the RM mode, and would always try to
reduce the usage of code switching as long as no fidelity loss is observed.
AwareCS is the optimization proposed in this paper. For compiler optimizations
except for code switching, they are not the focus of this paper and we adopt
existing compiler toolkits for them. Specifically, we use PyZX [31] to
optimize T gate counts and Qiskit [21] to optimize CX gate counts (from
unitary decomposition and remote CX gate routing).

##### Metircs

For the architecture design, the main metrics are the resource overhead,
latency and fidelity of error detection, code switching, and logical CX gates.
These metrics quantify the performance of one QEC-CS logical qubit. Besides,
we also consider the space-time overhead (‘# physical qubit used * latency’)
and SWAP cost required to execute benchmark programs, in order to evaluate the
performance of the placement of multiple logical qubits. For the compiler
design, three major metrics are considered. The first one is the code
switching count required for a quantum program. We expect to reduce code
switching operations. The remaining two are the overall program fidelity and
latency, which are conventional compiler metrics.

##### Device noise model and error decoding

We assume a circuit noise model [24] with a physical error probability $p_{e}$
for the single-qubit depolarizing error channel on single-qubit gates, the
two-qubit depolarizing error channel on two-qubit gates, and the Pauli-X error
channel on measurement and reset operations. For error decoding of the QEC-CS
architecture, we use the look-up table decoder for correcting data qubit
errors induced by one physical gate. We would add one error detection round
behind each logical gate.

Table 4: Resource, latency, and fidelity data of QEC-CS logical qubit layouts.
OECF, OCSF, OLCF: optimize the resource overhead of error detection circuits
(EC), code switching (CS), logical CX in the first priority, respectively.
OEL: optimize even distributed data qubit layout. ‘OECF’ is the one proposed
in this paper. The operation latency data are normalized to physical CX
counts. REM-CX: physical CX gate between non-neighboring qubits.

Arch Layouts | Resource Overhead | Operation Latency | Pseudo-threshold
---|---|---|---
Tot. # CX for Steane EC |  Tot. # CX for RM EC |  Avg. REM-CX length for CS |  Avg. REM-CX length for Steane $CX_{L}$ |  Avg. REM-CX length for RM $CX_{L}$ |  # physi- cal qubit per logi- cal qubit |  Steane EC gate |  RM EC gate |  Code Switching |  Avg. Steane $CX_{L}$ |  Avg. RM $CX_{L}$ |  Steane 1q gate |  Avg. Steane $CX_{L}$ |  RM 1q gate |  Avg. RM $CX_{L}$ |  Code switching
OECF | 40 | 152 | 3.7 | 9.64 | 10.73 | 42 | 24.8 | 74.4 | 225.1 | 46.35 | 61.80 | $1.4*10^{-3}$ | $2.8*10^{-4}$ | $1.1*10^{-4}$ | $3.1*10^{-5}$ | $6.8*10^{-5}$
OCSF | 68 | 268 | 1.7 | 11.14 | 10.83 | 36 | 69.2 | 187.8 | 487.2 | 41.20 | 82.40 | $5.5*10^{-4}$ | $1.5*10^{-4}$ | $3.8*10^{-5}$ | $1.6*10^{-5}$ | $2.9*10^{-5}$
OLCF | 68 | 236 | 7.5 | 9.50 | 9.50 | 30 | 69.2 | 190.2 | 529.8 | 30.9 | 56.65 | $5.5*10^{-4}$ | $1.7*10^{-4}$ | $4.8*10^{-5}$ | $2.1*10^{-5}$ | $2.5*10^{-5}$
OEL | 40 | 212 | 6.7 | 9.57 | 9.67 | 40 | 24.8 | 115.4 | 277.4 | 36.05 | 56.65 | $1.4*10^{-3}$ | $2.8*10^{-4}$ | $5.9*10^{-5}$ | $2.4*10^{-5}$ | $3.8*10^{-5}$

Table 5: Compilation results on the square grid of logical qubits generated by
OECF. ‘Normalized infidelity’: program infidelity normalized to Steane logical
CX counts (for $p_{e}<10^{-4}$). ‘Fidelity point’: program fidelity when
$p_{e}=10^{-6}$. The latency data is normalized to physical CX counts.

Program | # qubit | # gate | # CX | OECF+AgnosticCS |  OECF+AwareCS (Optimizations proposed in this paper)
---|---|---|---|---|---
Normalized infidelity |  Fidelity point | Latency |  Space-time Overhead | # CS |  Normalized infidelity |  Fidelity point | Latency |  Space-time Overhead | # CS
Elementary Function |  Multi-qubit XOR | 20000 | $2.19*10^{6}$ | $1.79*10^{6}$ | $4.76*10^{6}$ | 98.3% | $1.47*10^{8}$ | $1.24*10^{14}$ | $5.60*10^{5}$ | $4.72*10^{6}$ | 98.3% | $1.01*10^{8}$ | $8.51*10^{13}$ | $3.20*10^{5}$
Ripple-Carry Adder | 30000 | $2.27*10^{6}$ | $1.97*10^{6}$ | $4.20*10^{6}$ | 98.5% | $9.85*10^{7}$ | $1.24*10^{14}$ | $4.20*10^{5}$ | $4.17*10^{6}$ | 98.6% | $6.39*10^{7}$ | $8.35*10^{13}$ | $2.40*10^{5}$
Ripple-Carry Comparator | 30000 | $2.39*10^{6}$ | $2.06*10^{6}$ | $4.29*10^{6}$ | 98.4% | $1.00*10^{8}$ | $1.27*10^{14}$ | $4.20*10^{5}$ | $4.26*10^{6}$ | 98.5% | $6.63*10^{7}$ | $8.35*10^{13}$ | $2.40*10^{5}$
Quantum Application | Grover | 38 | $1.05*10^{6}$ | $6.30*10^{5}$ | $3.71*10^{6}$ | 98.7% | $1.33*10^{8}$ | $2.12*10^{11}$ | $5.79*10^{5}$ | $3.66*10^{6}$ | 98.7% | $8.56*10^{7}$ | $1.37*10^{11}$ | $3.31*10^{5}$
BWT Oracle | 28 | $1.03*10^{6}$ | $5.98*10^{5}$ | $3.81*10^{6}$ | 98.6% | $1.38*10^{8}$ | $1.62*10^{11}$ | $6.06*10^{5}$ | $3.77*10^{6}$ | 98.6% | $8.80*10^{7}$ | $1.03*10^{11}$ | $3.46*10^{5}$
UCCSD | 16 | $1.07*10^{6}$ | $1.79*10^{5}$ | $4.70*10^{6}$ | 98.3% | $2.36*10^{8}$ | $1.58*10^{11}$ | $8.23*10^{5}$ | $4.70*10^{6}$ | 98.3% | $2.36*10^{8}$ | $1.58*10^{11}$ | $8.23*10^{5}$

-4pt

(a) (b) (c) -8pt -5pt

Figure 10: Data in the plot is ‘overhead of the tested logical qubit
design$/$overhead of OECF’*100%-1. Logical qubits are arranged in a square
grid.

-4pt

(a) (b) (c) -8pt -5pt

Figure 11:  Data in the plot is (‘overhead of AgnosticCS$/$overhead of
AwareCS’*100%-1) on logical qubits generated by OCSF, OLCF and OEL.

-4pt (a) (b) (c) -8pt -12pt

Figure 12: The effect of connectivity when placing multiple logical qubits
generated by OECF.

###  5.2 Experiment Results

Table 4 shows the performance of the different logical qubit designs in terms
of resource overhead, latency, and fidelity. The ‘REM-CX length’ in Column 4-6
refers to the Manhattan distance between two data qubits we are going to
perform a physical CX gate on. The ‘REM-CX length’ is equal to the GHZ path
length plus one. Figure 9 shows the performance of different logical qubit
designs in the quantum program context. Table 5 and Figure 10 illustrate the
performance of code switching optimizations proposed in the paper. Figure 12
demonstrates the effect of connectivity when placing multiple logical qubits.
‘Connectivity-4/6/8’ means to let each logical qubit have 4/6/8 neighboring
logical qubits when placing multiple logical qubits. The ‘Connectivity-4
rotated’ architecture is achieved by rotating the ‘Connectivity-4’
architecture by $\frac{\pi}{4}$, as shown in Figure 7. Overall, compared to
other logical qubit designs (OCSF, OLCF, and OEL), the proposed logical qubit
design (OECF) on average reduces the error rate, space-time overhead, and
latency of test programs by 99.3%, 43.9% and 75.1%, respectively. Moreover, on
the proposed logical qubit design, compared to AgnosticCS, the proposed
AwareCS reduces the space-time overhead and code switching counts of test
programs by 43.8% and 62.5%, respectively. This benefit of AwareCS is not
limited by the logical qubit design. Finally, the results show that increasing
the connectivity between logical qubits does not necessarily induce a better
FTQC platform and different programs favor different logical qubit layouts. We
elaborate on these conclusions in the following analysis.

-5pt

####  5.2.1 The effect of logical qubit design

-10pt

##### Firstly, it is critical to reduce the resource overhead of error
detection circuits as the first priority when designing a logical qubit.

As shown in Table 4, compared to OCSF and OLCF, OECF has higher resource
overhead for code switching and logical CX gates, respectively. However, OECF
has the highest error threshold for all logical operations. This indicates
that error detection has the largest impact on the fidelity of logical
operations and OECF’s low overhead for error detection guarantees the
reliability of logical operations. The OEL logical qubit has the second-best
error threshold, also due to its specific optimizations for error detection
circuits. Moreover, OECF logical qubits are the most reliable for quantum
programs. As shown in Figure 9, OECF reduces the error rate of (six) test
programs on average by 138.8%, 113.1%, and 46.0%, compared to OCSF, OLCF, and
OEL, respectively.

##### Secondly, the latency of error detection circuits is also the most
important factor in the space-time overhead of quantum programs.

Though the OECF logical qubit has the most physical qubits per logical qubit
(see Table 4 Column 6), the smallest latency overhead of OECF logical qubits
(see Table 4 Column 2, 3) still guarantees the smallest space-time overhead
for quantum programs. As shown in Figure 9, OECF reduces the space-time
overhead of (six) test programs on average by 74.4%, 46.0%, 11.2%, compared to
OCSF, OLCF, and OEL, respectively. This is because each logical gate of a
quantum program is often followed by an error detection operation. This
amplifies the effect of the error detection latency for the overall program
latency. Indeed, as shown in Figure 9, OECS reduces the latency of test
programs on average by 103.4%, 104.8%, 17.0%, compared to OCSF, OLCF, and OEL,
respectively.

##### Thirdly, the optimization of logical CX gates is more important than the
optimization of code switching.

With similar error detection overhead, OCSF and OLCF show better code
switching and logical CX gates, due to their specific optimizations toward
code switching and logical CX gates, respectively. Inspecting Figure 9(a)(b),
OLCF induces 9.2% lower program error rate and 15.8% lower space-time
overhead, on average for test programs. This is because, after the proposed
compiler optimization for code switching, the number of logical CX gates is on
average 3.38 times more than the number of code switching (see Table 5 Column
5, 15) in test programs, making the optimization of logical CX gates more
advantageous. Ideally, for most Toffoli-gate based quantum programs, without
considering the overhead of SWAP-based routing, the logical T gate count is at
most 16.7% larger than the logical CX gate count (see Figure 8). On the other
hand, as shown in Table 5, one logical T gate on average induces 1.14 code
switching operations (see Table 5 Column 10 and 15). This means in a Toffoli-
gate based program, the number of code switching operations is at most 33.0%
larger than the number of logical CX gates. Thus, the logical CX count is
larger than the code switching count in the routed circuit, as long as each
logical CX gate requires 0.11 logical SWAP gates for routing. Therefore, in
most connectivity-constrained architectures, optimizing logical CX gates is
more critical than optimizing code switching.

##### Finally, incorporating QEC code information into the layout design is
critical for logical qubit design.

Compared to OECF, OEL first determines the data qubit layout according to the
underlying hardware topology. Though we have tried to improve the performance
of the logical qubit by OEL (in terms of error detection, logical CX and code
switching), the logical operations by OECF, especially the ones related to the
RM code mode, are more reliable than those by OEL, as shown in Table 4 Column
11-15. Moreover, as shown in Figure 9, compared to OECF, OEL on average
increases the program error rate, latency, and space-time overhead of test
programs by 46.0%, 17.0% and 11.2%, respectively.

-5pt

####  5.2.2 The effect of code switching optimization

-10pt

The optimization of code switching is critical for reducing the space-time
overhead of quantum programs. As shown in Table 5, compared to
‘OECF+AgnosticCS’, ‘OECF+AwareCS’ on average reduces the space-time overhead,
and code switching count of test programs by 43.8% and 62.5%, respectively.
This demonstrates that the code switching optimization would induce
significant space-time overhead reduction. This observation can be further
explained with two facts. Firstly, code switching widely exists in test
programs. For quantum programs executed with ‘OECF+AgnosticCS’, the code
switching count is on average about 62.2% of the logical CX count. Secondly,
the code switching operation is far more time-consuming than logical gates. As
shown in Table 4, the latency of code switching is 8.72, 2.99, 3.16, and 1.65
times the latency of ‘Steane 1q gate+EC’, ‘Steane CX gate+EC’, ‘RM 1q
gate+EC’, and ‘RM CX gate+EC’, respectively. As for the fact that AwareCS does
not show benefits on the UCCSD benchmark, it is because each logical T gate in
the UCCSD circuit is followed by a logical H gate, providing no opportunities
for code switching optimization. Fortunately, this is not a common pattern in
quantum programs, especially for Toffoli-gate-based programs (e.g., Grover).
Further, the benefit of AwareCS is significant even when logical qubit design
changes. As shown in Figure 11, compared to AgnosticCS, AwareCS on average
reduces the space-time overhead of test programs on OCSF, OLCF, and OEL
logical qubits by 46.4%, 52.1%, and 43.6%, respectively. This is because the
logical qubit design will not change the occurrence of code switching in
quantum programs and the latency of code switching is always far longer than
other logical operations in different logical qubit designs (see Table 9
Column 8-12). The benefit of AwareCS would become even more remarkable when
the logical qubit connectivity is higher. This is because the logical CX count
of test programs on highly-connected architecture would be smaller, amplifying
the effect of code switching.

-5pt

####  5.2.3 Architecture-Compiler Co-design

-10pt

##### No layout is universally better:

For physical quantum hardware with constrained connectivity between physical
qubits, enforcing higher connectivity between logical qubits when placing
multiple logical qubits does not necessarily induce a better computing
platform. As shown in Figure 12(b), compared to the connectivity-4 setting
(where logical qubits form a square grid), the connectivity-6 and
connectivity-8 setting does improve the fidelity of quantum programs because
they greatly reduce the SWAP gate count as shown in Figure 12(a). However, the
connectivity-8 setting induces higher space-time overhead than the
connectivity-4 setting, as shown in Figure 12(c). This is because logical CX
gates in the diagonal direction hurt the parallelism in logical CX gates and
induce extra latency (see Table 2). Also, as shown in Figure 12(c), the
connectivity-6 setting induces higher space-time overhead than the rotated
connectivity-4 setting. In this case, the horizontal logical CX gate takes
longer time than the diagonal logical CX gate (see Table 2). Overall, it is
reasonable to match the connectivity of logical qubits with the connectivity
of physical qubits. Enforcing higher connectivity between logical qubits may
not simultaneously provide benefits to fidelity and space-time overhead.

##### Architecture-Compiler Co-design:

While it is not possible to achieve better performance of all programs by
simply enforcing higher connectivity between logical qubits, it is possible to
promote the performance of some specific quantum programs with the compiler
output in Figure 12. For example, to achieve the smallest space-time overhead
while allowing slightly ($<2\%$) higher error rate of test programs (than on
the connectivity-4 layout), we can use the connectivity-6 layout for the UCCSD
benchmark and ‘Connectivity-4 rotated’ layout for the remaining programs.
Likewise, to achieve the lowest error rate while allowing slightly ($<2\%$)
higher space-time overhead of test programs (than on the connectivity-4
layout), we can use the connectivity-6 layout for the ripple-carry adder and
comparator benchmark and connectivity-8 layout for the remaining programs. The
ability of adjusting QEC-CS architecture provides us the opportunity to co-
design with the compiler to improve the performance of specific quantum
programs.

##  6 Related Work

Compilers for Programs upon QEC codes: Lao et al. [32] proposed a mapping
process to execute lattice surgery-based quantum circuits on surface code
architectures. Ding et al. [18] and Paler et al. [17] studied the compilation
of magic state distillation circuits, which is another way to implement the
logical T gate. Javadi et al. [33] and Hua et al. [16] studied the topological
routing of logical CX gates over the surface code. These works assume a
readily available FTQC architecture and do not consider implementing the QEC
code on hardware. Besides, those papers do not consider the optimization of
the code switching operation.

Implementing the QEC architecture: Reichardt [34] and Chamberland et al. [4]
respectively proposed planar and trivalent qubit layouts to synthesize the
color code. Chamberland et al. [6] introduced heavy architectures to map the
subsystem code and the surface code. Wu et al. [3] proposed an automated
method to stitch the surface code to superconducting quantum hardware. Those
efforts focus on one QEC code and one logical qubit. Those works cannot be
simply extended to support the code switching operation which involves dynamic
conversion between two QEC codes, let alone providing the compiler
optimization for code switching.

##  7 Conclusion

In this paper, we propose the first full-stack framework, named CECQ, from
architecture design to compiler design, to enable fault-tolerant quantum
computing based on code switching. Our framework searches for architecture
designs of logical qubits by inspecting the feature of QEC protocols, e.g.,
error detection and code switching. Afterward, our framework proposes context-
aware compilation optimizations to avoid unnecessary invocations of the code
switching operation, which are more erroneous and time-consuming than logical
gates. Finally, our framework presents the archi-tecture-compiler co-designs
to further unveil the computational potential of quantum computing based on
code switching. Overall, our paper presents the first systematic exploration
of code switching for FTQC, unveiling and crystallizing the extensive design
space of QEC-CS.

## Acknowledgment

This material is based upon work supported by the U.S. Department of Energy,
Office of Science, National Quantum Information Science Research Centers,
Quantum Science Center. Andrew W. Cross would like to acknowledge the support
from the U.S. Department of Energy, Office of Science, National Quantum
Information Science Research Centers, Co-design Center for Quantum Advantage
(C2QA) under contract number DESC0012704. The Pacific Northwest National
Laboratory is operated by Battelle for the U.S. Department of Energy under
Contract DE-AC05-76RL01830. This work was also supported in part by NSF
2048144, NSF 2138437 and Robert N. Noyce Trust.

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