# Application of Distributed Arithmetic to Adaptive Filtering Algorithms:
Trends, Challenges and Future

Mohd. Tasleem Khan

###### Abstract

The utilization of distributed arithmetic (DA) in AF algorithms has gained
significant attention in recent years due to its potential to enhance
computational efficiency and reduce resource requirements. This paper presents
an exploration of the application of DA to adaptive filtering (AF) algorithms,
analyzing trends, discussing challenges, and outlining future prospects. It
begins by providing an overview of both DA and AF algorithms, highlighting
their individual merits and established applications. Subsequently, the
integration of DA into AF algorithms is explored, showcasing its ability to
optimize multiply-accumulate operations and mitigate the computational burden
associated with AF algorithms. Throughout the paper, the critical trends
observed in the field are discussed, including advancements in DA-based
hardware architectures. Moreover, the challenges encountered in implementing
DA-based AF is also discussed. The continued evolution of DA techniques to
cater to the demands of modern AF applications, including real-time
processing, resource-constrained environments, and high-dimensional data
streams is anticipated. In conclusion, this paper consolidates the current
state of applying DA to AF algorithms, offering insights into prevailing
trends, discussing challenges, and presenting future research and development
in the field. The fusion of these two domains holds promise for achieving
improved computational efficiency, reduced hardware complexity, and enhanced
performance in various signal processing applications.

###### Index Terms:

Distributed Arithmetic, Adaptive Filtering Algorithms, Circuit Optimization,
Look-up Table.

##  I Introduction

In the realm of modern signal processing, the extraction of pertinent
information from noisy or distorted signals is a ubiquitous challenge.
Adaptive filtering (AF) algorithms become essential for addressing this
challenge in terms of improvisation across a spectrum of applications [1, 2],
including wireless communications [3], image and audio processing [4],
biomedical signal analysis [5], and more, as shown in Fig. 1. These algorithms
dynamically adjust their parameters to accommodate changing signal
characteristics, thereby enabling the extraction of valuable information from
complex and time-varying data. However, the computational intensity of AF
poses a substantial bottleneck in achieving real-time processing, especially
in resource-constrained scenarios.

Depending upon the requirements, AF algorithms are broadly classified as
least-mean squares (LMS) [6, 7], affine projection algorithm (APA) [8] and
recursive-least squares (RLS) [9]. LMS is an AF algorithm that minimizes mean
square error, suitable for slowly varying systems or unknown input signal
statistics; it’s effective but compromised by rapid changes or noise. It has a
low computational cost and good real-time capability due to its simplicity
[10]. APA enhances LMS with multiple regressors for faster convergence and
better tracking; it’s more complex but applicable in many real-time cases. RLS
excels in convergence and tracking, handling changing systems, but demands
more resources due to matrix operations, potentially challenging real-time
processing in low-resource settings. The choice depends on application needs
and the resources available. A typical diagram to illustrate the error
performance, computational cost, and real-time capabilities of these
algorithms is shown in Fig. 2. The LMS algorithm offers computational
simplicity, better real-time capabilities and provides satisfactory error
performance as compared to other two algorithms. Due to these reasons, it is
often optimized for hardware implementation on application-specific integrated
circuits (ASICs) and field-programmable gate arrays (FPGAs) [11, 12].

Figure 1: An overview of applications of AF algorithms.

Approximate computing (AC) in the context of AF introduces a trade-off between
real-time capability and error performance [13]. By allowing controlled
deviations from precise computations, AC techniques aim to reduce the
computational cost of AF algorithms. For example, applying AC to the RLS
algorithm can yield error performance similar to the APA by reducing the
computational load [14]. Similarly, applying AC to APA can result in error
performance similar to the LMS algorithm, again by lessening the computational
demands [15]. These transformations enabled by AC play a pivotal role in
catering to specific application needs. These approximations can lead to
faster processing and improved real-time responsiveness, crucial for
applications with stringent timing requirements. However, this advantage comes
at the cost of introducing errors in the filtering process, which can impact
the overall accuracy of the output signal [16]. Striking the right balance
between achieving real-time responsiveness and maintaining an acceptable level
of error performance is a central challenge for real-world applications.

Distributed arithmetic (DA) stands out as a remarkable approach for AF that
offers a distinct advantage over AC. Unlike AC, it provides a means to achieve
significant computational efficiency while maintaining error performance at
par with exact calculations. This technique capitalizes on pre-computed values
and binary representations, resulting in accelerated computations without any
compromise on the accuracy of the filtering process. By harnessing DA, the AF
algorithms can efficiently process data in real-time scenarios without
sacrificing the precision demanded by critical applications, positioning it as
an essential tool for achieving both high-performance and high-fidelity
outcomes. It was first introduced by Croisier in [17] and later improved by A.
Peled and B. Liu in [18]. Initially, it was applied to second-order infinite
impulse response (IIR) filters [19]. The capabilities of this technique were
extended to realizing higher-order IIR filters through strategic combinations.
It revolutionized DSP by proposing a novel approach for efficient
multiplication using pre-computed partial products stored in a lookup table
(LUT) [20, 21, 22, 23, 24, 25]. While initially devised for efficient
multiplication in DSP applications, the intersection of DA with AF algorithms
has opened up new vistas for optimizing computation and overcoming the
limitations of conventional filtering methods. The essence of DA lies in its
capacity to exploit the parallelism and eliminate the redundant operations,
leading to streamlined multiply-accumulate (MAC) operations that are intrinsic
to AF. By capitalizing on the inherent parallelism of DA, it is possible to
reduce the computational complexity of AF, thereby accelerating the processing
time and enabling real-time implementations [26, 27]. Some latest developments
in the field of neural networks using DA have been reported in [28, 29, 30].

Figure 2: Comparison of error performance, computational cost, and real-time
efficiency across LMS, APA, RLS with different implementation approaches such
as multipliers-based, DA and AC, where $E_{0}<E_{1}<E_{2}$.

The motivation behind writing this article on DA-based AF algorithms stems
from the growing significance and potential in the field of signal processing.
As this technique gains momentum, it is imperative to provide a consolidated
resource that explores its advantages, and limitations. By focusing on trends,
the article aims to shed light on the latest advancements and emerging
practices in the field, guiding researchers and practitioners toward novel
solutions. Addressing the challenges associated with DA-based AF algorithms
will foster a deeper understanding of their practical feasibility and
potential limitations. Overall, this article seeks to serve as a pivotal
resource that not only captures the current state of the field but also paves
the way for its future growth and innovation. In the subsequent section, the
discussion of DA-based LMS algorithms are presented, laying the groundwork for
a deeper understanding of their fusion.

##  II Literature review of DA-based architecture for LMS and its variants

Due to the complexity limitations of APA and RLS algorithms, DA is
predominantly applied to a standard LMS and its high-speed variants. In the
future, there is potential to combine DA with AC techniques, enabling the
approximate implementation of APA and RLS AFs. This convergence could yield
comparable error performance, computational efficiency, and real-time
capabilities to that of LMS AFs. Usually, AFs represent robust self-designing
systems utilized across a diverse range of DSP applications including active
power filters [31], bearing prognosis [32], active noise control [33, 34], and
5G communication systems [35, 36, 37, 38]. Among different AF algorithms,
finite impulse response (FIR) based structures stand out due to their inherent
stability characteristic. It comprises an adjustable coefficient FIR filter
alongside a component responsible for updating these coefficients through
adaptive algorithms.

DA presents a computationally efficient technique for bit-serial inner product
computations (IPCs) in AFs [39, 40, 41, 42, 43, 44, 45, 46, 47] and matrix-
vector multiplications in neural networks [28, 29, 30]. It proves valuable in
implementing digital filtering and machine learning processes without
necessitating hardware multipliers. By pre-computing and storing combinations
of filter coefficients within memory elements, typically look-up tables
(LUTs), the method allows for their retrieval using address formation based on
input sample bits or coefficients, from the least-significant bit (LSB) to the
most-significant bit (MSB). The LUT outputs are then subjected to shifting and
accumulation to compute the final digital filter output. Nonetheless, the DA
method faces a major drawback in the form of exponential growth in the number
of partial products stored within LUTs, particularly for large filter orders.
Complications also emerge when employing the DA approach to implement AFs. The
dynamic nature of AFs, which demands the updating of filter coefficients at
every iteration, renders pre-computing filter coefficients unfeasible. This
challenge significantly diminishes the benefits of the DA method. In the
following, the existing DA-based architectures for implementing LMS AF and its
high-speed variants are discussed.

###  II-A DA-based LMS AFs

The work presented in [40] for DA-based LMS AF has captured the interest of
researchers, driving them to explore architectural innovations aimed at
achieving optimized area, power, and throughput designs for LMS AFs [48]. They
introduced an effective update technique employing two distinct LUTs: a
filtering LUT and an auxiliary LUT. The update process for the auxiliary LUT
entails re-purposing the upper half of the previous LUT’s contents and adding
the most recent sample to calculate the remaining half. Meanwhile, the
filtering LUT is updated by scaling and integrating the contents of the
auxiliary LUT into corresponding addresses, in line with the LMS coefficient
update protocol. It is noteworthy that this update approach does not impose
any assumptions on the statistical characteristics of the input signal. An
improved version of [40] has been presented in [49]. Subsequently, a novel
conjugate DA structure was proposed for AFs [50]. In contrast to the
conventional or direct DA structure, the conjugate DA employs AF coefficients
to formulate addresses for the filtering LUT. This technique alleviates the
necessity for an auxiliary LUT, effectively halving the required memory and
enhancing throughput. Later on, two separate designs for two’s complement (TC)
and offset-binary coding (OBC) schemes, utilizing the conjugate DA approach,
were independently introduced [41]. For TC DA based AFs, the LUT update method
follows the procedure described in [40]. In the case of OBC DA based AFs, a
distinct update mechanism is adopted. This involves subtracting a term
computed using the most recent and the oldest samples from the LUT content at
even addresses and adding it to the content at odd addresses to compute the
succeeding iteration’s second and first halves of the LUT content,
respectively. The conjugate DA structure was also extended to implement
sliding block (SB) AFs [51] and its modified version of SB-DA AFs [52]. In SB-
DA AFs, the processing of input samples by the filter evolves slowly, with
only one sample changing per iteration. Through the utilization of the LUT
decomposition method established in [53, 54], only one of the smaller LUTs,
containing the oldest sample, requires modification, while an additional LUT
is designated to accommodate the newest sample. To execute such an operation
while reusing the LUT contents, circular shifting of the coefficients becomes
essential. This concept of LUT reusability is extensively employed in the
implementation of block-processing DA-AFs. In [42], the framework from [40]
was adopted while leveraging the OBC scheme. A novel update for the auxiliary
LUT was introduced, enabling its division into two smaller LUTs based on even
and odd address locations. An improved version of [42] has been presented in
[55]. This approach facilitated the development of a low-area and high-
throughput design for LMS AF. Further reduction in area has been achieved
without splitting the LUTs into even and odd components, as demonstrated in
[56]. In order to improve the throughput, two high-throughput designs based on
TC and OBC schemes have been recently presented in [57], utilizing the
frameworks of [41, 42].

In the following, two high-speed variants of LMS algorithm, namely, Delayed
LMS (DLMS) [58] and Block LMS (BLMS) [59] will be discussed. In DLMS, delay
registers are introduced in the adaptation loop, while in BLMS, block inputs
are processed in parallel. In the case of the BLMS algorithm, the frequency
domain variant is popular as it allows computational savings in hardware. Few
fast Fourier Transform (FFT) [60, 61, 62, 63, 64] based BLMS AFs are reported
in [65, 66]. Since both variants of LMS are capable of providing higher speeds
than standalone versions, it was intriguing to explore their DA-based
implementations.

TABLE I: Different DA-based architecture for LMS and its variants

Algo. | Design | Type |  No. of LUTs, LUT-Type
---|---|---|---
LMS | Allred et al. [40] | TC | Two, SRAM
Guo et al. [41] | TC | One, SRAM
Guo et al. [41] | OBC | One, ($\times\frac{1}{2}$) SRAM
Surya et al. [42] | OBC | Four ($\times\frac{1}{4}$) SRAM
Khan et al. [57] | TC | Two, ($\times\frac{1}{2}$) SRAM
Khan et al. [57] | OBC | Two ($\times\frac{1}{4}$) SRAM
DLMS | Meher et al. [44] | TC | One, Hardware
Park et al. [43] | TC | One, Hardware∗
Khan et al. [45] | OBC | One, Hardware∗∗
Khan et al. [47] | TC | One, Hardware∗∗∗
BLMS | Basanty et al. [67] | TC |  $L$, SRAM (Shared)
Basanty et al. [68] | TC |  $L$, Hardware (Shared)
Khan et al. [69] | OBC† |  $L$, SRAM (Shared)
Khan et al. [35] | OBC |  $L$, SRAM (Shared)
Khan et al. [70] | TC |  $L$, Hardware (Shared, Partial)
Khan et al. [71] | OBC |  $L$, Hardware (Shared, Partial)

  * •

${}^{{\dagger}}:$ Recursive OBC, $\times\frac{1}{2}$: LUT size reduced by half
compared to [40], $\times\frac{1}{4}$: LUT size reduced to one-fourth of [40],
${}^{*}:$ Represents a more hardware-optimized version of [44]. ${}^{**}:$
Represents a more hardware-optimized version of [43]. ${}^{***}:$ Represents a
more hardware-optimized version of [45]. Shared: Utilized for both the
computation of filter output and coefficient increment term. Partial: Stores
partial LUT contents.

###  II-B DA-based DLMS AFs

To improve the processing speed of DA-AF designs, pipelining delays have been
employed in the error feedback path for coefficient adaptation [72, 73, 44,
43, 45, 74, 47, 75]. It serves to reduce critical-path constraints through re-
timing of delays, and thereby improves the throughput of the system. The first
DA-based DLMS AF design was presented in [44], based on the TC DA.
Subsequently, a pipelined AF using TC conjugate DA structure was introduced in
[43]. It is more hardware optimized version of [44] due to the use of hardware
LUTs, resulting the savings in area and power. More importantly, this also
eliminates the LUT access time issues, and allows the possibility of sharing
partial products. In DA-based designs, pipelining introduces delay elements
that separate various processing stages, and accompanying register-based LUTs
to eliminate access time issues. Moreover, pipelined registers are introduced
between filtering and weight update processes [44, 43]. Register-based LUTs
perform parallel and online computation of DA combinations, albeit at the
expense of an exponential increase in the required number of registers.
Addressing this issue, proposals for multiplexed LUT and AND cell LUT
configurations were put forth in [74]. Enhanced performance was achieved
through an improved DA-AF design in [47], where an AND cell LUT served as the
base unit LUT, and delay elements were integrated into the adder tree. Due to
its advantages, it has been extended to a convex combination of two LMS for
convergence enhancement in [75, 76]. This approach replaces two combined AFs
with a single DA-AF unit featuring two multiplexed step sizes [46].

###  II-C DA-based BLMS AFs

The realm of block processing designs has been extensively explored in studies
such as [77, 67, 68, 69, 35, 70, 71]. In these designs, with a given block
length denoted as $L$, block digital filters manage $L$ input vectors and
compute an equivalent number of outputs in a single iteration. Consequently,
opting for a larger value of $L$ yields a proportional increase in hardware
costs, ultimately leading to a correspondingly elevated throughput. Within
block AFs, the DA methodology has been harnessed, as exemplified in [77],
where it finds application in efficiently implementing the FFT as part of the
Fast Block LMS method. Notably, the inaugural formulation of Block LMS (BLMS)
through a DA framework, built upon the conjugate TC DA-based structure, was
accomplished in [67]. Here, a comparable approach to that of Sliding Block DA
(SB-DA) was adopted for the updating of LUT contents. A conglomerate of LUTs,
designated as a processing element, where the oldest samples reside, undergoes
overwriting through combinations of the most recent samples during each
iteration. It is termed ”inter-iteration LUT reuse,” the technique involves
the recycling of LUT contents between successive iterations, specifically
within a processing element. The remaining processing elements, housing
intermediate samples, remain unaffected. The implementation of this approach
relies on a register array-based LUT, which facilitates the sharing of LUT
contents during a single iteration. This practice, known as ”intra-iteration
LUT sharing,” has been optimized in [68]. This optimization benefits from the
fact that successive LUTs within a processing element share three overlapping
samples, allowing half of the previous LUT’s contents to be shared with the
subsequent LUT. As a result, this strategy diminishes memory complexity. A
corresponding OBC DA-based implementation was introduced in [69], refining the
initial design proposed in [68] by incorporating an even-odd LUT decomposition
utilizing the OBC DA scheme [35]. Subsequent advancements embraced intra-
iteration adaptations for the TC DA in [70], further refined in [71] based on
OBC DA scheme.

##  III Formulation of LMS AF using DA

At the top-level, LMS AF for a system identification problem is shown in Fig.
3. In this section, the LMS AF is formulated using TC or OBC DA. The analysis
can be extended similarly for DLMS and BLMS algorithms. In this context, the
output $y_{n}$ of an $N^{\textnormal{th}}$ order LMS AF using an IPC at time
instant $n$ can be defined as

$y_{n}={\boldsymbol{w}}^{T}_{n}{\boldsymbol{x}}_{n}=\sum\limits_{i=0}^{N-1}w_{n}(i)x_{n-i}$
(1)

Here, ${\boldsymbol{x}}_{n}=[x_{n},x_{n-1},...,x_{n-N+1}]^{T}$ signifies the
input vector, while
${\boldsymbol{w}}_{n}=[w_{n}(0),w_{n}(1),...,w_{n}({N-1})]^{T}$ represents the
coefficient vector. Subsequently, an error term $e_{n}$ is calculated by
subtracting the obtained output $y_{n}$ from the desired signal $d_{n}$,
leading to the equation:

$e_{n}=d_{n}+z_{n}-y_{n}$ (2)

In this scenario, $z_{n}$ represents the additive white Gaussian noise
observed at the output of an unknown system, as illustrated in Fig. 3. The aim
is to adjust the coefficients during each iteration according to the computed
error outlined in (2), according to

${\boldsymbol{w}}_{n+1}={\boldsymbol{w}}_{n}+\mu e_{n}{\boldsymbol{x}}_{n}$
(3)

This article explores the possibilities of DA-based realization of LMS AF. To
begin with formulation of IPC given in (1) and coefficient update equation
given in (3), it is important understand whether inputs or coefficients are
represented in TC/OBC form. For instance, the work reported in [40] has
represented inputs in TC form, while the work presented in [41] has
represented the coefficients in TC/OBC form, and so on. For clarity, the
coefficients are represented in TC/OBC form in this work, however one can also
consider the inputs to be in TC/OBC form.

Figure 3: Block diagram of LMS AF with a system identification problem.

###  III-A IPC using TC DA

This subsection delves into the methodology of IPC using TC DA. The foundation
of this design is the representation of filter coefficients, denoted as
$w_{n}(i)$, in a signed TC $B$-bit format as

$w_{n}({i})=-w_{n}({i,0})+\sum\limits_{j=1}^{B-1}w_{n}({i,j})2^{-j}$ (4)

where $i\in[0,N-1]$. Substituting (4) into (1), and after some simplification,
yields:

$y_{n}=\sum\limits_{j=0}^{B-1}a_{n}({j})2^{-j}$ (5)

with

$a_{n}({j})=(-1)^{\lfloor{(B-1-j)}/{(B-1)}\rfloor}b_{n}({j})$ (6)

where $\lfloor\boldsymbol{\cdot}\rfloor$ represents the greatest integer
function, and $j$ is confined within the range $[0,B-1]$. The resulting
pattern shows that the filter partial products $a_{n}(j)$ undergo a shift-
accumulation over $B$ clock cycles, with a sign inversion occurring during the
$0^{\textnormal{th}}$ clock cycle. The term $b_{n}({j})$ is further defined by

$b_{n}({j})=\sum\limits_{i=0}^{N-1}x_{n-i}w_{n}({i,j})$ (7)

In this equation, $w_{n}({i,j})$ represents the bit-slices of the filter
coefficients, with values in the range $[0,1]$. This allows for the
representation of $b_{n}({j})$ through $2^{N}$ binary combinations, which can
be pre-computed and stored in a LUT, as illustrated in Fig. 4(a). Note that
the size of the LUT grows exponentially with $N$, which becomes problematic
for higher values of $N$. This issue could be mitigated by encoding the
coefficients and incorporating bit-symmetries using OBC scheme.

###  III-B IPC using OBC DA

In this methodology, the encoding of filter coefficients takes the form:
$w_{i}=\frac{1}{2}[w_{i}-{\overline{w}}_{i}]$, where ${\overline{w}}_{i}$
represents the TC of $w_{i}$. Building upon (4), it can be expanded further as

$w_{i}=\frac{1}{2}\bigg{[}-(w_{i,0}-{\overline{w}}_{i,0})+\sum\limits_{j=1}^{B-1}(w_{i,j}-{\overline{w}}_{i,j})2^{-j}-2^{-(B-1)}\bigg{]}$
(8)

Here, $\Delta w_{i,j}=(w_{i,j}-{\overline{w}}_{i,j})$ signifies the disparity
between the bit-slices of filter coefficients and their corresponding TCs.
Substituting (8) into (1) and undergoing subsequent simplification yields

$\displaystyle y_{n}$
$\displaystyle=\sum\limits_{j=0}^{B-1}\bigg{(}\frac{1}{2}\sum\limits_{i=0}^{N-1}x_{n-i}c_{i,j}\bigg{)}2^{-j}-\bigg{(}\frac{1}{2}\sum\limits_{i=0}^{N-1}x_{n-i}\bigg{)}2^{-(B-1)}$
(9)

with

$c_{i,j}=(-1)^{\lfloor{(B-1-j)}/{(B-1)}\rfloor}\Delta w_{i,j}$ (10)

The equation (9) is then transformed into a more concise form as represented
as

$y_{n}=\sum\limits_{j=0}^{B-1}d_{j}2^{-j}+d_{initial}2^{-(B-1)}$ (11)

where the term $d_{j}$ and $d_{initial}$, are respectively, expressed as

$d_{j}=\frac{1}{2}\sum\limits_{i=0}^{N-1}x_{n-i}c_{i,j},\qquad
d_{initial}=-\frac{1}{2}\sum\limits_{i=0}^{N-1}x_{n-i}$ (12)

It is noteworthy that the term $d_{j}$ has $2^{N}$ potential binary
combinations derived from input samples, which can be pre-computed and stored
in a LUT akin to the Type I structure. However, the nature of these stored
contents differs from that of the Type I structure, as $c_{i,j}$ values exist
within the range of $[-1,1]$. Based on the value of $c_{N-1,j}$, it is
apparent that the contents present at the first half and second half address
locations of the LUT are TC of each other. Therefore, it is sufficient to
store only $2^{N-1}$ half combinations in the LUT, as illustrated in Fig.
4(b).

Figure 4: LUT contents of an IPC with (a) TC DA and (b) OBC DA for $N=4$.

###  III-C Coefficient Update using TC and OBC DA

By representing the coefficients ${\boldsymbol{w}}_{n}$ in signed $B$-bit TC
form, we have

${\boldsymbol{w}}_{n}={\boldsymbol{W}}_{n}{\boldsymbol{s}}$ (13)

where ${\boldsymbol{s}}=[-2^{0},2^{-1},...,2^{-(B-1)}]$ is the vector of
binary weights and ${\boldsymbol{W}}_{n}=[w_{n}({i,j})]_{N\times B}$ is the
coefficient bit-slice matrix in TC form, where $w_{n}({i,j})\in[0,1]$
$\forall$ $0\leq i\leq N-1$ and $0\leq j\leq B-1$. Substituting (13) into (3),
we have

${\boldsymbol{W}}_{n+1}{\boldsymbol{s}}={\boldsymbol{W}}_{n}{\boldsymbol{s}}+\mu
e_{n}{\boldsymbol{x}}_{n}$ (14)

It is clear from (14) that LMS algorithm using TC DA is same as standard LMS
except that the coefficients are sliced into bits after update process. Unlike
(14), OBC exploits the bit-symmetries for representation of coefficients in
OBC form. By re-writing the coefficients as
${\boldsymbol{w}}_{n}=\frac{1}{2}[{\boldsymbol{w}}_{n}-(-{\boldsymbol{w}}_{n})]=\frac{1}{2}[{\boldsymbol{w}}_{n}-{\overline{\boldsymbol{w}}}_{n}-1]$,
where ${\overline{\boldsymbol{w}}}_{n}$ is the 1’s complement of
${\boldsymbol{w}}_{n}$. Therefore, we can express the coefficients
${\boldsymbol{w}}_{n}$ using (14) in OBC form as

${\boldsymbol{w}}_{n}={\boldsymbol{W}}_{n}{\boldsymbol{s}}=\frac{1}{2}\left[(\tilde{\boldsymbol{W}}_{n}-1){\boldsymbol{s}}\right]$
(15)

where $\tilde{\boldsymbol{W}}_{n}=[\tilde{w}_{n}({i,j})]_{N\times B}$
$\forall$ is the coefficient difference bit-slice matrix in OBC form with
$\tilde{w}_{n}({i,j})\in[-1,1]$. Substituting (15) into (3), and after some
simplification, we have

$\tilde{\boldsymbol{W}}_{n+1}{\boldsymbol{s}}=\tilde{\boldsymbol{W}}_{n}{\boldsymbol{s}}+2\mu
e_{n}{\boldsymbol{x}}_{n}$ (16)

Clearly, the coefficient update equation is affected by the bit-symmetries
i.e., it involves extra scaling of $2\times$ alongwith the step-size.

##  IV Trends, Challenges, and Future Prospects

In this section, the trends, challenges and future prospects of DA-based
implementation for LMS algorithm and variants will be discussed.

###  IV-A Trends

DA is an efficient technique used for the implementation of LMS AFs, involving
IPCs of binary vectors with shift and add operations. This aims to reduce
computation complexity and resource requirements. This could also involve
research into optimized hardware architectures, algorithmic enhancements, and
novel techniques for accelerating DA operations. Due to high computational
efficiency, researchers might explore hybrid approaches that combine DA or AC
with other adaptive filtering techniques to improve overall performance and
flexibility. With the increasing demand for real-time signal processing in
various fields such as communications, audio processing, and image processing,
DA-based AF may have been adapted and optimized for low-latency applications.
Energy-efficient signal processing is a significant consideration in many
applications. Researchers might work on optimizing DA-based adaptive filters
for reduced power consumption, making them suitable for battery-operated
devices and energy-constrained environments. Given the trend toward parallel
and distributed computing architectures, researchers may have explored ways to
parallelize and distribute the computations involved in DA-based AF. This
could lead to improved performance and scalability. Researchers might explore
ways to integrate machine learning techniques with DA-based AF to create
hybrid adaptive systems that can learn from data and adapt more effectively to
changing conditions. In recent works on DA-based implementation, hardware LUT
(or sometimes it is referred to as LUT-less design) removes the bottleneck of
LUT access time on the performance of LMS AFs, as mentioned before. In the
latest development on high-speed implementation of LMS algorithm, a
comprehensive analysis that combines both pipelining and block processing has
been presented in [78]. This work has developed a stochastic model which
established the relation of step-size in terms filter order and delay/block
size (or speedup).

###  IV-B Challenges

DA-based AF, while a powerful technique, also comes with certain challenges
and considerations that need to be addressed. Since DA relies on binary
representations and shift-and-add operations, which can lead to limited
precision and accumulation of errors over time. This can impact the overall
accuracy and performance of the filter, especially in applications requiring
high precision. Although applying DA to AF was seem to be initially difficult
as they are also involve coefficient adaptation. The issue of auxillary LUTs
for DA-based implementation was overcome wth conjungate DA. For real-time
implementation, choosing appropriate adaptation algorithms and strategies that
converge quickly while maintaining stability is essential. Inherently, DA-
based AFs are linear and may struggle when dealing with non-linear or time-
varying systems. Adapting to changes in system behavior while maintaining
filter stability can be difficult. While DA can reduce the number of
multiplications in several AF implementations, it can lead to increased
complexity in terms of shift-and-add operations, especially for higher input
or coefficient precision. This may pose challenges in terms of hardware
implementation, especially for high-speed. Previously, DA requires careful
management of memory resources for storing coefficients and intermediate
results. This has been replaced hardware LUTs which are important for real-
time or embedded systems. The filter length and step-size value play a crucial
role in determining its performance and complexity. Striking a balance between
achieving the desired filtering characteristics and managing computational
demands can be challenging. In addition, step-size can also adaptation rate,
for instance, achieving fast adaptation speed while ensuring stability can be
a delicate balance. Aggressive adaptation can lead to instability, while
overly cautious adaptation might result in slower convergence. While DA has
inherent parallelism especially when realizing the partial products with
hardware LUTs, efficiently parallelizing the computations across multiple
processing units or cores can be challenging, especially for complex filter
structures. It’s important to note that researchers continue to work on
addressing these challenges through algorithmic improvements, hardware
innovations, and hybrid approaches that combine DA with other techniques.

###  IV-C Future

The future research could focus on designing more efficient and specialized
hardware architectures optimized for DA-based AF. These architectures might
leverage emerging technologies such as FPGAs, ASICs, or even neuromorphic
computing for improved performance and energy efficiency. Furthermore,
combining DA-based AF with other advanced filtering techniques, such as
machine learning and neural networks, could lead to hybrid adaptive systems
that exploit the strengths of each approach. This might involve using machine
learning to initialize or fine-tune DA filters, enabling more adaptable and
robust filtering in complex scenarios. Researchers may also work on extending
the capabilities of DA-based filters to handle non-linear and time-varying
systems more effectively. Developing adaptive strategies that can dynamically
adjust filter parameters to accommodate changing system behaviors could open
up new applications. As the demand for real-time processing continues to grow
in applications like 6G communications, autonomous systems, and sensor
networks, the future scope of DA-based AF could involve optimizing the
technique for low-latency and high-throughput processing. Specifically, high-
speed LMS recently developed in [78] can be deployed in 6G communication
system due to both pipelining and block processing. With the proliferation of
edge computing and IoT devices, there could be increased interest in
developing lightweight and energy-efficient DA-based AF that can operate on
resource-constrained platforms. As technology unfolds, new fields may emerge
that can benefit from DA-based AF. For example, applications in quantum
computing, bio-informatics, or novel communication systems might present
opportunities for the application of this technique.

##  V Conclusion

In summary, the utilization of DA-based AF algorithms has garnered
considerable attention in recent years, owing to its potential to bolster
computational efficiency and diminish resource requirements. This paper has
delved into the application of DA in AF algorithms, scrutinizing trends,
addressing challenges, and delineating future prospects. It commenced by
furnishing an overview of both DA and AF algorithms, elucidating their
respective merits and established applications. The subsequent exploration
focused on integrating DA into AF algorithms, demonstrating its efficacy in
optimizing multiply-accumulate operations and alleviating the computational
burden associated with AF algorithms. Although the majority of designs center
on the implementation of LMS AFs due to their simplicity and commendable
performance, there exists a dearth of DA-based AF designs addressing more
advanced adaptive algorithms such as APA and RLS. Notably, a recurring trend
has surfaced, wherein various design types ultimately gravitate towards
conjugate OBC/TC DA based implementation with hardware LUTs. Such designs
obviate the need for auxiliary LUTs and further reduce memory access issue. In
a broader context, it is discernible that initial structures predominantly
embrace direct TC DA based paradigms, subsequently undergoing refinement via
the integration of conjugate DA or OBC DA-based methodologies. An additional
promising direction for future research revolves around the strategic pursuit
of novel adaptive algorithms such as presented in [78] amenable to the DA
implementation framework. To summarize, this paper consolidates the current
state of applying DA to AF algorithms, providing insights into prevailing
trends, addressing challenges, and outlining future research and development
in the field. The fusion of these two domains holds promise for achieving
improved computational efficiency, reduced hardware complexity, and enhanced
performance across various signal processing applications.

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