#  A note on the Erdős distinct subset sums problem

Quentin Dubroff  Department of Mathematics, Rutgers University, Piscataway,
NJ, USA<EMAIL_ADDRESS>,  Jacob Fox  Department of Mathematics,
Stanford University, Stanford, CA, USA<EMAIL_ADDRESS>and  Max
Wenqiang Xu  Department of Mathematics, Stanford University, Stanford, CA, USA
<EMAIL_ADDRESS>
###### Abstract.

We present two short proofs giving the best known asymptotic lower bound for
the maximum element in a set of $n$ positive integers with distinct subset
sums.

Fox is supported by a Packard Fellowship and by NSF award DMS-1855635. Xu is
supported by the Cuthbert C. Hurd Graduate Fellowship in the Mathematical
Sciences, Stanford

Let $\\{a_{1},\ldots,a_{n}\\}$ be a set of positive integers with
$a_{1}<\ldots<a_{n}$ and all subset sums distinct. Erdős conjectured that
$a_{n}\geq c\cdot 2^{n}$ for some constant $c>0$ and offered $\$500$ for a
proof or disproof. See [8] for more history on this. Using the second moment
method, Erdős and Moser [6] (see also [2]) proved

$a_{n}\geq\frac{1}{4}\cdot n^{-1/2}\cdot 2^{n}.$

There have been some improvements on the constant factor of the above lower
bound, including the work of Guy [7], Elkies [5], Bae [3], and Aliev [1]. In
particular, the previous best published lower bound was due to Aliev, which
gave the constant factor $\sqrt{3/2\pi}$. In the other direction, the best
known construction is due to Bohman [4], where he constructed such sets with
$a_{n}\leq 0.22002\cdot 2^{n}$.

In this note, we give two proofs of the best known lower bound, matching an
unpublished result of Elkies and Gleason (see [1]).

######  Theorem 1.

If a set $\\{a_{1},\ldots,a_{n}\\}$ of integers with $0<a_{1}<\ldots<a_{n}$
has all subset sums distinct, then

$a_{n}\geq\left(\sqrt{\frac{2}{\pi}}-o(1)\right)\cdot n^{-1/2}\cdot 2^{n}.$

The second proof uses an isoperimetric inequality to show that
$a_{n}\geq\binom{n}{\lfloor n/2\rfloor}$ for all $n$, which asymptotically
matches the lower bound above. The first proof uses the following result from
probability.

######  Theorem 2 (Berry-Esseen).

Let $X_{1},\ldots,X_{n}$ be independent random variables with
$\mathbb{E}[X_{i}]=0$, $\mathbb{E}[X_{i}^{2}]=\sigma_{i}^{2}$, and
$\mathbb{E}[|X_{i}|^{3}]=\rho_{i}<\infty$. Let $X=X_{1}+\cdots+X_{n}$ and
$\sigma^{2}=\mathbb{E}[X^{2}]$. Then

$\sup_{x\in\mathbb{R}}|F(x)-\Psi(x)|\leq C\cdot\psi,$

where $F(x)$ and $\Psi(x)$ are the cumulative distribution functions for $X$
and the normal distribution with mean zero and standard deviation $\sigma$,
respectively, $C$ is an absolute constant, and
$\psi=\sigma^{-3}\cdot\sum_{i=1}^{n}\rho_{i}$.

It is known [10] that one can take $C=0.56$ in the Berry-Esseen theorem.

Using the Berry-Esseen theorem and an inequality of Moser, our proof verifies
Erdős’ conjecture that $a_{n}=\Omega(2^{n})$ if the distribution of a random
subset sum is not close to normal. If the distribution is close to normal, we
replace Chebyshev’s inequality in the second moment argument by the normal
distribution in bounding the probability that a random subset sum is in an
interval.

###### Proof of Theorem 1.

Let $\epsilon_{1},\ldots,\epsilon_{n}\in\\{-1,1\\}$ be independently and
uniformly distributed and let $X=\epsilon_{1}a_{1}+\ldots+\epsilon_{n}a_{n}$.
The random variable $X$ has mean $0$ and is symmetric around $0$. Moreover,
each of its possible values occurs with probability $2^{-n}$ by the distinct
subset sums property, and each of its possible values are of the same parity.
Note that the variance of $X$ is $\sigma^{2}=\sum_{i=1}^{n}a_{i}^{2}$.

Let $\delta=\delta_{n}$ tend to $0$ slowly as $n$ tends to infinity, with
$\delta>n^{-1/2}$, e.g., $\delta=1/\log n$ works. We first notice that if
$\sigma\leq a_{n}/\delta$, then Moser’s lower bound on the variance [7]:

$\sigma^{2}=\sum_{1\leq i\leq n}a_{i}^{2}\geq 1^{2}+2^{2}+4^{2}+\cdots
2^{2(n-1)}=\frac{4^{n}-1}{3}$

gives the desired lower bound $a_{n}\geq\delta\cdot 2^{n-1}>n^{-1/2}\cdot
2^{n}$.

It remains to consider the case $\sigma>a_{n}/\delta$. We next apply Theorem
2. Note that $X=\sum_{i=1}^{n}X_{i}$, where $X_{i}=\epsilon_{i}a_{i}$. We have
$\rho_{i}=a_{i}^{3}$ and $\sum_{i=1}^{n}\rho_{i}\leq
a_{n}\cdot\sum_{i=1}^{n}a_{i}^{2}=a_{n}\sigma^{2}$, which implies $\psi\leq
a_{n}/\sigma<\delta$ by the definition of $\psi$ and the bound on $\sigma$. By
Theorem 2, we have $\sup_{x\in\mathbb{R}}|F(x)-\Psi(x)|\leq\delta$, that is,
$X$ is $\delta$-close to normal. We bound $\textrm{Pr}[|X|\leq\ell]$ in two
different ways to get a lower bound for $\sigma$.

Since the $2^{n}$ possible outcomes for $X$ have the same parity and are
distinct, we obtain

(1) $\textrm{Pr}[|X|\leq\ell]\leq(\ell+1)\cdot 2^{-n}.$

On the other hand, let $\ell=\alpha\sigma$ with $\alpha=\alpha_{n}$ tending to
$0$ as $n$ tends to infinity with $\delta=o(\alpha)$, e.g.,
$\alpha=\sqrt{\delta}$ works. As $X$ is $\delta$-close to a normal
distribution, we obtain that

(2)
$\textrm{Pr}[|X|\leq\ell]=\frac{1}{\sigma\sqrt{2\pi}}\int_{-\ell}^{\ell}\exp\big{(}-\frac{x^{2}}{2\sigma^{2}}\big{)}dx+O(\delta)\sim\sqrt{\frac{2}{\pi}}\,\frac{\ell}{\sigma}.$

Comparing (1) and (2), we obtain that
$\sigma\geq\left(\sqrt{2/\pi}-o(1)\right)\cdot 2^{n}$. Comparing this with the
upper bound $\sigma^{2}=a_{1}^{2}+\cdots+a_{n}^{2}\leq na_{n}^{2}$, we have
$a_{n}\geq\left(\sqrt{2/\pi}-o(1)\right)\cdot n^{-1/2}\cdot 2^{n}$ as desired.
$\Box$

The second proof will use the following special case of Harper’s vertex-
isoperimetric inequality. We write $2^{[n]}$ for the set of subsets of
$\\{1,2,\ldots,n\\}$, and for $\mathcal{F}\subseteq 2^{[n]}$ we define the
vertex boundary $\partial\mathcal{F}=\\{A\in\mathcal{F}^{c}:|A\triangle
B|=1\text{ for some }B\in\mathcal{F}\\}$.

######  Theorem 3 (Harper).

If $\mathcal{F}\subset 2^{[n]}$ such that $|\mathcal{F}|=2^{n-1}$, then
$|\partial\mathcal{F}|\geq\binom{n}{\lfloor n/2\rfloor}$.

See [9] for a full statement of Harper’s theorem as well as [11] and [12] for
a particularly nice proof.

###### A second proof of Theorem 1.

Set $a=(a_{1},\ldots,a_{n})$ and note that $a\cdot\epsilon\neq 0$ for all
$\epsilon\in\\{-\frac{1}{2},\frac{1}{2}\\}^{n}$. Let $\mathcal{F}$ be the
$2^{n-1}$ points $\epsilon$ in $\\{-\frac{1}{2},\frac{1}{2}\\}^{n}$ such that
$a\cdot\epsilon<0$. Identifying $\\{-\frac{1}{2},\frac{1}{2}\\}^{n}$ with
$2^{[n]}$ in the natural way, we have $\eta\in\partial\mathcal{F}$ if $\eta\pm
e_{i}\in\mathcal{F}$ for some standard basis vector $e_{i}$. Theorem 3 then
gives $|\partial\mathcal{F}|\geq\binom{n}{\lfloor n/2\rfloor}$, where each
$\eta\in\partial\mathcal{F}$ must satisfy $0<a\cdot\eta<a_{n}$. Therefore
there are distinct $\epsilon,\eta$ $\in\partial\mathcal{F}$ such that
$|a\cdot(\epsilon-\eta)|\leq a_{n}/\binom{n}{\lfloor n/2\rfloor}$. However,
$\epsilon-\eta\in\\{-1,0,1\\}^{n}$, so $|a\cdot(\epsilon-\eta)|=|\sum_{i\in
I}a_{i}-\sum_{j\in J}a_{j}|$ for some $I,J\subseteq[n]$, and we get
$|a\cdot(\epsilon-\eta)|\geq 1$ by the distinct subset sum property. Comparing
the lower and upper bound on $|a\cdot(\epsilon-\eta)|$ gives
$a_{n}\geq\binom{n}{\lfloor n/2\rfloor}=\left(\sqrt{2/\pi}-o(1)\right)\cdot
n^{-1/2}\cdot 2^{n}$. $\Box$

Acknowledgements. We would like to thank Noga Alon, Matthew Kwan, Bhargav
Narayanan, Joel Spencer and Yufei Zhao for helpful comments.

## References

  * [1] I. Aliev, Siegel’s lemma and sum-distinct sets, Discrete Comput. Geom. 39 (2008), 59–66.
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  * [4] T. Bohman, A construction for sets of integers with distinct subset sums, Electron. J. Combin. 5 (1998), Research Paper 3, 14 pages.
  * [5] N. D. Elkies, An improved lower bound on the greatest element of a sum-distinct set of fixed order, J. Combin. Theory Ser. A 41 (1986), 89–94.
  * [6] P. Erdős, Problems and results in additive number theory, Colloque sur la Théorie des Nombres, Bruxelles, 1955, pp. 127–137, George Thone, Liège; Masson and Cie, Paris, 1956.
  * [7] R. K. Guy, Sets of integers whose subsets have distinct sums, Theory and practice of combinatorics, 141–154, North-Holland Math. Stud., 60, Ann. Discrete Math., 12, North-Holland, Amsterdam, (1982).
  * [8] R. K. Guy, Unsolved Problems in Intuitive Mathematics, Vol. I, Number Theory, Problem C8, Springer-Verlag (1981).
  * [9] L. H. Harper, Optimal numberings and isoperimetric problems on graphs, J. Combin. Theory 1 (1966), 385-393.
  * [10] I. G. Shevtsova, An improvement of convergence rate estimates in the Lyapunov theorem, Dokl. Math. 82 (2010), 862–864.
  * [11] D. J. Kleitman, Extremal hypergraph problems. Surveys in combinatorics, Proc. Seventh British Combinatorial Conf., Cambridge, (1979), pp. 44–65, London Math. Soc. Lecture Note Ser., 38, Cambridge Univ. Press, Cambridge-New York, (1979).
  * [12] I. Leader, Discrete isoperimetric inequalities. Probabilistic combinatorics and its applications (San Francisco, CA, 1991), 57–80, Proc. Sympos. Appl. Math., 44, AMS Short Course Lecture Notes, Amer. Math. Soc., Providence, RI, 1991.


# Single-electron occupation in quantum dot arrays at selectable plunger gate
voltage

Marcel Meyer  Corentin Déprez  Ilja N. Meijer  Florian K. Unseld  QuTech and
Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046,
2600 GA Delft, The Netherlands  Saurabh Karwal  Amir Sammak  QuTech and
Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155,
2600 AD Delft, The Netherlands  Giordano Scappucci  Lieven M. K. Vandersypen
Menno Veldhorst  corresponding author<EMAIL_ADDRESS>QuTech and Kavli
Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA
Delft, The Netherlands

(August 28, 2024)

###### Abstract

The small footprint of semiconductor qubits is favorable for scalable quantum
computing. However, their size also makes them sensitive to their local
environment and variations in gate structure. Currently, each device requires
tailored gate voltages to confine a single charge per quantum dot, clearly
challenging scalability. Here, we tune these gate voltages and equalize them
solely through the temporary application of stress voltages. In a double
quantum dot, we reach a stable (1,1) charge state at identical and
predetermined plunger gate voltage and for various interdot couplings.
Applying our findings, we tune a 2$\times$2 quadruple quantum dot such that
the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V.
The ability to define required gate voltages may relax requirements on control
electronics and operations for spin qubit devices, providing means to advance
quantum hardware.

Quantum Dot, Single-electron Occupation, Uniformity, Stress Voltage, Spin
Qubit

## Introduction

Semiconductor spin qubits have become a compelling platform for quantum
computation. Single qubit gate fidelities of 99.99% [1] and two-qubit gate
fidelities exceeding 99% [2, 3, 4, 5] have been demonstrated. A moderate
sensitivity to thermal effects allowed for the implementation of quantum
operations above one Kelvin [6, 7, 8]. Furthermore, the small size of
semiconductor spin qubits and their compatibility with advanced semiconductor
manufacturing [9, 10, 11] may facilitate devices with large numbers of qubits
as required for practical applications. Recent advances in the material
platforms supported the realization of a $2\times 2$ qubit array in germanium
[12], a linear six qubit system in silicon [13], and the operation of a 16
quantum dot crossbar array [14]. However, scaling up the number of qubits is
challenging, especially when considering the numbers needed for fault-tolerant
quantum computation [15, 16, 17]. A particular challenge lies in the
sensitivity of qubits to their environment leading to considerable variations
of their properties, a notion that was already highlighted in the seminal work
on quantum computation by Loss and DiVincenzo [18].

Substantial reductions in variability have been achieved through progress in
heterostructure growth and device fabrication. For instance, these efforts
focus on reducing material disorder [19, 20, 21, 22, 23, 24, 25, 26],
advancing device fabrication [27, 28, 29] and addressing fluctuations in
mechanical stress induced by the deposition of metallic gate electrodes [30,
31, 32]. However, significant variations remain observable in current devices
[33, 34, 14] and it is an open question whether sufficient uniformity can be
reached through material development alone.

Alternatively, fluctuations in the potential landscape can be compensated by
temporarily applying stress voltages [35, 36, 37, 38]. An alternating sequence
of stress voltages and pinch-off measurements has already enabled on-demand
reshaping of pinch-off voltage characteristics and their homogenization
without signs of reduced device stability afterwards. Furthermore, such
sequences allowed to alter the potential offset of a single electron
transistor (SET) at a temperature of $\approx 4.2\leavevmode\nobreak\ $K [38].
Yet, this methodology has not been applied to individual electrons in a
quantum dot. Also, overcoming qubit variations in quantum processors will
require the tuning of multiple quantum dots.

Here, we demonstrate the use of stress voltages to tune the potential
landscape in a quantum dot array. We show that this approach allows to change
and equalize the plunger gate voltages required to reach single-electron
occupation in a double quantum dot without changing any other gate voltages.
Importantly, we find that the resulting confining potential remains stable for
hours afterwards. To illustrate its robustness and versatility, we demonstrate
that the method employed can be applied at various barrier voltages and thus
interdot tunnel couplings. Furthermore, we show that the procedure can be
extended to homogenize the plunger gate voltages defining the single
occupation charge state in a $2\times 2$ quantum dot system.

## Results

Figure 1: Device and tuning of a double quantum dot. (a) Scanning electron
micrograph of a device nominally identical to the one under study. Confinement
(C$i$) and barrier (B$i$ and B$ij$) gates are designed to define four quantum
dots indicated by the white circles. Their charge occupation is controlled by
four plunger (P$i$) gates. Confinement gates are outlined by dashed lines for
clarity. A sensor quantum dot is formed under S1 and measured in transport.
(b) Charge stability diagram showing the single-electron occupation of the
Q3-Q4 double quantum dot formed underneath P3 and P4. The plotted signal is
locally contrast normalized (LCN) to increase the visibility of the charge
transition lines as described in the methods section. Dashed lines connect
charge triple degeneracy points and thereby indicate transitions of the charge
ground state which cannot be observed directly due to latching effects. The
plunger gate voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ that set a
$(1,1)$ charge state are indicated by vertical and horizontal bars. The ranges
are extracted around the center point of the (1,1) charge region (see
methods). Unprocessed data shown in supplementary section S6. (c) Plunger gate
voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ as extracted in (b).

Fig. 1.a shows a scanning electron micrograph of a device nominally identical
to the one under study in this work, which is fabricated on a 28Si/SiGe
heterostructure [39] (see methods). The gate design allows for the formation
of a $2\times 2$ quantum dot array (white circles) and two adjacent single
electron transistors (SETs) on the left and right side [40]. We form the
quantum dots Q3 and Q4 underneath the plunger gates P3 and P4 and also tune up
the SET below the sensor gate S1. The left side of the device is operated as
an electron reservoir. Fig. 1.b depicts a charge stability diagram recorded
after the initial tuning. It shows the typical honeycomb pattern of a double
quantum dot and depletion down to the $(N_{3},N_{4})=(1,1)$ charge state with
$N_{i}$ the charge occupation of Q$i$.

The charge stability diagram reveals a large asymmetry in the plunger gate
voltages required to reach the single-electron regime. The voltage ranges
$[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ from the first to the second charge
transition line of the two quantum dots are indicated by a horizontal and a
vertical bar (see methods for the definition). As illustrated in Fig. 1.c
those ranges do not overlap for the two quantum dots and in particular we find
a separation of more than 2(4) times the Q3(Q4) charging voltage $V_{{\rm
P}i}^{\rm C}=V_{{\rm P}i}^{+}-V_{{\rm P}i}^{-}$. While this is a rather
extreme case, significant asymmetries of the plunger gate voltage ranges
loading a single electron are commonly observed in quantum dot devices [33,
41, 42, 43, 14]. Therefore, if single-electron occupation can be achieved at
equal plunger gate voltages in the device of Fig. 1 this would provide good
prospects for the homogenization of the required plunger gate voltages in
other devices that already are intrinsically more uniform.

Figure 2: Single-electron occupation at predetermined plunger gate voltages
through voltage stressing. (a) Schematic of the stress-measure sequence
applied to shift the voltages required to obtain the $(1,1)$ charge state.
Increasing stress voltages $V_{\rm stress}$ are applied for $t_{\rm
stress}=1\leavevmode\nobreak\ $min interleaved by charge stability diagram
measurements. (b) Expected trajectory for the center of the (1,1) charge
region $\textbf{{V}}^{(1,1)}$ in the ($V_{\rm P3}$,$V_{\rm P4}$) plane during
the tuning procedure as defined prior to conducting the experiment. The color
of the path refers to the plunger gate being stressed. (c) Actual trajectory
of $\textbf{{V}}^{(1,1)}$ followed during the tuning procedure. The triangle,
circles and diamond mark the starting point, (intermediate) targets and the
endpoint of the path, respectively. Black arrows indicate the time flow. (d)
$V^{(1,1)}_{\rm P3}$ (bottom) and $V^{(1,1)}_{\rm P4}$ (top) as a function of
the applied stress voltage $V_{\rm stress}$. The triangle, circles and diamond
mark the same points as in (c) and black arrows indicate the time flow. (e)
Plunger gate voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ that keep
the double quantum dot in the $(1,1)$ charge state after tuning (see methods).
Targets are indicated by the dotted lines. (f) Corresponding charge stability
diagrams recorded after the application of the respective stress voltage
sequences. The white square markers show the target voltages
$\textbf{{V}}^{\rm T}=(V^{\rm T},V^{\rm T})$. Plunger gate voltage ranges
$[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ that keep the system in the $(1,1)$
charge state are indicated by vertical and horizontal bars. Dashed lines
indicate transitions of the charge ground state which cannot be observed
directly due to latching effects. Unprocessed data shown in supplementary
section S6.

### (1,1) charge occupation at predetermined plunger gate voltage

To increase the potential uniformity, we follow our previous work [38] and
apply stress voltages $V_{\rm stress}$ on gate electrodes to reshape the
background potential landscape. We aim to tune the system such that the (1,1)
charge state is reached at predetermined plunger gate voltage. Specifically we
target to load a single electron per quantum dot for $V_{\rm P3}=V_{\rm
P4}=V^{\rm T}$ with $V^{\rm T}=1\leavevmode\nobreak\ $V, 1.1 V and 1.2 V by
sequentially tuning the potential below the two plunger gates following the
path shown in Fig. 2.b. Fig. 2.a illustrates the employed procedure for a
single plunger gate P$i$. We apply a stress voltage $V_{\rm stress}$ for
$t_{\rm stress}=1\leavevmode\nobreak\ $min. Afterwards, we measure charge
stability diagrams around $V_{{\rm P}i}=V^{\rm T}$ and if necessary the sensor
gate voltage $V_{\rm S1}$ is compensated to restore maximum sensitivity of the
SET. From the charge stability diagrams we then extract the voltage range
$[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ required to reach single charge
occupation. If setting the target voltage does not yield the targeted electron
occupation in Q$i$ ($V^{\rm T}$ not in $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$)
the sequence is repeated with an increased (decreased) stress voltage to shift
the voltage range further upward (downward). If a single electron is loaded at
the target voltage configuration we stop applying stress voltages to P$i$ and
analogously tune the potential of the other quantum dot. After the initial
tune up (Fig. 1), we first follow the stressing procedure to lower the
required plunger gate voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ to
reach single-electron occupancy at 1 V. During this process we adjust the
barrier gate B2 voltage in order to maintain a significant tunnel rate. Then,
we perform the stressing experiment and advance from point A to E in Fig. 2.b.
Here, we only change the sensor gate S1 voltage and keep all other gate
voltages constant (see supplementary section S8 for the voltage settings).

Fig. 2.f shows charge stability diagrams recorded after tuning toward the
predefined targets $V^{\rm T}$. A clear shift of the (1,1) charge region to
higher plunger gate voltages and then back down is observable. Furthermore,
after the completion of each tuning, setting the plunger gate voltages
$(V_{\rm P3},V_{\rm P4})$ to $\textbf{{V}}^{\rm T}=(V^{\rm T},V^{\rm T})$
(white square marker) loads a single electron per quantum dot as also
highlighted in Fig. 2.e showing the extracted voltage ranges $[V_{{\rm
P}i}^{-},V_{{\rm P}i}^{+}]$. This demonstrates tunability of the chemical
potentials and control over the electron occupation in a double quantum dot
through the temporary application of stress voltage. Note that charge latching
is reduced (increased) when tuning the voltage ranges $[V_{{\rm
P}i}^{-},V_{{\rm P}i}^{+}]$ upwards (downwards). This suggests a crosstalk
effect of the applied stress voltages on the surrounding tunnel barrier
potentials.

Fig. 2.c shows the reconstructed evolution of the center point of the (1,1)
charge region $\textbf{{V}}^{\mathrm{(1,1)}}=(V^{(1,1)}_{\rm
P3},V^{(1,1)}_{\rm P4})$ during the tuning procedure (see methods section).
Overall, the experimental trajectory reproduces qualitatively the intended one
shown in Fig. 2.b. The predominantly horizontal and vertical progressions in
the $(V^{(1,1)}_{\rm P3},V^{(1,1)}_{\rm P4})$ plane suggest limited crosstalk,
i.e. applying stress voltages to one gate P$i$ only has a small effect on the
charge transition voltages of the quantum dot below the other plunger gate.
Quantitatively, we find slopes $dV^{(1,1)}_{{\rm P}i}/dV^{(1,1)}_{{\rm P}j}$
between $-0.31\leavevmode\nobreak\ $V/V and $-0.04\leavevmode\nobreak\ $V/V.
The sign of these slopes is consistent with the sign of the capacitive shift
of the transition line voltage of Q$j$ when the plunger gate voltage $V_{{\rm
P}i}$ is changed (see supplementary section S1). Correcting for this effect,
we obtain the change of the charge transition voltages of Q$j$ induced
exclusively by the application of stress voltages set to P$i$. We find
crosstalks of $(+0.37\pm 0.03)\leavevmode\nobreak\ $V/V and $(+0.19\pm
0.03)\leavevmode\nobreak\ $V/V for P3 on Q4 and P4 on Q3 respectively.
Overall, while these crosstalk effects could be compensated for, the simple
approach presented here allowed to tune the potentials of the quantum dots to
the predetermined targets.

In Fig. 2.d the center voltages $V^{(1,1)}_{3}$ and $V^{(1,1)}_{4}$ are
plotted as a function of the applied stress voltage $V_{\rm stress}$. We
recover the typical hysteresis cycle observed when tuning pinch-off voltages
using an analogous method in similar devices [38]. Noticeably, for steadily
decreasing stress voltages there is an initial increase in $V^{(1,1)}_{{\rm
P}i}$ before it rapidly drops to lower voltages at $V_{\rm
stress}\approx-4\leavevmode\nobreak\ $V. In Fig. 2.c this manifests as non-
monotonic progressions of $\textbf{{V}}^{(1,1)}$ between the target points C
and D. $V^{(1,1)}_{\rm P4}$ and $V^{(1,1)}_{\rm P3}$ initially increase by 40
mV and 180 mV, respectively, before they decrease and approach $V^{\rm
T}=1.1\leavevmode\nobreak\ $V.

Summarizing, Fig. 2 demonstrates that the background potential in the quantum
well can be reshaped such that each quantum dot can be occupied with one
electron using uniform plunger gate voltages.

Figure 3: Stability of the (1,1) charge state after stress tuning. (a) Time
traces of the plunger gate voltage ranges that keep the system in the $(1,1)$
charge state (see methods for the definition) after the application of a
sequence of increasing stress voltages. $t$ is the time after the application
of the last stress voltage. Note that the underlying charge stability diagram
measurements were interleaved with charge noise measurements on the sensor
(see supplementary section S3). Additional traces are presented in
supplementary section S2. (b) Overlay of charge stability diagrams taken at
the beginning (star, olive green) and end (hexagon, light green) of the time
trace shown in (a). Horizontal and vertical bars indicate the respective
plunger gate voltage ranges that keep the system in the (1,1) charge state.
Dashed lines indicate transitions of the charge ground state which cannot be
observed directly due to latching effects. Unprocessed data shown in
supplementary section S6.

### Time stability

To understand the impact of stress voltages on device stability, we record
multiple charge stability diagrams as a function of time after the initial
stress tuning towards $V^{\rm T}=1\leavevmode\nobreak\ $V (A in Fig.2.d). Fig.
3.a shows the extracted evolution of the plunger gate voltage range that keeps
the quantum dots Q3 and Q4 in the single-electron occupation. Here, the time
$t$ refers to the time since the last application of a stress voltage and
voltages are plotted relative to $V^{\rm T}$. We find that the double quantum
dot system remains in the $(1,1)$ charge state for more than 15 h showing only
a weak drift. This is confirmed by standard deviations of 3 mV, 3 mV, 2 mV,
and 1 mV for $V_{\rm P3}^{-}$, $V_{\rm P3}^{+}$, $V_{\rm P4}^{-}$, and $V_{\rm
P4}^{+}$, respectively, which remain negligible compared to the charging
voltages of 148 mV and 87 mV for Q3 and Q4, respectively. Overlaying the
charge stability diagrams recorded at $t=0\leavevmode\nobreak\ $h and at
$t=17\leavevmode\nobreak\ $h, as depicted in Fig. 3.b, provides further
confirmation of the device stability. Additional time traces demonstrating
stability up to 40 h after the application of the last stress voltages are
presented in supplementary section S2. Moreover, we find no increase in the
charge noise sensed by the right SET when comparing to typical values for such
devices (see supplementary section S3). Note that the charge noise amplitude
measured by the SET might differ from the charge noise level that would affect
the coherence of qubits in the array. Nevertheless, we conclude that there are
no signs of decreased device stability caused by the application of stress
voltages.

Figure 4: Single-electron occupation at predetermined plunger gate voltage for
high and low interdot coupling. (a)-(e) Charge stability diagrams measured
after tuning the system through applying stress voltages such that the (1,1)
charge state is the ground state when applying the plunger gate voltages
$\textbf{{V}}^{\rm T}=(1\leavevmode\nobreak\ {\rm V},1\leavevmode\nobreak\
{\rm V})$ (white square marker). In each case a different barrier gate voltage
$V_{\rm B34}$ is set before the tuning (labelled in the plot titles). The
range of plunger gate voltages $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ that keep
the system in the $(1,1)$ charge state is indicated by horizontal and vertical
bars (see methods). Dashed lines indicate transitions of the charge ground
state which cannot be observed directly due to latching effects. The
unprocessed data is shown in supplementary section S6. (f) Plunger gate
voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ extracted from (a)-(e).
The dotted line indicates the target voltage $V^{\rm T}=1\leavevmode\nobreak\
$V.

### Predetermined plunger gate voltage for tunnel coupled quantum dots

We now address the question whether single-electron occupation can still be
achieved by a predetermined gate voltage, when changing the coupling between
the quantum dots. In our double quantum dot system, we can control the
interdot coupling by adjusting the barrier gate B34 voltage to tune the system
from strong to weak coupling quantum dots. We achieve this by varying the
barrier gate voltages between $0\leavevmode\nobreak\ $V and
$-0.5\leavevmode\nobreak\ $V. After setting a barrier gate voltage, we apply
stress voltages to the plunger gates to obtain the $(1,1)$ charge state at
$\textbf{{V}}^{\rm T}=(1\leavevmode\nobreak\ {\rm V},1\leavevmode\nobreak\
{\rm V})$. Fig. 4.a-e shows the resulting charge stability diagrams. The
charge transition line pattern changes from exhibiting nearly diagonal lines
at $V_{\rm B34}=0\leavevmode\nobreak\ $mV towards a rectangular grid-like
pattern at $V_{\rm B34}=-500\leavevmode\nobreak\ $mV, revealing the transition
from high to low coupling. In all cases the application of stress voltage
sequences allows to obtain the $(1,1)$ charge state at $\textbf{{V}}^{\rm
T}=(1\leavevmode\nobreak\ {\rm V},1\leavevmode\nobreak\ {\rm V})$. This is
confirmed by the extracted voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm
P}i}^{+}]$ plotted in Fig. 4.f. Crucially, this is achieved without defining
virtual gates. We conclude that for a wide range of interdot couplings single-
electron occupation can be achieved at predetermined plunger gate voltage
independently of the applied barrier voltage.

Figure 5: (1,1,1,1) charge state at 1 V on all plunger gates (a), (b) Charge
stability diagrams recorded after applying stress voltage sequences to tune
the (1,1,1,1) charge state to be the ground state when all plunger gate
voltages are set to 1 V. The first two transition lines of each quantum dot
are indicated by dashed lines. The voltage ranges to keep the system in the
(1,1,1,1) charge state are indicated by horizontal and vertical bars (see
methods). A white square marks the point when all plunger gates are at 1 V.
The plotted signal is the summation of several charge stability diagrams with
identical voltage ranges recorded for slightly varied voltages on the SET
plunger S1 (see supplementary section S7). Contrast is enhanced by a local
contrast normalization (LCN). (a) shows charge transitions of Q1 and Q3 and
(b) exhibits charge transition lines of all four dots.

### (1,1,1,1) charge state at (1,1,1,1) V

Finally, we utilize our findings to tune a $2\times 2$ quantum dot array such
that the $(N_{1},N_{2},N_{3},N_{4})=(1,1,1,1)$ charge state is the ground
state when all plunger gate voltages are set to 1 V. Starting from the Q3-Q4
double quantum dot, we form the quantum dots Q1 and Q2 which are predominantly
controlled by the plunger gates P1 and P2. Then, the system is tuned solely
through tailored stress voltage sequences applied to the plunger gates. Fig. 5
shows two charge stability diagrams recorded after this tuning process
unveiling four sets of charge transition lines. These can be associated with
the four quantum dots by analysing further charge stability diagrams recorded
by sweeping additional plunger gate combinations (see supplementary section
S4). Yellow, orange, red and purple dashed lines mark the first two charge
addition voltages of quantum dot Q1, Q2, Q3 and Q4, respectively. The target
voltage configuration $\textbf{{V}}^{\rm T}=(V^{\rm T}_{\rm P1},V^{\rm T}_{\rm
P2},V^{\rm T}_{\rm P3},V^{\rm T}_{\rm P4})=(1\leavevmode\nobreak\ {\rm
V},1\leavevmode\nobreak\ {\rm V},1\leavevmode\nobreak\ {\rm
V},1\leavevmode\nobreak\ {\rm V})$ is shown by a white square marker and the
voltage ranges that keep the system in the (1,1,1,1) charge state are
indicated by horizontal and vertical bars. $\textbf{{V}}^{\rm T}$ clearly
falls between the first two charge transition lines for all four quantum dots
confirming that we reached the targeted configuration. Note that all quantum
dots are strongly affected by plunger gate P2 and P4 as observable in Fig.
5.b. However, in Fig. 5.a the voltages on P1 and P3 only seem to affect the
charge occupation of Q1 and Q3. We speculate this behavior to originate from
asymmetries in the gate layout and device imperfections [40]. Crucially, we
find that the stressing procedure is effective for the tuning of a nonlinear
quadruple quantum dot array.

## Discussion

In summary, we have shown that single-electron occupation in quantum dots can
be achieved at equal predetermined plunger gate voltage, by making use of a
stress-voltage based procedure. Importantly, we find that after such a tuning
the systems remains stable for hours only exhibiting small progressive drifts
which do not affect the charge configuration. We envision that the stressing
methodology may find several applications in semiconductor quantum technology.
For instance, it may facilitate the operation of crossbar arrays which
crucially rely on shared gate voltages [44, 14]. While our experiments suggest
tunability of the entire potential landscape, more research is needed to
understand the level of control over the barrier potentials. A predetermined
gate voltage to set a given charge state can also relax the requirements on
control electronics and facilitate their integration. Furthermore, we envision
that stressing voltages can provide tunability of other parameters. For
example, the $g$-tensor of germanium qubits is strongly dependent on the
electric field [28, 45], such that stressing voltages may provide tunability
over the qubit resonance frequency. We therefore envision that stressing
procedures may become a standard and essential routine in the tuning of large
quantum circuits.

## Material and methods

### Heterostructure and device fabrication

The device under study in this work is fabricated on a 28Si/SiGe
heterostructure [39] which is based on a Si wafer. First, a linearly graded
Si1-xGex buffer with $x$ varying from 0 to 0.3 is grown followed by a 300 nm
relaxed Si0.7Ge0.3 layer. A 7 nm purified (800 ppm) ${}^{28}\text{Si}$ layer
defines the quantum well and is separated from the gate stack by another 30 nm
thick relaxed Si0.7Ge0.3 buffer that is passivated in dichlorosilane at 500
∘C. Phosphorus ion implantation is utilized to contact the two dimensional
electron gas and a 10 nm aluminum oxide layer precedes the deposition of gate
electrodes. The latter are spread across three layers and made of Ti/Pd
deposited via electron beam evaporation. They are separated by 5 nm thick
layers of aluminium oxide. In all cases aluminium oxide is deposited via
atomic layer deposition [28].

### Setup and voltage pulses

All measurements are performed in a dilution refrigerator at a base
temperature of $\approx 20\leavevmode\nobreak\ $mK. The gate voltages are
supplied by digital analog converters (DACs) with a resolution of 18 bit and a
voltage range of $\pm 4\leavevmode\nobreak\ $V which was amplified to $\pm
20\leavevmode\nobreak\ $V for the plunger gates. The current through the SET
is measured via a current-to-voltage converter connected to a digitizer
module. Confinement and stress voltages are applied via the DACs while charge
stability diagrams are recorded by sending fast voltage pulses. The latter are
generated by an arbitrary waveform generator (AWG). DAC and AWG voltage
signals are merged with a bias tee located on the sample PCB at the mixing
chamber stage. AWG pulses are modified to correct for voltage drifts caused by
(dis)charging of the bias tees. Furthermore, cross-capacitive shifts from P3
and P4 on the sensing dot potential are compensated for by proportionally
adjusting $V_{\rm S1}$ when sweeping the plunger gate voltages $V_{{\rm P}i}$
($\Delta V_{\rm S1}/\Delta V_{{\rm P}i}<0.01$).

### Local contrast normalization

In voltage scans spanning a large range, cross-capacitive coupling of the
plunger gates to the SET can cause significant variations in sensor
sensitivity. This leads to contrast fluctuations across the charge stability
diagram and hampers identification of charge transition lines. We compensated
for this effect by applying a local contrast normalization (LCN). In essence,
a smoothed charge stability map is subtracted to compensate for a slowly
varying offset after which a smoothed local variance is utilized to locally
normalize the signal:

${\rm LCN}(I)=\frac{I-I\ast f_{\mathrm{Gaussian}}}{\sqrt{(I-I\ast
f_{\mathrm{Gaussian}})^{2}\ast f_{\mathrm{Gaussian}}}}$ (1)

Here, the asterisk denominates a convolution, $I$ is the sensor signal and
$f_{\rm Gaussian}$ refers to a normal distribution with a mean and variance
chosen between 4 and 50 pixels.

### Extraction of characteristic voltages from charge stability diagrams

For each charge stability diagram we identify the coordinates of the charge
triple degeneracy points (triple points) that constitute the corners of the
(1,1) charge region. From these we calculate the voltage ranges $[V_{{\rm
P}i}^{-},V_{{\rm P}i}^{+}]$ that keep the system in the (1,1) charge state
around the center point $\textbf{{V}}^{(1,1)}$ (in Fig. 1) or the target
voltages $\textbf{{V}}^{\rm T}$ (in all other figures). The center point
$\textbf{{V}}^{(1,1)}$ of the (1,1) charge region is determined as the
centroid of the triple points at the $(2,0)-(1,1)$ and $(1,1)-(2,0)$ charge
transitions. Note that the voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm
P}i}^{+}]$ are a measure of the maximum voltage variation on a single plunger
gate for which the charge state remains constant. When taking into account
more than a single gate voltage a polytope describes the applicable gate
voltages that keep the charge state at single electron occupation. For
instance, when considering two plunger gates the polytope would be the hexagon
typically found in a double quantum dot honeycomb pattern. While we utilize
one-dimensional voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm P}i}^{+}]$ to ease
visualizations, after all stressing experiments the target voltage point
$\textbf{{V}}^{\rm T}$ lies inside the single charge occupation region (inside
the respective gate voltage polytope).

We have used the triple points for the analysis because of their robustness
against latching effects. For instance, in Fig. 1.b the dashed lines show
reconstructed charge transition lines of quantum dot Q3 which has a weak
coupling to the nearby charge reservoir. Consequentially, $[V_{{\rm
P}i}^{-},V_{{\rm P}i}^{+}]$ can include regions of meta-stable charge state
(in between the observed and the reconstructed charge transition). This does
not impact our conclusions because, at the end of all stressing experiments,
the target voltage point $\textbf{{V}}^{\rm T}$ lies in a region of stable
charge state.

## Data availability

The data and analysis supporting this work are openly available in a public
Zenodo repository at https://doi.org/10.5281/zenodo.8322422 [46].

## Acknowledgements

We gratefully acknowledge D. Degli-Esposti, D. Michalak and M. Mehmandoost for
sharing their expertise on the underlying physics and for their valuable
advice. Furthermore, we thank S. L. de Snoo for software support and all the
members of the Veldhorst, Vandersypen and Scappucci group for many stimulating
discussions.

We acknowledge funding by Intel Corporation. This work is part of the ’Quantum
Inspire – the Dutch Quantum Computer in the Cloud’ project (with project
number [NWA.1292.19.194]) of the NWA research program ’Research on Routes by
Consortia (ORC)’, which is funded by the Netherlands Organization for
Scientific Research (NWO).

## Competing interest

M. Veldhorst is inventor on a patent application related to this work (PCT/N
L2022/050377), filling date 30 June 2022. The other authors declare no
competing financial interest.

Supplementary Information

##  S1 Stress voltage induced crosstalk

Figure S1: Stress voltage induced crosstalk on quantum dots. (a) Trajectory of
the (1,1) charge state center point $\textbf{{V}}^{(1,1)}$ in the $(V_{\rm
P3},V_{\rm P4})$ plane during the tuning experiment shown in Fig. 2 of the
main text (identical to Fig. 2.c). (b) Part of the trajectory between the
points A and AB. The black line is a linear fit to the data to determine the
slope $s^{\gamma}_{34}$ that quantifies the crosstalk of plunger gate P4 on
quantum dot Q3. (c) Illustration of a device cross section portraying the
capacitive effect of the plunger gate voltage $V_{\rm P4}$ on the potential of
quantum dot Q3 ($C^{\alpha}_{34}$) and the crosstalk effect of applying stress
voltages to plunger gate P4 on the potential of quantum dot Q3
($C^{\tau}_{34}$). (d) Schematic charge stability diagram illustrating how the
charge transition voltages of quantum dot Q3 shift when changing the voltage
on plunger gate P4. Grey lines indicate the charge transition lines before and
black lines after changing the potential of Q4 through applying stress
voltages. For illustration purposes the interdot coupling between Q3 and Q4
and the capacitive coupling of P3 onto Q4 are neglected. (e) Example charge
stability diagram taken at point A in (a). The slope $s^{\alpha}_{34}$ of the
transition lines of Q3 (black dashed lines) are determined as a measure for
the relative capacitive effect of plunger gate P4 onto the potential of
quantum dot Q3. To ensure robustness against distortions from charge latching
effects, the Q3 charge transition lines are defined as the lines connecting
the respective triple charge degeneracy points. (f) All extracted
$s^{\alpha}_{34}$ during the tuning from point A to AB in (a). (g) Crosstalk
$s^{\gamma}_{ij}$ caused by stressing plunger gate P$i$ (diamonds) and cross-
capacitance effect $s^{\alpha}_{ij}$ of plunger gate voltage $V_{{\rm P}j}$
(downward pointing triangles) onto the potential of quantum dot Q$i$ along the
trajectory in (a). Between C and CD and CD and D only the last ten points are
fitted to extract $s^{\gamma}_{ij}$. Due to a limited number of data points no
values are shown for the tuning between D and E. (h) Stress voltage induced
crosstalk effect $s^{\tau}_{ij}$ of plunger gate P$j$ onto the potential of
quantum dot Q$i$ corrected for the capacitive coupling of plunger gate P$j$
onto the potential of quantum dot Q$i$.

A stress voltage applied to a plunger gate P$j$ not only alters the potential
of the quantum dot Q$j$ located directly underneath it but also affects
neighbouring quantum dots Q$i$. We investigate this crosstalk by further
analyzing the tuning of the Q3-Q4 double quantum dot presented in Fig. 2 of
the main text. Fig. S1.a shows the trajectory of the center
$\textbf{{V}}^{(1,1)}$ of the (1,1) charge state region in the $(V_{\rm
P3},V_{\rm P4})$ plane (same as Fig. 2.c of the main text). The crosstalk
manifests as a deviation from perfectly horizontal or vertical progressions of
$\textbf{{V}}^{(1,1)}$. We quantify it by applying a linear regression as
exemplary shown in Fig. S1.b for the section from A to AB. The extracted slope
$s^{\gamma}_{34}$ is a measure for the crosstalk of plunger gate P4 onto
quantum dot Q3.

Two mechanisms can explain the observed crosstalk as illustrated in Fig. S1.c:
(1) Tuning the potential landscape of Q4 through the application of stress
voltages also affects the potential of Q3 even if all gate voltages are reset
to their initial value afterwards. For instance, this effect could be caused
by the (de)charging of traps at the interface that capacitively couple to Q3
($C^{\tau}_{34}$) [47, 35, 36, 48, 37]. (2) $V^{(1,1)}_{{\rm P}3}$ is defined
as the middle point between the (1,0)-(1,1) and (1,1)-(1,2) charge transition
at $V_{\rm P4}=V^{(1,1)}_{{\rm P}4}$ (and vice versa). Due to the capacitive
coupling of P4 onto Q3 ($C^{\alpha}_{34}$) a shift in $V^{(1,1)}_{{\rm P}4}$
is therefore also reflected in $V^{(1,1)}_{{\rm P}3}$. Fig. S1.d portrays the
mechanism. It shows a schematic charge stability diagram before (grey charge
transition lines) and after (black charge transition lines) tuning the
potential below P4 through the application of stress voltages. As the Q3
charge transition lines are tilted by the cross-capacitance $C^{\alpha}_{34}$,
a change in $V^{(1,1)}_{{\rm P}4}$ also results in a change of
$V^{(1,1)}_{{\rm P}3}$ (center point of the light and dark pink vertical bar).

To quantify the latter effect we determine the slope $s^{\alpha}_{34}$ of the
Q3 charge transition lines at the (1,1) charge region. Fig. S1.e depicts an
exemplary charge stability diagram during the tuning process with the
respective Q3 charge transition lines indicated by dashed lines. All extracted
$s^{\alpha}_{34}$ between the points A and AB in Fig. S1.a are plotted in
Fig.S1.f. We find that $s^{\alpha}_{34}$ remains constant throughout the
entire stress voltage sequence from A to AB.

The same analysis steps are repeated for all sub parts between A and D of the
trajectory in Fig. S1.a. Fig. S1.g summarizes all $s^{\gamma}_{ij}$ (diamonds)
and $s^{\alpha}_{ij}$ (downward pointing triangles). The magnitude of the
cross-capacitance effect $s^{\alpha}_{ij}$ is consistently larger than the
magnitude of the measured crosstalk $s^{\gamma}_{ij}$. To estimate the stress
voltage crosstalk $s^{\tau}_{ij}$ solely caused by shifts of the intrinsic
potential we subtract $s^{\alpha}_{ij}$ from $s^{\gamma}_{ij}$ and plot the
difference in Fig. S1.h. We find a positive voltage stress related crosstalk,
which has a similar magnitude as the capacitive effect $s^{\alpha}_{ij}$. As
$s^{\tau}_{ij}$ and $s^{\alpha}_{ij}$ have a different sign they partially
cancel each other and lead to a reduced effective crosstalk $s^{\gamma}_{ij}$
when applying stress voltage sequences.

##  S2 Additional time traces recorded after applying stress voltages

Figure S2: Additional time traces after applying stress voltage sequences.
(a)-(c) Time traces of the voltage ranges $[V_{{\rm P}i}^{-},V_{{\rm
P}i}^{+}]$ after the application of a stress voltage sequence. (a), (b) and
(c) are recorded after tuning to the target points A, C and E as presented in
Fig. 2 in the main text, respectively. $t$ is the time after the application
of the last stress voltage. (a) is identical to Fig. 3.a in main text. Note
that the underlying charge stability diagram measurements were interleaved
with charge noise measurements on the sensor (see supplementary section S3).

Fig. S2 shows two additional time traces not shown in Fig. 3 in the main text.
Note that in Fig. S2.b and c the recording of the time traces was started 20 h
and 4 h after the application of the last stress voltage, respectively. The
additional curves confirm that after the application of a stress voltage
tuning the system remains in a (1,1) charge state for 40 h at least only
exhibiting small progressive drifts.

##  S3 Charge noise after applying stress voltages

Figure S3: Sensor charge noise after applying stress voltages. (a) Power
spectral density (PSD) extracted from sensor current time traces recorded
after tuning to point A in Fig. 2.b of the main text.
$S_{\epsilon}=\alpha^{2}S_{I}/|dI/dV_{\rm S1}|$ with $\alpha$ the lever arm of
sensor plunger gate S1 extracted from coulomb diamonds, $|dI/dV_{\rm S1}|$ the
maximum slope of the coulomb peak and $S_{I}$ the PSD of the current through
the sensor [49]. For the measurement the sensor plunger voltage $V_{\rm S1}$
is tuned to the Coulomb peak flank, the voltage for which the sensing quantum
dot is most sensitive to potential fluctuations. The black line is a fit to
$S_{\epsilon}$ between 0.1 Hz and 5 Hz with $S^{\rm fit}_{\epsilon}=A\times
f^{-\kappa}$. The noise amplitude $A$ at 1 Hz is given in the upper right.
$\kappa=0.96$ (b) and (c) Same as (a) but recorded after reaching target point
C and E in Fig. 2.b of the main text, respectively. $\kappa=1.38$ for C and
$\kappa=1.07$ for E.

As the presented tuning procedure might alter the configuration of charge
traps in the heterostructure (see supplementary section S5) we investigate the
system charge noise after applying stress voltages. Specifically, we measure
time traces of the current through the sensing quantum dot (underneath S1) and
compute the power spectral density (PSD). To obtain maximum sensitivity of the
sensor current to potential fluctuations we tune the sensor plunger gate
voltage $V_{\rm S1}$ to the flank of a Coulomb peak. Fig. S3.a, b and c depict
PSD spectra obtained after tuning to the target point A, C and E in Fig. 2.b,
respectively. Note that target points A and C are reached by applying
positively signed stress voltages and target point E is reached by applying
negatively signed stress voltages. The charge noise curves follow the typical
$1/f$ frequency dependence. Therefore we fit them between 0.1 Hz and 5 Hz with
$S^{\rm fit}_{\epsilon}=A\times f^{-\kappa}$ (black line). We find noise
amplitudes of $\sqrt{A}=0.71\leavevmode\nobreak\ \mu{\rm eV}/{\rm Hz}^{1/2}$,
$\sqrt{A}=0.60\leavevmode\nobreak\ \mu{\rm eV}/{\rm Hz}^{1/2}$ and
$\sqrt{A}=0.78\leavevmode\nobreak\ \mu{\rm eV}/{\rm Hz}^{1/2}$ as well as
exponents $\kappa=0.96$. $\kappa=1.38$ and $\kappa=1.07$ for target point A, C
and E, respectively. These values are comparable to charge noise amplitudes in
Si/SiGe reported in the literature [49, 50, 51] and charge noise values
measured in the same device during an earlier cooldown [39]. Thus, we find no
indication that a spin qubit implemented in a stressed quantum dot would be
impaired by a degraded noise environment. However, further research is
required as the charge noise sensed by the sensor might not be representative
for the charge noise affecting qubits that are tuned in the quantum dots.

##  S4 Identification of the four quantum dots

In order to identify the quantum dots visible in Fig. 5 of the main text we
measure multiple charge stability diagrams by sweeping all pairwise
combinations of the device plunger gate voltages. The obtained charge
stability diagrams are plotted in Fig. S4. The center left and bottom center
panel are identical with the charge stability diagrams shown in Fig. 5 of the
main text. All maps are obtained at the same gate voltage configuration and at
their center point all plunger gates are set to 1 V.

The charge stability diagrams can be analyzed starting from one charge
transition line, e.g. the first vertical charge transition line in the center
left panel (indicated by a yellow dashed line). Due to its strong coupling to
plunger gate P1 we identify it as a charge transition line of quantum dot Q1.
We mark the crossing point of this Q1 charge transition line with the $V_{\rm
P1}=1\leavevmode\nobreak\ $V line (vertical white line) by a yellow circle.
Then we place another yellow circle marker at identical $V_{\rm P3}$ on the
$V_{\rm P2}=1\leavevmode\nobreak\ $V line in the center panel of the figure.
The vertical white lines inside one row of figure panels are identical line
cuts in the gate voltage space. Therefore both marked points identify the same
charge transition line of the same quantum dot (Q1). Analogously two charge
stability diagrams in one column of figure panels can be compared. By
repeating the process for all neighbouring charge stability diagrams one can
identify the charge transition lines of four quantum dots Q1-Q4. Note that the
charge transition lines of quantum dot Q4 (purple) latch when the sweep
direction (black arrow in the upper right of each panel) is nearly
perpendicular to the charge transition lines. Therefore the crossing point of
the first Q4 charge transition line with the $V_{\rm P1}=1\leavevmode\nobreak\
$V line in the bottom left panel and the crossing point with the $V_{\rm
P3}=1\leavevmode\nobreak\ $V line in the bottom right panel differ from the
crossing point with the $V_{\rm P2}=1\leavevmode\nobreak\ $V line in the
bottom center panel. Furthermore, in the left column another nearly vertical
charge transition line is visible in the background. However, it shows
negligible coupling to the other charge transition lines and likely is a
signature of a spurious defect quantum dot outside but close to the active
device region.

Figure S4: Charge stability diagrams identifying the quantum dots Q1-Q4.
Charge stability diagrams recorded for all plunger gate combinations. The
arrow in the upper left corner indicates the sweep direction. The center point
(crossing point of the white lines) for each charge stability diagram
corresponds to the same voltage configuration with $V_{\rm P1}=V_{\rm
P2}=V_{\rm P3}=V_{\rm P4}=1\leavevmode\nobreak\ $V. Horizontal white lines
mark identical line cuts in the gate voltage space inside each column of
charge stability diagrams. Vertical white lines mark identical line cuts in
the gate voltage space inside each row of charge stability diagrams. Colored
dashed lines indicate charge transitions and colored circles mark crossing
points of the charge transitions with the white lines. Each color refers to a
quantum dot as indicated by the legend in the upper right. To enhance the
visibility of the charge transition lines the derivative of the sensor current
was taken ad a local contrast normalization (LCN) was applied.

##  S5 Underlying physical mechanisms

Applying a stress voltage to a selected gate electrode possibly alters the
occupation of charge traps in the gate dielectrics and heterostructure
directly underneath [47, 35, 36, 48, 37]. As the electric field bends the
conduction band electrons might tunnel into or out of these charge traps.
Removing the stress voltage then effectively freezes their occupation which
permanently alters the intrinsic potential landscape. Charge traps can be
present in the oxide layer [52, 53, 54, 55], originate from unpassivated
silicon and germanium dangling bonds [53, 54, 55] or arise from mechanical
stress induced by the deposition of metallic gate electrodes [30, 32].
Furthermore, also the relocation of mobile ions might change the intrinsic
potential [56]. Note that these processes in general are independent of the
quantum well material itself and stress-voltage-controlled shifts of the
intrinsic potential also have been observed in Ge/SiGe heterosturctures [57,
38].

##  S6 Raw data underlying Fig. 1-4 of the main text

Fig. S5, S6, S7, and S8 display the unprocessed charge stability diagram data
underlying Fig. 1.b, 2.f, 3.b, and 4.a-e of the main text, respectively.

Figure S5: Raw data underlying Fig. 1.b. of the main text Figure S6: Raw data
underlying Fig. 3.f of the main text. Figure S7: Raw data underlying Fig. 3.b
of the main text. (a) Charge stability diagram taken at the beginning of the
time trace shown in Fig. 3.a of the main text. (b) Charge stability diagram
taken at the end of the time trace shown in Fig. 3.a of the main text. Figure
S8: Raw data underlying Fig. 4 of the main text. (a)-(e) correspond to Fig.
4.a-e of the main text, respectively.

##  S7 Raw data underlying Fig. 5 of the main text

Fig. S9 and Fig. S10 show the unprocessed charge stability diagram data
underlying Fig. 5.a and b of the main text, respectively. Each map is recorded
at a different sensor gate S1 voltage to account for the cross-capacitance
effect of the plunger gates on the sensing dot potential which limits the
sensing dot sensitivity to small plunger gate voltage ranges.

We combine the charge stability diagrams by summing up the sensor current
signals as exemplary shown in Fig. S11.a for the data shown in Fig. S10.
Afterwards, the signal gradient $\nabla I$ is calculated as depicted in Fig.
S11.b. Finally, a local contrast normalization (see methods section) is
applied to allow for an eased identification of charge transition lines across
the full map. Fig. S11.c depicts the resulting charge stability diagram which
is identical to the charge stability diagram shown in Fig. 5.b of the main
text.

Figure S9: Charge stability diagrams underlying Fig. 5.a. (a)-(f) Multiple
charge stability diagrams showing charge transition lines of quantum dot Q1
and Q3. Maps are taken at various sensor gate S1 voltages as indicated above
the plots. Figure S10: Charge stability diagrams underlying Fig. 5.b. (a)-(e)
Multiple charge stability diagrams showing charge transition lines of quantum
dot Q1-4. Maps are taken at various sensor gate S1 voltages as indicated above
the plots. Figure S11: Processing of the data underlying Fig. 5.b. (a) Sum of
the sensor response $I$ of the charge stability diagrams shown in Fig. S10.
(b) Gradient $\nabla I$ of the data shown in (a). (c) Final signal ${\rm
LCN}(\nabla I)$ after applying a local contrast normalization to the map shown
in (b).

##  S8 Overview of applied gate voltage configurations

Figure S12: Gate voltage evolution during the presented experiments. Each
panel shows the gate voltage evolution of a single gate during the experiments
presented in the figures of the main text as given on the x-axis. Note that
$V_{\rm S2C}=0\leavevmode\nobreak\ $V during all experiments. The inset shows
an SEM image of a device nominally identical to the one under study.
Confinement gates are outlined by a white dashed line. Labels indicate the
gate electrode naming convention utilized throughout the manuscript and in the
panels of this figure.

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