††thanks: Present address: Harvard University, Cambridge, MA 02138, USA

# Characterizing quantum processors using discrete time crystals

Victoria Zhang  Paul D. Nation<EMAIL_ADDRESS>IBM Quantum, Yorktown
Heights, NY 10598, USA

###### Abstract

We present a method for characterizing the performance of noisy quantum
processors using discrete time crystals. Deviations from ideal persistent
oscillatory behavior give rise to numerical scores by which relative quantum
processor capabilities can be measured. We construct small sets of qubit
layouts that cover the full topology of a target system, and execute our
metric over these sets on a wide range of IBM Quantum processors. We show that
there is a large variability in scores, not only across multiple processors,
but between different circuit layouts over individual devices. The stability
of results is also examined. Our results suggest that capturing the true
performance characteristics of a quantum system requires interrogation over
the full device, rather than isolated subgraphs. Moreover, the disagreement
between our results and other metrics indicates that benchmarks computed
infrequently are not indicative of the real-world performance of a quantum
processor. This method is platform agnostic, simple to implement, and scalable
to any number of qubits forming a linear-chain, while simultaneously allowing
for identifying ill-performing regions of a device at the individual qubit
level.

##  I Introduction

Computing the performance characteristics of quantum processors has long been
a mainstay of quantum computing research [1, 2, 3, 4]. More recently, as
quantum devices have reached qubit counts beyond these more rigorous methods,
focus has moved to holistic benchmarks [5, 6] and suites of test-circuits [7,
8, 9, 10, 11] to validate progress. With the public availability of multiple
quantum processor technologies, these “application benchmarks” allow for
performance comparisons across platforms that take into account the strengths
and weaknesses of each approach.

Here we propose a new characterization method based on recent demonstrations
of discrete time crystals (DTC) [12, 13]. DTC has several properties that make
it suitable for characterizing quantum hardware. First, the non-equilibrium
DTC state of an ideal periodically driven many-body system exhibits stable
oscillations of the single-qubit polarization $\langle Z_{i}(t)\rangle$,
deviations from which indicate imperfections in the system (noise), and
provide a natural means by which to characterize processor performance.
Second, unlike benchmarks such as Quantum Volume (QV) [6] that effectively
twirl away coherent errors [14, 15], DTC evolution is generated by periodic
applications of a unitary that enhances coherent errors in the system, and is
thus sensitive to noise sources that benchmarks with random structure might
otherwise miss. Moreover, in contrast to many Hamiltonian simulation test-
circuits that need some level of Trotterization specified, DTC evolution is
exact, simplifying the analysis.

In this work we show that DTC allows for in-depth characterization of quantum
processor performance. Unlike most quantum benchmarks and test suites, where
device performance is gauged on only a subset of qubits, we are interested in
both the local and device-wide performance of a quantum processor. While full
system characterization requires running circuits on every compatible subgraph
of the full device topology; a task that scales unfavorably as device
connectivity and number of qubits grows, here we take advantage of the fact
that computing a set of physical qubit layouts (subgraphs) corresponding to a
given input circuit is fast relative to other compilation timescales [16], and
use a minimal, or close to minimal, set of layouts that extends over the full
topology of the device as a proxy for complete system characterization.

We execute our DTC benchmark on the majority of IBM Quantum systems, and
compare the performance across these processors. In particular, we find that
there are large performance variations over quantum systems with numbers of
qubits large enough to support multiple disjoint layouts. Additionally we see
that other stated metric values attached to each processor are, in general,
not good predictors of DTC circuit performance. The locality of noise in
systems with many-body localization [17, 18, 19] allows variations across a
device to be traced to individual qubits that perform poorly, indicating a
strong local noise environment; qubits act as regional noise barometers.
Finally, we also look at stability of our benchmark over time and find that,
while there are large variations in the absolute performance scores for a
given qubit layout, including within a single calibration cycle, sections of
the chip with the highest relative reported values tend to remain optimal over
time. Our method is platform agnostic and simple to implement, providing a
faithful metric by which relative quantum processor performance can be gauged
and tracked over time.

The paper is organized as follows. First, in Sec. (II) we describe our method
of DTC characterization focusing on circuit creation, performance metric
definition, and detailing the procedure for layout construction used for full-
device performance evaluation. Section (III) looks at the results of running
$5$ and $20+$ qubit DTC performance evaluations over IBM Quantum systems,
including a discussion of the stability of results over time. Finally, we
summarize the results in Sec. (IV), discuss how to interpret these findings,
and point to possible future research directions utilizing the methods
presented here. Appendix (A) includes a discussion of noise localization in
systems such as DTC, including a simulation highlighting this localization for
the circuits used in this work.

##  II Methodology

Our starting point is the unitary operator for a DTC corresponding to a
linear-nearest neighbor Hamiltonian with discrete time-translation symmetry,
Eq. (1) from Ref. [13]

$\hat{U}=e^{-\frac{i}{2}\sum_{j}h_{j}\hat{Z}_{j}}~{}e^{-\frac{i}{4}\sum_{j}\phi_{j}\hat{Z}_{j}\hat{Z}_{j+1}}~{}e^{-i\frac{\pi
g}{2}\sum_{j}\hat{X}_{j}},$ (1)

where $g$ controls the angle of rotation for all qubits about the x-axis, and
$\phi_{j}$ and $h_{j}$ are phases drawn at random from a uniform distribution
whose average value is dependent on the selected value of $g$ [20]. While the
use of random parameters is required to stabilize the many-body localization
needed for observing DTC [17], the ability to create random instances of
circuits is also a desired property for characterizing quantum systems.

Our characterization circuits are formed by generating a specific realization
of Eq. (1), $\hat{\mathcal{U}}$, specified by the number of qubits $q$, a
given $g\sim 1$, and a corresponding random set of phases set by a random
number generator seeded with a given integer. This unitary is then used to
generate a family of circuits, each with an increasing number of
$\hat{\mathcal{U}}$ applied to a specific initial state $|\psi(0)\rangle$:
$\\{\hat{\mathcal{U}}^{n}|\psi(0)\rangle~{}|~{}n\in[0,N_{\rm max}]\\}$, where
$N_{\rm max}$ is the maximum number of discrete cycles we wish to observe.
While we are free to pick any initial state, here we select the ground state
of the system $|\psi(0)\rangle=|0^{\otimes q}\rangle$, as any deviations from
ideal behavior when no $\hat{\mathcal{U}}$ are applied can then be directly
equated to state preparation and measurement (SPAM) errors in the system.

Figure 1: Layouts corresponding to the 5-qubit covering set used on IBM
Quantum 27-qubit Falcon processors in this work.

We are interested in the cycle amplitude $A_{j}(n)$ of qubit $j$, defined to
be the absolute difference in polarization values between the $n_{\rm th}$ and
$n_{\rm th}+1$ cycles: $A_{j}(n)=\left|\langle Z_{j}(n+1)\rangle-\langle
Z_{j}(n)\rangle\right|$. From simple depolarizing noise model simulations it
is expected that the cycle amplitude decays exponentially, suggesting that we
can define a cycle visibility threshold of $2/e$, below which the cycle
amplitude $A_{j}(n)$ is considered no longer visible. The maximum number of
cycles for which a given $A_{j}(n)$ is above this visibility threshold is
defined to be the number of visible cycles, $N_{\rm vis}$, and is the quantity
of interest in our characterization.

Noise localization in DTC allows us to connect the number of visible cycles to
the local errors acting on a qubit. This is easiest seen in the small-error
limit of the depolarizing model [17], and ignoring single-qubit gate errors
that are over an order of magnitude smaller than those of two-qubit gates on
IBM Quantum systems. This leads to an approximate expression for the number of
visible cycles on the $i$-th qubit $N^{(i)}_{\rm vis}$:

$N^{(i)}_{\rm
vis}\simeq\frac{15}{16}\frac{g(\Gamma_{i})}{\left(\epsilon_{i}^{\rm
left}+\epsilon_{i}^{\rm right}\right)},$ (2)

where $\epsilon_{i}^{\rm left}$ and $\epsilon_{i}^{\rm right}$ are the two-
qubit entangling gate errors to the left and right of the $i$-th qubit in the
chain, respectively, and $g(\Gamma_{i})\lesssim 1$ relates the qubit readout-
error, $\Gamma_{i}$, in the weak-error limit to the corresponding reduction in
the cycle-amplitude. Note that, while Eq. (2) makes clear the functional
relationship between the number of cycles and the error rates acting on a
qubit, in practice this expression need not be valid for all qubits in a
device. Indeed, we will encounter examples of both strong readout and gate
errors in Sec. (2).

For comparing results over multiple qubits, we use the mean number of visible
cycles over the set of qubits. This value does not require classical
simulation to evaluate, allowing our metric to scale beyond $\mathcal{O}(10)$
qubits. Note that we could also derive a metric based on values for the decay
rate in the cycle amplitude curves found via curve fitting. However in
practice, deviations from ideal exponential decay can lead to difficulties in
fitting, and curve fitting requires a large number of circuit evaluations. In
contrast, although not done here, our metric based on cycle visibility allows
for iterative execute of circuits only up to the point where visibility is
lost; the cost of performing DTC characterization can be greatly reduced.

Due to the wide variability in important system metrics seen in near-term
quantum systems [16], reporting the number of visible cycles, or any other
characterization values, over just a subset of qubits fails to capture many
aspects of device performance. While it is relatively fast to compute all
possible subgraphs that are compatible with a given input circuit [21, 22],
the combinatorial explosion of possibilities renders execution on hardware
unfeasible. As a proxy for this full characterization we introduce a covering
set of physical qubit layouts, that corresponds to a reduced set of layouts
that cover the full device entangling gate topology (coupling map). In this
work, this set is produced starting with an initial layout, e.g. as given by
rustworkx [23], and adding subsequent layouts that maximize the relative
compliment between the edges of the system topology already in the set and
those in the considered layout. This procedure is continued until all the
edges of the device topology are in the set. This greedy algorithm does not
guarantee that the covering set is a minimal, but in practice it often is, or
very close to it. An example covering set for 5-qubit DTC circuits over the
topology for 27-qubit IBM Quantum Falcon systems is shown in Fig. (1).

##  III Results

###  III.1 5-qubit DTC characterization

To begin, we consider the number of visible cycles for a 5-qubit DTC
characterization. This allows for comparing our performance metric across the
majority of IBM Quantum systems, and is also the same width as QV32 circuits,
the minimal value for most processors, giving us a baseline for comparing our
metric against the reported QV value for each system. We generate DTC circuits
[24] out to $N_{\rm max}=80$ using Eq. (1), by setting $g=0.95$, and $\rm RZZ$
gate parameters sampled uniformly from the interval $[\pi/8,3\pi/8]$. Random
$\rm RZ$ gate angles are sampled over the interval $[-\pi,\pi]$. The
corresponding circuit for $\hat{\mathcal{U}}$ generated using a random number
generator with seed=12345 is shown in Fig. (2).

Figure 2: The circuit for the 5-qubit DTC unitary operator used for
characterization across systems.

Circuits are compiled using Qiskit [25] with optimization_level=3, and mapped
onto covering sets using mapomatic [16, 26]. We use the Qiskit Runtime Sampler
primitive for circuit execution, and jobs corresponding to individual layouts
in a covering set are batched within a Runtime Session so that they execute
sequentially on-chip; individual jobs are not subject to the fair-share
scheduling priority. We sample all circuits $10^{4}$ times for reasonable
precision in the computed polarizations, and set skip_transpilation=True as
our circuits are already mapped to the target device. Additionally, the
default readout mitigation performed by the Sampler is disabled by setting
resilience_level=0.

Figure (3) shows the mean cycle visibility for the 10 layout covering set from
Fig. (1) using the unitary $\hat{\mathcal{U}}$ in Fig. (2) on the 27-qubit IBM
Quantum Auckland system.

Figure 3: Mean amplitude of layouts in a covering set, Fig. (1), as a function
of the number of DTC cycles on the 27-qubit IBM Quantum Auckland system.
Dashed horizontal line shows the $2/e$ threshold for visibility.

We see that there is a marked difference in the average cycle amplitude decay
rates across the layouts, highlighting the variability in performance across
the system; something that would be missed if we did not probe the full
topology. This in turn gives rise to visible cycles ranging from 45 cycles
(layout 0) down to 3 (layout 3), yielding a system wide average visibility of
16.7 cycles. Layouts that deviate from the ideal value ($2$) at zero cycles,
e.g. layouts 3 and 8 in Fig. (3), where no $\hat{\mathcal{U}}$ has been
applied indicate that the qubits are not in the ground state as expected, and
that SPAM errors are non-negligible over one or more qubits in the layouts,
i.e. $g(\Gamma_{i})<1$ in Eq. (2). At the time of execution, Auckland
calibration data, Fig. (5), indicated that qubit 15 had a readout error rate
of $\sim 30\%$. This qubit is in both layout 3 and 8, corroborating our model,
and highlighting the sensitivity of DTC characterization on underlying device
performance metrics.

Figure 4: Qubit polarization per cycle from Fig. (3) for qubits
$[10,12,15,18,17]$ forming layout 8. Figure 5: Error map for the 27Q IBM
Quantum Auckland system generated from calibration data taken on October 31,
2022. Edges of the graph colored red indicate CNOT gates that failed the
calibration procedure; nominally a signature of gates with outsized error
rates. Figure 6: Results of executing 5-qubit DTC characterization over a
covering set for each quantum processor. The same covering set is used for
processors with matching topologies. Systems are ordered by increasing qubit
count and reported QV values. Processors with no reported QV values are
presented last.

In general, the poor performance of a given layout cannot be attributed to
uniformly low-performing qubits. Rather, it is nominally a small number of
qubits within the given layout that swing the average lower. As an example, in
Fig. (4) we plot the single-qubit polarization values for the qubits
comprising layout 8 in Fig. (3). It is clear that two qubits, $\rm Q15$ and
$\rm Q18$, fail to perform even a single meaningful oscillation, and thus
greatly diminish the visibility of the set as a whole. Once again, this agrees
with the calibration data, Fig. (5), where two out of the four CNOT gates in
the layout failed calibration due to their large error rates. Layout 3 also
covers $\rm Q15$ and $\rm Q18$, see Fig. (1), and shows even lower cycle
visibility, suggesting there are additional faulty qubits in that set. That
individual qubits can be corrupted without affecting the layout as a whole is
a direct result of noise localization in many-body localized systems; qubits
are primarily sensitive to only those noise sources that act directly on the
qubit itself. A simulation of this noise localization is given in App. (A).
From Eq. (2), our characterization based on average number of visible cycles
can be approximately viewed as the average of the inverse gate errors acting
on individual qubits in a layout, with each component weighted by a term
proportional to the qubit readout error.

Although much of the DTC characterization performance corresponds well to
device calibration data, this is not universally the case. For example, layout
4 in Fig. (1) covers a section of the Auckland system with error rates well
below the device average [see Fig. (5)], yet the DTC characterization in Fig.
(3) reveals that this section of the chip performs poorly, failing to achieve
double-digit numbers of visible cycles; system data derived from one- and two-
qubit calibrations can fail to capture real-world performance. This
underscores the need for characterization methods like DTC in evaluating the
quality of quantum systems.

Having examined DTC characterization of a single quantum system, we now turn
to performance comparisons across multiple quantum processors. We repeat the
same characterization performed on the Auckland device across a wide range of
compatible IBM Quantum systems with the results presented in Fig. (6). The
same covering set as Auckland was used for all 27-qubit machines, while a new
covering set was generated for other unique system topologies. Figure (6)
shows that, like the earlier results on Auckland, there is a large variability
in device performance on systems with 27+ qubits, where there is little
overlap between the individual layouts within the covering sets. Many
processors include subgraphs with visibilities in the single-digits indicating
that a wide range of systems have one or more qubits with strong local noise
that can greatly shift the mean cycle visibility lower at the granularity
considered here. The systems with layouts supporting the largest visible
cycles, the Kyiv and Peekskill systems, also have the largest fluctuations in
scores indicating that, while sections of the devices perform well, there is a
large degree of variability in terms of quality across the chips. Users
executing experiments on these devices would therefore experience vastly
different performance depending on the qubit layout used in circuit
compilation. This emphasizes how device-wide characterization and qubit
selection is critical for achieving high fidelity results on near-term quantum
devices

Figure (6) also reveals that the measured system performance is, in general,
uncorrelated to the reported QV values for the systems. In particular out of
the QV128 systems, only the Kolkata device contains a layout that bests lower
QV systems in our tests, save for the single high-visibility outlier layout on
the QV64 Kyiv system. In contrast, the QV128 Montreal and Mumbai systems are
unable to match the performance of even the QV16 Jakarta system. As a whole we
see that the IBM Quantum Peekskill system, with no reported QV value, performs
the best on average, with 4 layouts supporting 45+ visible cycles; there are
5Q regions of the topology with relatively little noise. We caution that the
results presented in Fig. (6) do not equate to claims that our metric and QV
benchmarking are at odds with each other. Rather, the disparity can likely be
attributed to the fact that the reported QV values for a given system are
nominally computed once, usually at system bring-up, and therefore may not be
indicative of device performance at the time of DTC testing. Some reported QV
values are more than one year old. In addition, the QV score of a system is
computed only over a very specific set of qubits deemed to be the best
performing set at the time and thus QV, like other metrics reported on
singular subgraphs, is not indicative of total system performance.

While computing the QV of a system is difficult for users, especially QV64 and
higher [27], we can look at the stability of the system through the lens of
DTC. Figure (7) shows the number of visible cycles per layer in the covering
set for IBM Quantum Auckland, measured over the course of a week. It is clear
that, even on the timescale of a single day, there are large swings, up to 11,
in the number of visible cycles for layers capable of more than single-digit
visibility. Taken as a whole, the data for Auckland shows a visible cycle
variability of $\sim\pm 20\%$ over the course of a week. However, while the
absolute cycle visibility shows marked deviations, the most performant sets of
qubits remain optimal despite of these fluctuations; the relative quality of
sets of qubits is more consistent over time. The variability seen in Fig. (7)
gives credence to the idea that infrequently computed benchmarks like QV are
not faithful predictors of current near-term system performance. Taken
together with Fig. (6), our results suggest that users looking to maximize the
fidelity of their circuits could benefit from more frequent full-system
characterization information.

Figure 7: Stability of DTC cycle visibility for the 10 layouts in the 5-qubit
covering set, Fig. (1), on the IBM Quantum Auckland system. Characterization
was run repeatedly from October 24th to October 31st, 2022. Variability
between data points is due to lack of system availability, e.g. low scheduling
priority, system reservations, calibration periods, etc.

###  III.2 20+ qubit DTC characterization

We now extend DTC characterization to layouts with 20+ qubits. With our metric
equating to average of the inverse noise strength experienced by qubits within
a given layout, we expect a reduction in the variance of results across a
system as the effect from individual noisy qubits becomes less appreciable,
and layouts within a covering set increasingly overlap. It might also be
assumed that the device wide average over a covering set remains relatively
constant when the number of qubits increases. However, our 5-qubit DTC results
are greatly impacted by edge-effects due to the short-length of the layouts.
In particular, qubits at the edge of a chain participate in two-qubit
interactions with only a single neighboring qubit; one of the two terms in the
denominator of Eq. (2) is zero. In contrast, qubits in the bulk have two
neighbors that they interact with and therefore, all else being equal, qubits
at the interior of a layout have fewer visible cycles as they partake in more
noisy interactions. We therefore expect that, at small numbers of qubits, the
system-wide average visibility is boosted by edge-effects that are suppressed
at larger layout lengths.

Figure 8: Results of 20-qubit DTC covering set characterization. Systems are
ordered by increasing qubit count and reported QV values.

This intuition is confirmed in Fig. (8) where 20Q DTC characterization is
performed over IBM Quantum systems with 27 or more qubits. We see that there
is an overall decrease in the average number of visible cycles over the
covering sets as compared to our 5-qubit results, highlighting the edge-
effects present in small width DTC circuits. The decreased variance between
layouts within a covering set is also inline with expectations, however at
20-qubits there are still large variations in performance across the IBM
Quantum Kyiv system that are not seen on the Washington system of the same
size. This indicates that there are uncommonly large portions of the system
exhibiting bipolar performance characteristics. Once again, we see little
correlation with reported QV values, with QV128 systems Montreal and Mumbai
scoring on par with QV32 (Geneva) and QV64 (Cairo) machines. While IBM Quantum
Peekskill was the best performing system on 5-qubit DTC characterization, at
20-qubits the Ithaca system supports the largest average number of visible
cycles. Surprisingly, the average 5- and 20-qubit DTC scores are nearly
identical for Ithaca, suggesting that edge-effects do not have a big impact on
this system. However, because the 20-qubit DTC data was not taken at the same
time as the 5-qubit results, other issues such as device stability [Sec.
(III.1)] may also play an attributing role.

In Table (1) we focus on the 65Q IBM Quantum Ithaca and 127Q Washington
systems going out to increasing numbers of qubits for DTC characterization.

| 20-qubit | 30-qubit | 40-qubit | 50-qubit
---|---|---|---|---
Mean cycle visibility | 22.7 | 25.0 | 25.6 | 25.5
Standard deviation | 3.5 | 3.0 | 1.6 | 1.1
Number of layouts | 6 | 4 | 4 | 4
(a) 65Q Ithaca

| 20-qubit | 40-qubit | 60-qubit | 80-qubit
---|---|---|---|---
Mean cycle visibility | 10.0 | 10.4 | 11.1 | 11.2
Standard deviation | 2.6 | 1.8 | 1.4 | 1.0
Number of layouts | 11 | 7 | 6 | 5
(b) 127Q Washington

Table 1: Mean cycle visibility, standard deviation, and number of layouts for
the 65-qubit Ithaca and 127-qubit Washington systems as a function of the
number of qubits used in DTC characterization.

The lack of appreciable changes in the number of visible cycles shown in
Table. (1) as we increase the number of qubits indicates that DTC
characterization at $\sim 20$ qubits is sufficient to suppress edge-effects in
our covering set results. Although increasing the length of the layouts used
in DTC characterization reduces the variance in the data, it is clear even at
20-qubits that the Ithaca system performs much better than Washington,
averaging $\sim 2.5$x the number of visible cycles; there is a pronounced
reduction in the local noise seen by qubits in the Ithaca system as compared
to the Washington device. This is generally inline with system calibration
data taken from the machines, however differences in the relative performance
between DTC characterization and predicted performance based on system
calibration data occur across both machines, allowing only a qualitative
comparison to be made.

##  IV Conclusion

We have demonstrated that DTC allows for meaningful, in-depth characterization
of near-term quantum processor performance through systematic evaluation of
the majority of the IBM Quantum processor fleet. Our method is easy to
evaluate, and can be executed across the full-topology of a quantum system,
yielding insights into device quality that would otherwise go overlooked with
single subgraph evaluation. Owing to many-body noise-localization present in
DTC, we are able to not only evaluate linear-chains of qubits but also
pinpoint poor performing regions of a quantum system down to the single-qubit
level. Our results are corroborated by device calibration data, while
providing a more faithful tally of system performance than is possible with
one- and two-qubit benchmarking. Using DTC we have tracked the stability of
quantum processors, and have seen that there are sizable variations in
absolute system performance, but that relative performance of qubit layouts
does not vary greatly over time. This indicates that metrics computed
infrequently are not faithful indicators of performance, and we have shown
that system quality as measured by DTC is in general not correlated with the
reported QV values for IBM Quantum systems due to infrequent computation of
the latter.

The noise-locality of DTC allows for the method described here to be extended
in a variety of novel ways. Rather than full-characterization, DTC can be used
to efficiently probe a quantum system for “faulty qubits"; qubits that can
perform only a limited number of visible cycles. Because the number of cycles
for faulty qubits is small, the number of circuit executions is minimal,
leading to a quick method by which regions of a system defined by the layouts
in a covering set possessing large local noise can be interrogated. Taken a
step further, because each qubit acts as a local noise barometer, the number
of visible cycles from DTC characterization is effectively mapping out the
noise profile of a quantum device. Thus with judicious selection of covering
sets and readout error mitigation [28], it is possible to use the method here
to create an effective error map of a quantum system. The use of such error
maps, either independently or in conjunction with with device calibration
data, for qubit selection (e.g. using mapomatic [16]) is currently an ongoing
effort. The wealth of information obtainable via DTC experiments, that goes
beyond that found in other application-based test circuits, will likely make
it a mainstay of quantum computing characterization methods for near-term
quantum systems.

###### Acknowledgements.

The authors thank Isaac Lauer, Doug McClure, David McKay, Hasan Nayfeh, and
Sami Rosenblatt for helpful discussions. VZ was supported by a Quantum
Undergraduate Research at IBM and Princeton (QURIP) 2022 internship. All
figures, save for Fig. (5), are created with Matplotlib [29].

Figure 9: (a) A linear nearest-neighbor chain of qubits with the CNOT error
rate between qubits $2$ and $3$ set at $10\%$ assuming a depolarizing noise
model. (b) Simulation of the circuit from Fig. (2) using the model from (a) to
compute the single-qubit polarization values for qubits $0\rightarrow 2$. The
results for qubits $3$ and $4$ closely match those of qubit $2$ and $1$,
respectively.

##  Appendix A Noise localization

One of the advantages of utilizing DTC for characterization lies in the
confinement of noise in many-body localized systems [17, 18, 19]. This allows
us to consider the number of visible cycles on each qubit as a relative gauge
of the local noise strength. Although this effect has already been examined in
Ref. [17], we do so again here for completeness, and to confirm that this
localization of noise is valid in the circuits used in this work. To do so, we
consider a 5-qubit linear nearest-neighbor topology, as shown in Fig. (9a),
where the CNOT gate between qubits $Q2$ and $Q3$ is subject to a depolarizing
noise model with $10\%$ error rate. All other gate and qubit values are
assumed to be ideal. Figure (9b) shows simulations of the single-qubit
polarization values, $\langle Z_{i}\rangle$, for qubits $0\rightarrow 2$ over
a range of cycles for the circuit shown in Fig. (2). From this figure it is
clear that while the large error between $Q2$ and $Q3$ leads to a strong decay
in the polarization for those qubits, other qubits not directly participating
in the noisy two-qubit gate are only weakly affected. In this example,
although $Q2$ is heavily suppressed (only 5 visible cycles), we must go out
relatively large numbers of cycles to see appreciable decay in the
polarization for $Q1$. $Q0$, being further away in the topology, shows even
weaker signatures of the noise on its polarization values. In Fig. (9b) both
$Q1$ and $Q0$ have $200$ visible cycles, and could support many more had we
considered a larger $N_{\rm max}$ in the simulations.

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