# Current-limiting amplifier for high speed measurement of resistive switching
data

T. Hennen<EMAIL_ADDRESS>IWE II, RWTH Aachen University, 52074 Aachen,
Germany  E. Wichmann  IWE II, RWTH Aachen University, 52074 Aachen, Germany
A. Elias  Western Digital San Jose Research Center, 5601 Great Oaks Pkwy, San
Jose, CA 95119  J. Lille  Western Digital San Jose Research Center, 5601 Great
Oaks Pkwy, San Jose, CA 95119  O. Mosendz  Western Digital San Jose Research
Center, 5601 Great Oaks Pkwy, San Jose, CA 95119  R. Waser  IWE II, RWTH
Aachen University, 52074 Aachen, Germany  D. J. Wouters  IWE II, RWTH Aachen
University, 52074 Aachen, Germany  D. Bedau<EMAIL_ADDRESS>Western
Digital San Jose Research Center, 5601 Great Oaks Pkwy, San Jose, CA 95119

###### Abstract

Resistive switching devices, important for emerging memory and neuromorphic
applications, face significant challenges related to control of delicate
filamentary states in the oxide material. As a device switches, its rapid
conductivity change is involved in a positive feedback process that would lead
to runaway destruction of the cell without current, voltage, or energy
limitation. Typically, cells are directly patterned on MOS transistors to
limit the current, but this approach is very restrictive as the necessary
integration limits the materials available as well as the fabrication cycle
time. In this article we propose an external circuit to cycle resistive memory
cells, capturing the full transfer curves while driving the cells in such a
way to suppress runaway transitions. Using this circuit, we demonstrate the
acquisition of $10^{5}$ $I,V$ loops per second without the use of on-wafer
current limiting transistors. This setup brings voltage sweeping measurements
to a relevant timescale for applications, and enables many new experimental
possibilities for device evaluation in a statistical context.

††preprint: AIP/123-QED

##  I Introduction

Today, much effort is focused on employing emerging materials and physical
mechanisms for the purpose of data storage and computationWouters, Waser, and
Wuttig (2015); Yu and Chen (2016); Burr  _et al._ (2017); Sangwan and Hersam
(2020); Ma  _et al._ (2019). Several schemes make use of Resistive Switching
(RS), which refers to a large class of related phenomena wherein the
resistance of a two-terminal device can be controlled via electrical stimuli
Ielmini and Waser (2015). These effects can be used, as in Resistive Random
Access Memory (RRAM), to store bits as non-volatile resistance states.
Resistive switches can be fabricated using wide variety of CMOS-compatible
materials, and are highly attractive due to their simple device structure,
high speed, scalability, and potential for 3D integration as required by next
generation memory and computing architectures.

A central challenge for RRAM is the intrinsically stochastic nature of the RS
process, which leads to large variability in the programmed resistance states
and switching parameters Chen and Lin (2011); Fantini  _et al._ (2013).
Achieving an acceptable level of control over the switching process will
require an in-depth understanding of the statistical processes at play, as
well as an optimization of active material together with the control
circuitry. For this purpose, it is necessary to drive memory cells through a
statistically significant number switching cycles, and to rapidly test
different materials and modes of operation on a wafer probing system.

RRAM is commonly benchmarked by direct application of square voltage pulse
sequences, but one of the shortcomings of this approach is that only the
resulting resistance states are typically recorded, while the dynamics of the
conductance changes in the material are very often left unmeasured.
Quasistatic $I,V$ loops are an alternative measurement where switching is
induced by an applied voltage that is continuously ramped at low speed
($\sim$1 V/s) between positive and negative values. The current resulting from
these sweeps is sampled and plotted against the applied voltage as shown in
Fig. 1. Such $I,V$ loops are relatively rich in information, and important
parameters such as the resistance non-linearity, voltage/current switching
thresholds, and details of the transition behavior can be extracted. However,
the low speed of the measurement puts excessive electrical stress on the
device and makes experiments involving more than a few hundred switching
cycles impractical.

Figure 1:  Schematic diagram of a single cycle $I,V$ loop measurement. Such
loops show statistical variation device-to-device and cycle-to-cycle, and
important switching parameters may be extracted from their measurement.
Figure 2:  Crossbar structures (100 nm) before (left) and after (right) being
subjected to a current overshoot induced by an SMU with current compliance
(top), and capacitive discharge of a 20 cm coaxial cable placed after a
current limiting series resistance (bottom). Although the cells are visibly
destroyed, both nevertheless continued to show measurable RS behavior, as a
conducting path still existed through what remained of the oxide material.

While negative resistance transitions in RS materials can occur on timescales
below 1 nsTorrezan  _et al._ (2011); Menzel  _et al._ (2019); von Witzleben
_et al._ (2020), the nanoscale material volumes involved cannot normally
survive prolonged exposure to the voltage required to initiate the transition,
as the current density quickly reaches levels that cause irreversible thermal
damageMeng  _et al._ (2020). Thus, $I,V$ loop measurements are only possible
in the context of a feedback mechanism to prevent runaway destruction of the
RS device. Externally implemented current limiting such as the current
compliance function of commercial Source Measure Units (SMUs) and
Semiconductor Paramater Analyzers (SPAs) are known to cause large overshoots
that can lead to catastrophic damage to cellsLu  _et al._ (2012); Tirano  _et
al._ (2011) (Fig. 2) and can otherwise strongly influence the
measurementsKinoshita  _et al._ (2008); Ambrogio  _et al._ (2016). Patterning
RS devices directly on MOS transistors provides superior current limiting, but
the required integration limits the materials available and necessitates long
fabrication cycle timesKinoshita  _et al._ (2008); Nardi  _et al._ (2011);
Nguyen  _et al._ (2015). A simpler approach from the point of view of
fabrication is to integrate fixed resistors in series with the devices Fantini
_et al._ (2012); Fan  _et al._ (2015). However, the large linear feedback
introduced by this relatively inflexible method significantly affects the
switching behavior Hardtdegen  _et al._ (2018); Gonzalez  _et al._ (2020), and
can push the operating voltage outside of the practical range.

The circuit design reported in this work represents a new way to characterize
RS devices. It can be used to suppress current overshoots and collect very
large volumes of $I,V$ sweeping characteristics without the requirement of
CMOS integration. We demonstrate collection of $10^{5}$ switching cycles per
second, which is highly useful for studying the stochastic nature of switching
processes.

##  II External current limiting amplifier

###  II.1 Design principles

For the purpose of rapidly testing devices with minimal nano-fabrication
overhead, compatibility with isolated two-terminal structures is necessary and
should be provided by an external Current Limiting Amplifier (CLA) circuit
placed in series with the Device Under Test (DUT) in a setup similar to that
shown in Fig. 3. When the series combination is driven by a voltage waveform,
the circuit should provide a variable current limit in the approximate range
10 $\mu$A$-$1 mA in the forward polarity (SET direction). Because of the self-
limiting nature of the RESET process under voltage control, current should
flow through the circuit unimpeded in the reverse polarity (RESET direction).

DUTAWG$50\Omega$$50\Omega$Oscilloscope$50\Omega$$50\Omega$$50\Omega$ Current
---
Limiting
Amplifier
$\mathrm{V_{out}}$$\mathrm{I_{out}}$$\mathrm{I_{limit}}$$450\Omega$SplitterPC

Figure 3:  Schematic of a measurement setup using the current limiting
amplifier circuit. A two channel arbitrary waveform generator (AWG) applies a
driving signal to the DUT as well as a signal to control the value of the
forward current limit. An oscilloscope measures simultaneous samples of the
voltage at both electrodes, as well as the device current. A jumper connects
the ground planes of the left and right probes to reduce interference and
inductance in the signal path.

To avoid any influence of the circuit on the switching process before the
current limit is reached, the circuit should present a negligible impedance
for all currents below the limit. Only once the DUT current reaches the limit,
the circuit should rapidly transition into a current source behavior to
terminate the runaway switching process. In other words, the circuit should
ideally present a frequency independent $I,V$ characteristic as shown in Fig.
4(a) in series with the device. The circuit should be highly stable for a
variety of loads, and its design should be as simple as possible in order to
easily distinguish the role of the DUT in measurements of the overall
electrical response.

Figure 4:  The current limiting $I,V$ characteristic intended to be placed in
series with the DUT. In the ideal case (a), the differential resistance is
zero below the adjustable current limit (here 200 $\mu$A), and infinite above.
An approximation (b) can be realized using a common-base amplifier with
voltage and current bias.

Crucially, any overshoot above the current limit following a SET transition
should be suppressed as much as possible. Because such overshoots are caused
by the stray capacitance at the terminal of the current limiting circuit, this
capacitance is considered a critical design parameter to be minimized. It is
therefore not an option to connect the CLA to the DUT over a length of coaxial
cable, as this would present an effective capacitance of 100 pF/m. To reduce
this capacitance, the probing circuit needs to be mounted as close as possible
to the DUT, and a short unshielded probe needle should be mounted directly to
its circuit board.

The measurement setup should allow application of voltage signals of at least
1 MHz to the device, and a low-noise current output should have a resolution
below 1 $\mu$A and should be able to register fast rise times of switching
events below 100 ns. The bandwidth of signal application and current
measurement should not depend strongly on the resistance state of the DUT, nor
on the current limit used. External commercial equipment should be used to
generate and sample voltage waveforms, where an important requirement is a
large enough memory capacity to capture hundreds to thousands of $I,V$
datapoints each switching cycle for $10^{5}-10^{6}$ cycles per measurement
shot.

###  II.2 Implementation

The basic idea behind the presented circuit design is to use a single bipolar
junction transistor (BJT) $I,V$ characteristic to implement the desired
current limiting response while also providing transimpedance amplification of
the DUT current. Packaged discrete BJTs for radio frequency applications are
available with very low parasitic capacitance, making them highly suitable
here for use in the input stage. The common-base (CB) amplifier configuration
is of particular interest as a high-bandwidth current buffer, featuring a low
input impedance and small feedback capacitance that does not suffer from the
Miller effect. With voltage and current biasing, a CB amplifier can closely
approximate the targetted current limiting $I,V$ characteristic shown in Fig.
4. A simplified schematic of the input stage used to accomplish this is shown
in Fig. 5.

Input(from
DUT)$I_{d}$$I_{\text{bias}}$$V_{EE}$$I_{E}$V${}_{\text{bias}}$$R_{C}$$I_{C}$$V_{CC}$Output

Figure 5:  A simplified diagram of a circuit implementing unipolar current
limiting and transimpedance amplification. The value of the forward current
limit is set by $I_{\text{bias}}$, and the input voltage is approximately 0 V
for input currents below this limit.

The basic operation of this input stage is straightforward to analyze.
Applying Kirchhoff’s current law at the input node, it can be seen that
whenever the DUT current $I_{d}$ is less than the bias current
$I_{\text{bias}}$, the BJT emitter current $I_{E}$ is positive and transistor
will be in forward-active mode. In this mode, with an appropriate setting of
$V_{\text{bias}}\approx 0.7$ V, the input voltage $V_{\text{in}}$ will be held
close to 0 V due to the high forward transconductance of the BJT. Thus, for
either positive or negative voltages applied to the DUT, the input stage
effectively presents a low impedance to ground as long as
$I_{d}<I_{\text{bias}}$. As $I_{d}$ approaches $I_{\text{bias}}$, the BJT
enters cut-off mode, where its effect in the circuit can be ignored and the
input behaves as a current source with $I_{d}=I_{\text{bias}}$.

Ideally, the voltage bias $V_{\text{bias}}$ should be chosen so that the input
current is zero for an input voltage of zero (such that the curve of Fig. 4
intersects the origin). Considering an approximated Ebers-Moll model of the
BJT, it follows that

$V_{\text{bias}}=-nV_{T}\log\left(\frac{I_{\text{bias}}}{I_{s}}+1\right),$ (1)

where $I_{s}$ is the saturation current of the base-emitter junction,
$V_{T}\approx 26$ mV is the thermal voltage, and $n$ is the diode ideality
factor. The output of this stage then gives an amplified voltage signal
$V_{\text{out}}$ that is linearly related to the input current

$I_{d}=I_{\text{bias}}-\left(\frac{1+\beta}{\beta}\right)\left(\frac{V_{CC}-V_{\text{out}}}{R_{C}}\right),$
(2)

where $\beta$ is the forward common-emitter current gain of the NPN
transistor.

A full circuit diagram expanding on this concept is given in Fig. 6, with a
prototype PCB layout also pictured in Fig. 7. Here, Q1 is the CB amplifier
corresponding to that depicted in Fig. 5, and a nearly ideal voltage
controlled current source is realized by the emitter degenerated cascode
amplifier formed by Q2, Q3, and R2. The dependence of the current limit
$I_{\text{bias}}$ on the control voltage $V_{c}$, which is approximately
linear for $I_{\text{bias}}>100~{}\mu\text{A}$, is calibrated for $V_{c}$
values between $-10~{}\text{V}$ and $-1~{}\text{V}$ by an SMU measurement. The
$V_{c}$ signal is then generated according to interpolation of the calibration
table at the desired $I_{\text{bias}}$ values.

Contact Probe $\mathrm{R_{1}}$
---
$\mathrm{2k\Omega}$
$\mathrm{R_{2}}$
---
$\mathrm{2k\Omega}$
$\mathrm{R_{3}}$
---
$\mathrm{2k\Omega}$
$\mathrm{R_{4}}$
---
$\mathrm{2k\Omega}$
Q1Q2Q3Q4Q5Q6+6V-10V$\mathrm{V_{c}}$$+$$-$OPA277$+$$-$THS3091$\mathrm{R_{9}}$$1.21\mathrm{k}\Omega$
$\mathrm{R_{8}}$
---
$1.21\mathrm{k}\Omega$
$\mathrm{R_{10}}$$50\Omega$$\mathrm{V_{out}}$AD8130$+$$-$REFFB$\mathrm{R_{6}}$$499\Omega$$\mathrm{R_{7}}$$50\Omega$$\mathrm{I_{out}}$$499\Omega$$\mathrm{R_{5}}$

Figure 6:  Full schematic for the current limiting probing circuit. All BJT
devices are ON Semiconductor part no. NSVF5501SKT3G. Transistors Q1-Q3 perform
the current limiting function, with the current limit controlled by the input
signal $V_{c}$. Regulated power supplies providing $\pm$10 V and +6 V are not
shown.

Further circuitry in Fig. 6 is included to null voltage offsets and condition
the output signals for transmission to 50 $\Omega$ oscilloscope inputs. From
Eq. 1, it is seen that the ideal value of $V_{\text{bias}}$ depends slightly
on the value of $I_{\text{bias}}$. Therefore, simply using a constant value of
$V_{\text{bias}}$ would create offset voltages at the input terminal on the
order of $10-100$ mV as $I_{\text{bias}}$ is varied. To automatically
compensate this effect, a reference path $R_{3},Q_{4},Q_{5},Q_{6},R_{4}$
mirrors the components $R_{1},Q_{1},Q_{2},Q_{3},R_{2}$, and is used to
actively zero the input offset for all values of $I_{\text{bias}}$ via OPA277.
This same structure also generates a reference voltage for a differential
measurement performed by AD8130, producing a low-offset output signal
$I_{\text{out}}$ proportional to the input current. A voltage follower
(THS3091) with very low input capacitance (0.1 pF) is also placed directly at
the input node, providing a simultaneous measurement of the DUT voltage drop.

Figure 7:  Photograph of the probing circuit board contacting a prototype RRAM
device. Left and right probes are mounted on independent micropositioners.

##  III  Measurement Results

Current overshoots accompanying sudden negative resistance transitions are
suppressed in our measurement scheme by minimizing the capacitance at the
input node of the CLA. This is done by careful selection of the input
transistors and by avoiding proximity of input traces to the ground plane.
However, the parasitic capacitance cannot be fully eliminated and the
potential to create overshoots inevitably remains. Since overshoot transients
tend to play a critical role in switching behavior in practice, it is
important to characterize and model them.

In general, the time-dependent $I,V$ trajectory of a current overshoot is not
solely a characteristic of the measurement setup, but is determined by the
coupled dynamics of the DUT conductance and the driving circuitry. The
duration and amplitude of the overshoot therefore depends on the type and
history of the RS cell being measured, and is not easily reproducible. To
measure the overshoot characteristic in a standardized way, a test sample
designed to imitate the resistive switching action was constructed using
surface mount components. A mechanical reed relay in series with a 1.2
k$\Omega$ and in parallel with 100 k$\Omega$ was found to be well suited for
this purpose, providing a controllable sub-nanosecond transition between two
discrete resistance levels with negligible parasitic effects.

With the reed switch connected in the position of the DUT and biased by 1 V,
the current transient following a resistance transition was measured with 350
MHz bandwidth (Fig. 8). Close agreement of the transient was found with the
solution of a differential equation describing the charging of the CLA input
node,

$C_{p}\frac{dV_{d}}{dt}=I_{\text{bias}}\left[1-\exp{\left(\frac{V_{d}-V_{a}}{V_{T}}\right)}\right]-\frac{V_{d}}{R_{d}},$
(3)

where $C_{p}=5.7$ pF is the parasitic capacitance at the input, $V_{d}$ is the
DUT voltage drop, $V_{a}$ is the applied voltage, and $R_{d}$ is the DUT
resistance (here assumed a step function in time). Note that $C_{p}$ includes
the self-capacitance of the measured cell, which is approximately 0.5 pF for
the reed relay circuit. This should be taken into consideration in the memory
cell design itself, where thin dielectric layers and large contact pads or
device areas can contribute significantly to the total $C_{p}$, which
intrinsically degrades the overshoot performance. Given the single parameter
$C_{p}$, the simple model of Eq. 3 is expected to accurately characterize the
transient response of the CLA circuit, and should be incorporated with a
physical device model to properly understand the complete picture of the
coupled system during a measurement.

Figure 8:  Current overshoot characterization using a reed relay to abruptly
switch from 100 k$\Omega$ to 1.2 k$\Omega$ at time 1 ns with 1 V applied and
with a current limit of 100 $\mu$A. Under these conditions, the CLA returned
to the current limit in $\sim$20 ns, whereas a commercial SMU produced a more
complex overshoot response lasting several microseconds.

For comparison, the current overshoot transient induced using a modern SMU was
measured under identical conditions. For the first $1~{}\mu$s after the
resistance transition, the transient begins with the discharge of a 1 m
coaxial cable which must be used to connect the instrument. Between
$1-10~{}\mu$s, a proprietary feedback circuit is engaged and produces a long
unpredictable current excursion before undershooting and eventually settling
to the programmed current compliance level. Relative to this, the overshoot
duration is reduced in the CLA measurement by over two orders of magnitude.

To demonstrate the RS cycling operation using the external CLA circuit, we
tested a TaOx-based nano-scaled (100 nm) RRAM device of a design which was
known not to survive repeated switching using a commercial SMU. With the CLA
input connected to the DUT top electrode, the current limit was set to 300
$\mu$A and a triangular voltage signal with period 10 $\mu$s and amplitude 1.5
V was applied to the DUT bottom electrode using a Rigol DG5102 AWG. The
applied voltage and device current were sampled at 1.25 GS/s using a Picoscope
6404D deep-storage oscilloscope. In a single measurement lasting only one
second, $10^{5}$ full $I,V$ loops were successfully collected, each containing
1,564 8-bit $I,V$ samples (Fig. 9). It is furthermore possible to collect
millions of such cycles in a practical amount of time by collating multiple
measurement shots, creating powerful datasets for statistical evaluation of RS
devices.

Figure 9:  A measurement of $10^{5}$ consecutive $I,V$ loops collected in one
second with the CLA circuit using a triangular voltage excitation and 300
$\mu$A current limit. Data is smoothed by a 15 sample moving average, and
every 100th cycle is plotted. To conform to plotting convention, the applied
voltage is defined as the negative of the AWG voltage.

##  IV Conclusion

Resistive switching devices are promising building blocks for future memory
and neuromorphic architectures, with the salient property of large cycle-to-
cycle variability. Conventional lab measurements of these cells commonly
represent very different conditions from integrated systems, and often have
unclear implications for device applications. In particular, current
overshoots during runaway resistance transitions hinder the ability to control
and characterize the switching process. In this work, an external current
limiting amplifier was developed to reduce the overshoot effect and allow for
measurements of full $I,V$ loops at $\sim 10^{6}$ times faster rates than
commercial SMUs. The minimal design with low transistor count is relatively
robust against load-induced instability and has the important advantage that
its response is accurately predictable using a few idealized component models.

## References

  * Wouters, Waser, and Wuttig (2015) D. J. Wouters, R. Waser, and M. Wuttig, Proc. IEEE 103, 1274 (2015).
  * Yu and Chen (2016) S. Yu and P.-Y. Chen, IEEE Solid-State Circuits Mag. 8, 43 (2016).
  * Burr  _et al._ (2017) G. W. Burr, R. M. Shelby, A. Sebastian, S. Kim, S. Kim, S. Sidler, K. Virwani, M. Ishii, P. Narayanan, A. Fumarola, L. L. Sanches, I. Boybat, M. Le Gallo, K. Moon, J. Woo, H. Hwang, and Y. Leblebici, Adv. Phys. X 2, 89 (2017).
  * Sangwan and Hersam (2020) V. K. Sangwan and M. C. Hersam, Nat. Nanotechnol. 15, 517 (2020).
  * Ma  _et al._ (2019) W. Ma, P.-F. Chiu, W. H. Choi, M. Qin, D. Bedau, and M. Lueker-Boden, in  _International Conference on Rebooting Computing_ (IEEE, 2019) pp. 1–9.
  * Ielmini and Waser (2015) D. Ielmini and R. Waser,  _Resistive Switching_ (John Wiley & Sons, 2015).
  * Chen and Lin (2011) A. Chen and M.-R. Lin, in  _International Reliability Physics Symposium_ (IEEE, Monterey, CA, USA, 2011) pp. MY.7.1–MY.7.4.
  * Fantini  _et al._ (2013) A. Fantini, L. Goux, R. Degraeve, D. Wouters, N. Raghavan, G. Kar, A. Belmonte, Y.-Y. Chen, B. Govoreanu, and M. Jurczak, in  _International Memory Workshop_ (IEEE, 2013) pp. 30–33.
  * Torrezan  _et al._ (2011) A. C. Torrezan, J. P. Strachan, G. Medeiros-Ribeiro, and R. S. Williams, Nanotechnology 22, 485203 (2011).
  * Menzel  _et al._ (2019) S. Menzel, M. von Witzleben, V. Havel, and U. Böttger, Faraday Discuss. 213, 197 (2019).
  * von Witzleben  _et al._ (2020) M. von Witzleben, T. Hennen, A. Kindsmüller, S. Menzel, R. Waser, and U. Böttger, J. Appl. Phys. 127, 204501 (2020).
  * Meng  _et al._ (2020) J. Meng, B. Zhao, Q. Xu, J. M. Goodwill, J. A. Bain, and M. Skowronski, J. Appl. Phys. 127, 235107 (2020).
  * Lu  _et al._ (2012) Y. M. Lu, M. Noman, W. Chen, P. A. Salvador, J. A. Bain, and M. Skowronski, J. Phys. D Appl. Phys. 45, 395101 (2012).
  * Tirano  _et al._ (2011) S. Tirano, L. Perniola, J. Buckley, J. Cluzel, V. Jousseaume, C. Muller, D. Deleruyelle, B. De Salvo, and G. Reimbold, Microelectron. Eng. 88, 1129 (2011).
  * Kinoshita  _et al._ (2008) K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y. Sugiyama, Appl. Phys. Lett. 93, 033506 (2008).
  * Ambrogio  _et al._ (2016) S. Ambrogio, V. Milo, Z. Wang, S. Balatti, and D. Ielmini, IEEE Electron Device Lett. 37, 1268 (2016).
  * Nardi  _et al._ (2011) F. Nardi, D. Ielmini, C. Cagli, S. Spiga, M. Fanciulli, L. Goux, and D. Wouters, Solid-State Electron. 58, 42 (2011).
  * Nguyen  _et al._ (2015) C. Nguyen, C. Cagli, E. Vianello, A. Persico, G. Molas, G. Reimbold, Q. Rafhay, and G. Ghibaudo, in  _Integrated Reliability Workshop_ (IEEE, 2015) pp. 17–20.
  * Fantini  _et al._ (2012) A. Fantini, D. J. Wouters, R. Degraeve, L. Goux, L. Pantisano, G. Kar, Y.-Y. Chen, B. Govoreanu, J. A. Kittl, and L. Altimime, in  _International Memory Workshop_ (IEEE, 2012) pp. 1–4.
  * Fan  _et al._ (2015) Y.-S. Fan, L. Zhang, D. Crotti, T. Witters, M. Jurczak, and B. Govoreanu, IEEE Electron Device Lett. 36, 1027 (2015).
  * Hardtdegen  _et al._ (2018) A. Hardtdegen, C. La Torre, F. Cuppers, S. Menzel, R. Waser, and S. Hoffmann-Eifert, IEEE Trans. Electron Devices 65, 3229 (2018).
  * Gonzalez  _et al._ (2020) M. B. Gonzalez, M. Maestro-Izquierdo, F. Jiménez-Molinos, J. B. Roldán, and F. Campabadal, Appl. Phys. Lett. , 6 (2020).


* Drawel et al. [2020] Nagat Drawel, Hongyang Qu, Jamal Bentahar, and Elhadi M. Shakshuki.  Specification and automatic verification of trust-based multi-agent systems.  _Future Gener. Comput. Syst._ , 107:1047–1060, 2020.  doi: 10.1016/j.future.2018.01.040.  URL https://doi.org/10.1016/j.future.2018.01.040.
  * Dreossi et al. [2019] Tommaso Dreossi, Daniel J. Fremont, Shromona Ghosh, Edward Kim, Hadi Ravanbakhsh, Marcell Vazquez-Chanlatte, and Sanjit A. Seshia.  Verifai: A toolkit for the design and analysis of artificial intelligence-based systems, 2019.
  * Gao et al. [2019] Qitong Gao, Davood Hajinezhad, Yan Zhang, Yiannis Kantaros, and Michael M. Zavlanos.  Reduced variance deep reinforcement learning with temporal logic specifications.  In _Proceedings of the 10th ACM/IEEE International Conference on Cyber-Physical Systems_ , ICCPS ’19, pages 237–248, New York, NY, USA, 2019. Association for Computing Machinery.  ISBN 9781450362856.  doi: 10.1145/3302509.3311053.  URL https://doi.org/10.1145/3302509.3311053.
  * Genco and Primiero [2023] Francesco A. Genco and Giuseppe Primiero.  A typed lambda-calculus for establishing trust in probabilistic programs.  _CoRR_ , abs/2302.00958, 2023.  doi: 10.48550/arXiv.2302.00958.  URL https://doi.org/10.48550/arXiv.2302.00958.
  * Ghilezan et al. [2018] Silvia Ghilezan, Jelena Ivetić, Simona Kašterović, Zoran Ognjanović, and Nenad Savić.  Probabilistic reasoning about simply typed lambda terms.  In _International Symposium on Logical Foundations of Computer Science_ , pages 170–189. Springer, 2018.
  * Harrison [2003] J. Harrison.  Formal verification at intel.  In _18th Annual IEEE Symposium of Logic in Computer Science, 2003_ , pages 45–54, 2003.  doi: 10.1109/LICS.2003.1210044.
  * Herzig et al. [2010] Andreas Herzig, Emiliano Lorini, Jomi Fred Hübner, and Laurent Vercouter.  A logic of trust and reputation.  _Log. J. IGPL_ , 18(1):214–244, 2010.  doi: 10.1093/jigpal/jzp077.  URL https://doi.org/10.1093/jigpal/jzp077.
  * Kwiatkowska et al. [2002] Marta Z. Kwiatkowska, Gethin Norman, and David Parker.  Prism: Probabilistic symbolic model checker.  In _Proceedings of the 12th International Conference on Computer Performance Evaluation, Modelling Techniques and Tools_ , TOOLS ’02, pages 200–204, Berlin, Heidelberg, 2002. Springer-Verlag.  ISBN 3540435395.
  * Liau [2003] Churn-Jung Liau.  Belief, information acquisition, and trust in multi-agent systems–a modal logic formulation.  _Artif. Intell._ , 149(1):31–60, 2003.  doi: 10.1016/S0004-3702(03)00063-8.  URL https://doi.org/10.1016/S0004-3702(03)00063-8.
  * Liu and Lorini [2017] Fenrong Liu and Emiliano Lorini.  Reasoning about belief, evidence and trust in a multi-agent setting.  In Bo An, Ana L. C. Bazzan, João Leite, Serena Villata, and Leendert W. N. van der Torre, editors, _PRIMA 2017: Principles and Practice of Multi-Agent Systems - 20th International Conference, Nice, France, October 30 - November 3, 2017, Proceedings_ , volume 10621 of _Lecture Notes in Computer Science_ , pages 71–89. Springer, 2017.  ISBN 978-3-319-69130-5.  doi: 10.1007/978-3-319-69131-2\\_5.  URL https://doi.org/10.1007/978-3-319-69131-2\\_5.
  * Primiero [2020] Giuseppe Primiero.  A logic of negative trust.  _J. Appl. Non Class. Logics_ , 30(3):193–222, 2020.  doi: 10.1080/11663081.2020.1789404.  URL https://doi.org/10.1080/11663081.2020.1789404.
  * Primiero and Boender [2017] Giuseppe Primiero and Jaap Boender.  Managing software uninstall with negative trust.  In Jan-Philipp Steghöfer and Babak Esfandiari, editors, _Trust Management XI - 11th IFIP WG 11.11 International Conference, IFIPTM 2017, Gothenburg, Sweden, June 12-16, 2017, Proceedings_ , volume 505 of _IFIP Advances in Information and Communication Technology_ , pages 79–93. Springer, 2017.  ISBN 978-3-319-59170-4.  doi: 10.1007/978-3-319-59171-1\\_7.  URL https://doi.org/10.1007/978-3-319-59171-1\\_7.
  * Primiero and Boender [2018] Giuseppe Primiero and Jaap Boender.  Negative trust for conflict resolution in software management.  _Web Intell._ , 16(4):251–271, 2018.  doi: 10.3233/WEB-180393.  URL https://doi.org/10.3233/WEB-180393.
  * Primiero and D’Asaro [2022] Giuseppe Primiero and Fabio Aurelio D’Asaro.  Proof-checking bias in labeling methods.  In Guido Boella, Fabio Aurelio D’Asaro, Abeer Dyoub, and Giuseppe Primiero, editors, _Proceedings of 1st Workshop on Bias, Ethical AI, Explainability and the Role of Logic and Logic Programming (BEWARE 2022) co-located with the 21th International Conference of the Italian Association for Artificial Intelligence (AI*IA 2022), Udine, Italy, December 2, 2022_ , volume 3319 of _CEUR Workshop Proceedings_ , pages 9–19. CEUR-WS.org, 2022\.  URL https://ceur-ws.org/Vol-3319/paper1.pdf.
  * Primiero et al. [2017] Giuseppe Primiero, Franco Raimondi, Taolue Chen, and Rajagopal Nagarajan.  A proof-theoretic trust and reputation model for VANET.  In _2017 IEEE European Symposium on Security and Privacy Workshops, EuroS &P Workshops 2017, Paris, France, April 26-28, 2017_, pages 146–152. IEEE, 2017.  ISBN 978-1-5386-2244-5.  doi: 10.1109/EuroSPW.2017.64.  URL https://doi.org/10.1109/EuroSPW.2017.64.
  * Seshia et al. [2018] Sanjit A. Seshia, Ankush Desai, Tommaso Dreossi, Daniel J. Fremont, Shromona Ghosh, Edward Kim, Sumukh Shivakumar, Marcell Vazquez-Chanlatte, and Xiangyu Yue.  Formal specification for deep neural networks.  In Shuvendu K. Lahiri and Chao Wang, editors, _Automated Technology for Verification and Analysis_ , pages 20–34, Cham, 2018. Springer International Publishing.
  * Singh [2011] Munindar P. Singh.  Trust as dependence: a logical approach.  In Liz Sonenberg, Peter Stone, Kagan Tumer, and Pinar Yolum, editors, _10th International Conference on Autonomous Agents and Multiagent Systems (AAMAS 2011), Taipei, Taiwan, May 2-6, 2011, Volume 1-3_ , pages 863–870. IFAAMAS, 2011.  ISBN 978-0-9826571-5-7.  URL http://portal.acm.org/citation.cfm?id=2031741\&CFID=54178199\&CFTOKEN=61392764.
  * Termine et al. [2021a] Alberto Termine, Alessandro Antonucci, Giuseppe Primiero, and Alessandro Facchini.  Logic and model checking by imprecise probabilistic interpreted systems.  In Ariel Rosenfeld and Nimrod Talmon, editors, _Multi-Agent Systems - 18th European Conference, EUMAS 2021, Virtual Event, June 28-29, 2021, Revised Selected Papers_ , volume 12802 of _Lecture Notes in Computer Science_ , pages 211–227. Springer, 2021a.  ISBN 978-3-030-82253-8.  doi: 10.1007/978-3-030-82254-5\\_13.  URL https://doi.org/10.1007/978-3-030-82254-5\\_13.
  * Termine et al. [2021b] Alberto Termine, Giuseppe Primiero, and Fabio Aurelio D’Asaro.  Modelling accuracy and trustworthiness of explaining agents.  In Sujata Ghosh and Thomas Icard, editors, _Logic, Rationality, and Interaction - 8th International Workshop, LORI 2021, Xi’ian, China, October 16-18, 2021, Proceedings_ , volume 13039 of _Lecture Notes in Computer Science_ , pages 232–245. Springer, 2021b.  ISBN 978-3-030-88707-0.  doi: 10.1007/978-3-030-88708-7\\_19.  URL https://doi.org/10.1007/978-3-030-88708-7\\_19.
  * Urban and Minè [2021] Caterina Urban and Antoine Minè.  A review of formal methods applied to machine learning, 2021.
  * Warrell [2016] Jonathan H. Warrell.  A probabilistic dependent type system based on non-deterministic beta reduction.  _CoRR_ , abs/1602.06420, 2016.  URL http://arxiv.org/abs/1602.06420.
  * Wing [2021] Jeannette M. Wing.  Trustworthy ai.  _Commun. ACM_ , 64(10):64–71, sep 2021.  ISSN 0001-0782.  doi: 10.1145/3448248.  URL https://doi.org/10.1145/3448248.