Impact of $R$ and $C$ on Power Consumption To better understand the nuances of
the evaluation results, we first build the intuition about how different
photonic unit sizes affect power consumption. In this regard, we summarize the
changes in power consumption for different components of the microarchitecture
when we double the number of rows (i.e., design a tall photonic unit) vs. the
number of columns (design a wide photonic unit). In both cases, the latency is
halved, but due to the interplay of different power components, especially the
MZMs and the lasers, one design gets better than the other in terms of energy
efficiency.

Table : Impact of $R$ and $C$ on the power consumption. Component | 2$\times$ Increase in R | 2$\times$ Increase in C
---|---|---
MZMs | 1$\times$ | 2$\times$
Lasers | 2$\times$ | 2$\times$
SRAM arrays | 2$\times$ | 2$\times$
DACs for MZMs | 1$\times$ | 2$\times$
DACs for PDs | 2$\times$ | 2$\times$
ADCs (training) | 1$\times$ | 1$\times$
ADCs (inference) | 2$\times$ | 1$\times$

##  Impact of $t_{DAC}$ on Area and EDP

[t]0.24 [width=]figures/delay_train.png [t]0.24 [width=]figures/delay_inf.png

Figure : Average EDP and the corresponding area for different extra DAC delays
on a 128$\times$128 core running at 5 GHz in the encoding scheme. A small
increase in EDP with a forced DAC delay can drastically decrease area,
especially for training.

We begin with an evaluation of the sensitivity of EDP and area to the extra
delay we introduce in the DAC for encoding. To demonstrate the benefit of this
delay, we plot the EDP and area (see Figure ) for different delay amounts for
with a 128$\times$128 photonic unit running at 5 GHz as an example. On the
left side, we can see that even a small delay of 1 ns can reduce the area by
$\approx$80% with $<$1% increase in EDP. The change in EDP with the increase
in $t_{DAC}$ is minimal because we switch a tile after every D ($\approx
10^{3}$) cycles during training, and the 1 ns delay, i.e., 5 cycles, is
insignificant compared to that. However, within these 5 cycles, one DAC can
control 5$\times$ more PDs than before. As a result, we need less number of
DACs and can achieve a significant area reduction. For inference too, applying
$t_{DAC}$ helps reduce area without compromising too much on EDP, although to
a lesser extent than for training. This is because tile switching occurs more
frequently during inference than training. Additionally, we perform both
encoding and similarity checking in the same photonic core, resulting in the
delay affecting both stages. Despite this, the area reduction is substantial
and contributes to efficient resource utilization.

##  Energy-Delay-Area Product (EDAP)-optimized design

We explore the design space for each encoding scheme with an exhaustive search
and find the architectural parameters that minimize the average EDAP over all
the datasets that we have considered. We list the parameters and their power
and performance in Table . We use these parameters for power and area
breakdown analysis in the later subsections. In general, we derive the
following key insights based on the choice of the design parameters: First,
having a tall photonic unit is more energy-efficient than a wide one. This is
because, for a column of PDs, the MZM power is higher than the power in the
laser source that drives the PDs. More details about this tradeoff are
provided in the next subsection. Second, For record-based encoding (same as
graph encoding) a smaller photonic unit is preferred than that for encoding.
Record-based encoding is power-hungry due to frequent tile switching.
Therefore, having a small PD array, which requires less data loading per
cycle, lowers power. Third, running at the maximum frequency is a priority for
getting the maximum benefit from a photonic unit. In our design, 5 GHz is the
highest possible frequency because our chosen ADC operates at 5 GS/s. Unless
bounded by a low power constraint or a bottleneck element that restricts the
operating frequency, the best frequency choice would be the highest one. In
all the chosen designs, the operating frequency is 5 GHz.

##  Power Breakdown of

Table : Latency and power for the parameters (, number of photonic units, $f$, $t_{DAC}$) that minimize EDAP for training and inference under 20 W power and 500 $mm^{2}$ area. 3*  | Enc.
---
type
3*Datasets | Training | Inference (1 million)
|  |  2*Params |  2*  | Latency
---
(ms)
2*  | Power
---
(W)
2*Params |  2*  | Latency
---
(ms)
2*  | Power
---
(W)
5*[origin=c]90Traditional | ISOLET |  5*  | 128$\times$76,
---
4 units,
5 GHz,
1 ns
0.09 | 4.8 |  5*  | 128$\times$128,
---
4 units
5 GHz
1 ns
8.71 | 10.3
| UCIHAR |  | 0.08 | 4.84 |  | 8.54 | 10.12
| FACE |  | 6.7 | 4.94 |  | 8.41 | 10.34
| PAMAP |  | 0.98 | 4.92 |  | 1.8 | 9.32
| PECAN |  | 0.18 | 4.7 |  | 5.1 | 9.97
5*[origin=c]90Record | ISOLET |  5*  | 128$\times$12
---
3 units
5 GHz
0.7 | 19.41 |  5*  | 108$\times$12
---
3 units,
5 GHz
122.45 | 18.4
| UCIHAR |  | 0.63 | 19.45 |  | 110.04 | 18.61
| FACE |  | 56.85 | 19.6 |  | 117.94 | 18.81
| PAMAP |  | 9.13 | 17.66 |  | 20.69 | 13.5
| PECAN |  | 1.24 | 19.64 |  | 59.44 | 19.13
3*[origin=c]90Graph | DD |  3*  | 108$\times$12,
---
3 units,
5 GHz
0.07 | 16.42 |  3*  | 96$\times$48,
---
1 unit,
5 GHz
52.14 | 19.86
| ENZYMES |  | 0.005 | 14.28 |  | 9.85 | 12.52
| PROTEINS |  | 0.01 | 13.16 |  | 9.14 | 16.08

In Figure , we show the power breakdown for training and inference with
different encoding schemes. We choose the design parameters listed in Table
for each plot. We show the breakdowns for the dataset ISOLET in and record-
based encoding and DD for graph encoding. The breakdown trends are similar in
other datasets with small variations. MZM tuning is the dominant power-
consuming source for encoding contributing more than 50% of the total power
consumption. Usually, in the electro-photonic accelerators, we find that the
ADCs and the lasers are the primary power consumers. However, both the laser
power and ADCs contribute little to our design. The laser power is low due to
the low SNR requirement for HDC and fewer losses in the optical path in our
design. The ADCs for both training and inference have a low bit precision and
in training, we only use one ADC per photonic unit for our efficient bundling
strategy. Therefore, the MZM tuning power becomes the bottleneck in the
design. SRAM data movement is also another major power-consuming source,
contributing $\approx$23% to the total power consumption. For inference with
encoding, we need to use adders and TIAs of all the rows, so they contribute a
good percentage to the power consumption as well. In record-based encoding,
the tile switching in every cycle results in the SRAM power consumption being
dominant. The second-most power-consuming source is the MZM tuning circuit,
and the other contributions are minimal. We find the same trends for graph
encoding as well because it follows the same procedure as record-based
encoding.

##  Area Breakdown of

[width=0.5]figures/pow_donut_trial.pdf

Figure : Power breakdown of HDC training and inference for different encoding
schemes. The design parameters minimize average EDAP and are listed in Table .

[width=0.45]figures/donut_area_2.pdf

Figure : Area breakdown of HDC training and inference with . The design
parameters are from Table .

In Figure , we show the area breakdown of training and inference with encoding
with the architecture parameters (see Table ) that minimize EDAP for ISOLET.
The breakdown trends are similar in other datasets and other encoding schemes
with small variations caused by the size of the SRAM. The dominant area
bottleneck for both training and inference is the DACs. Each DAC consumes
significantly more area than a PD and the DACs account for $\approx$83-87%
area of the chip. For inference, every row of a photonic unit uses an ADC,
whereas in training only one ADC is used per photonic unit. Consequently, ADC
contribution constitutes $\approx$7% of the area in inference but is
negligible in training. The other contributors are MZMs and adders (and ADCs
for training), consuming $\approx$2% of the area. If one wants a single design
that supports both training and inference, then one will need to use the
design parameters for inference from Table .

##  Iso-area and Iso-power Analysis

[t]0.24 [width=]figures/budget_pow_train.png [t]0.24
[width=]figures/budget_pow_inf.png

Figure : Best average EDP (normalized) for different encoding schemes for
different power budgets. The area budget is 500 $mm^{2}$. The EDP for encoding
with no extra DAC delay saturates quickly. The EDP for record-based encoding
and encoding with extra DAC delay saturate slower.

[t]0.24 [width=]figures/budget_area_train.png [t]0.24
[width=]figures/budget_area_inf.png

Figure : Best average EDP (normalized) for different encoding schemes for
different area budgets. The power budget is fixed at 20 W. Record-based
encoding saturates faster than encoding.

In this section, for each encoding scheme, we perform an exhaustive search to
find the design configuration that minimizes the average EDP over the datasets
for different resource (power/area) budgets. We first plot the normalized
average EDP for different power budgets with a fixed 500 $mm^{2}$ area
constraint in Figure . We can observe that the EDP for record-based encoding
saturates slowly, meaning that with this encoding and the associated dataflow,
the accelerator can leverage the increasing power budget. This is because the
record-based encoding is power-hungry due to frequent data loading from the
SRAM and so it needs to run on smaller photonic units to save power when the
power budget is low. Allocating a higher power budget allows for larger
photonic units and faster execution for both training and inference, resulting
in a slow saturation rate. On the other hand, the EDP for encoding with no
delays saturates quickly because it consumes a large area even at low power
consumption due to the huge number of DACs being inactive most of the time.
Allowing the extra delay in encoding helps to slow down saturation by allowing
for expansion in the computing resources (PDs and MZMs) while reducing the
number of DACs. In Figure , we plot the normalized EDP for different area
budgets with a fixed 20 W power constraint. Here, record-based encoding
saturates faster because its power consumption uses up the available power
budget even for smaller designs i.e. low area. However, for encoding, the
increased area is utilized without crossing the power constraint. The extra
DAC delay does not make any difference in this case because we are not limited
by area. The key takeaway from our analysis is that record-based encoding is
power-hungry, so having a higher power budget is beneficial for it. For
encoding, the bottleneck is the area. Therefore, a larger area is beneficial
for achieving better energy efficiency.

##  Comparison with SOTA Electro-Photonic DNN Accelerator

Table : Comparison of SOTA electro-photonic accelerators: ADEPT (AD)
[cansu2021electro], DEAP-CNN (DC) [deap-cnn], and ALBIREO (AL)
[shiflett2021albireo] with (PH) for HDC training (top) and inference (bottom)
using one million samples with encoding. Training
---
2*Datasets | Latency (ms) | Power (W) | EDP (Js) | Efficiency (Sample/s/W/$mm^{2}$)
| AD | DC | AL | PH | AD | DC | AL | PH | AD | DC | AL | PH | AD | DC | AL | PH
ISOLET | 0.28 | 2.56 | 4.36 | 0.09 | 13.67 | 100 | 60 | 4.8 | 1.04E-06 | 6.53E-04 | 1.14E-03 | 3.98E-08 | 1.07E+04 | 5.90E+03 | 2.05E+02 | 6.43E+04
UCIHAR | 0.28 | 2.54 | 3.97 | 0.08 | 13.33 | 100 | 60 | 4.84 | 1.01E-06 | 6.48E-04 | 9.44E-04 | 3.13E-08 | 1.10E+04 | 5.90E+03 | 2.24E+02 | 7.19E+04
FACE | 22.30 | 213.99 | 365.29 | 6.70 | 13.58 | 100 | 60 | 4.94 | 6.75E-03 | 4.58E+00 | 8.01E+00 | 2.21E-04 | 1.12E+04 | 5.90E+03 | 2.05E+02 | 7.11E+04
PAMAP | 16.73 | 250.32 | 55.74 | 0.98 | 5.31 | 100 | 60 | 4.92 | 1.49E-03 | 6.27E+00 | 1.86E-01 | 4.72E-06 | 4.46E+04 | 5.90E+03 | 1.57E+03 | 5.71E+05
PECAN | 0.62 | 9.13 | 8.13 | 0.18 | 12.27 | 100 | 60 | 4.7 | 4.65E-06 | 8.34E-03 | 3.97E-03 | 1.52E-07 | 1.91E+04 | 5.90E+03 | 3.92E+02 | 1.19E+05
Inference
Datasets | Latency (ms) | Power (W) | EDP (Js) | Efficiency (Sample/s/W/$mm^{2}$)
| AD | DC | AL | PH | AD | DC | AL | PH | AD | DC | AL | PH | AD | DC | AL | PH
ISOLET | 42.68 | 409.60 | 699.20 | 8.71 | 15.98 | 200 | 120 | 10.3 | 2.91E-02 | 3.36E+01 | 5.87E+01 | 7.82E-04 | 4.75E+03 | 1.47E+03 | 5.12E+01 | 2.75E+04
UCIHAR | 42.68 | 409.60 | 638.40 | 8.54 | 15.57 | 200 | 120 | 10.12 | 2.84E-02 | 3.36E+01 | 4.89E+01 | 7.38E-04 | 4.88E+03 | 1.47E+03 | 5.60E+01 | 2.86E+04
FACE | 42.68 | 409.60 | 699.20 | 8.41 | 15.76 | 200 | 120 | 10.34 | 2.87E-02 | 3.36E+01 | 5.87E+01 | 7.32E-04 | 4.82E+03 | 1.47E+03 | 5.12E+01 | 2.84E+04
PAMAP | 8.54 | 409.60 | 91.20 | 1.80 | 19.81 | 200 | 120 | 9.32 | 1.44E-03 | 3.36E+01 | 9.98E-01 | 3.02E-05 | 1.92E+04 | 1.47E+03 | 3.92E+02 | 1.47E+05
PECAN | 25.61 | 409.60 | 364.80 | 5.10 | 16.16 | 200 | 120 | 9.97 | 1.06E-02 | 3.36E+01 | 1.60E+01 | 2.59E-04 | 7.83E+03 | 1.47E+03 | 9.80E+01 | 4.85E+04

Table  shows a detailed comparison of the three SOTA electro-photonic DNN
accelerators and for performing HDC training and inference with encoding. We
do not compare the record-based encoding for the SOTA accelerators, as they
are all inefficient for this encoding scheme. We use the architectural
configurations prescribed in the corresponding papers of the SOTA
accelerators. For , we use the parameters mentioned in Table  that minimize
EDAP. For calculating area efficiency, we use the area of the active computing
elements and the data converters for all accelerators for a fair comparison.
For all datasets, we observe that achieves lower latency and lower power than
other accelerators for both training and inference. ADEPT shows the closest
performance to for training and inference, but it still has 3-4$\times$ higher
latency. The power consumption is also higher in ADEPT than , primarily due to
the substantial laser power that supports the long chain of MZIs in its
photonic core, and the higher bit-precision of the the ADCs and DACs. DEAP-CNN
is efficient in training if the data fits efficiently into its banks. However,
because the MRRs introduce crosstalk and the tuning circuits are costly, it is
challenging to design large MRR banks. The total number of computing elements
(MRRs) in DEAP-CNN is much smaller than ADEPT (MZIs) and (PDs), even though it
consumes the highest power. As a result, the latency of DEAP-CNN is at least
one order of magnitude higher than . ALBIREO has the highest latency among all
accelerators because it is highly optimized for CNNs and is not suitable for
hyperdimensional computing. Overall, on average, for training achieves three
orders of magnitude lower EDP and one order of magnitude better efficiency
(throughput/power/area) than the SOTA electro-photonic accelerators. In
inference too, achieves at least two orders of magnitude lower EDP and one
order of magnitude better efficiency than the SOTA electro-photonic
accelerators. It should be noted that the efficiency improvement of over ADEPT
is better for inference than training. This is because, in inference, the CHV
matrix shape is narrow ($K\times D$), and a square 128$\times$128 MZI array of
ADEPT wastes a lot of area when mapping the CHV matrix. Having the flexibility
on the shape of the photonic unit is a key advantage for to be more suitable
for HDC than a square MZI-array-based accelerator, especially for inference.

##  Comparison with CiM-based Accelerator

Table : Comparison between CiM-based accelerator and (PH) when performing
training and inference. Training
---
2*Dataset | Training time (ms) |  2*  | $\times$
---
Speed-up
Power (W) |  2*  | Power ratio
---
(EP/CiM)
| PH | CiM |  | PH | CiM |
ISOLET | 0.09 | 94.76 | 1.05E+03 | 5.32 | 9.40E-03 | 5.66E+02
UCIHAR | 0.08 | 92.64 | 1.16E+03 | 5.36 | 9.40E-03 | 5.70E+02
FACE | 6.7 | 6892.52 | 1.03E+03 | 5.49 | 9.40E-03 | 5.84E+02
Inference
2*Dataset | Throughput (inf/s) |  2*  | $\times$
---
Speed-up
Power (W) |  2*  | Power ratio
---
(PH/CiM)
| PH | CiM |  | PH | CiM |
ISOLET | 1.15E+08 | 7.56E+04 | 1.52E+03 | 11.50 | 1.24E-02 | 9.27E+02
UCIHAR | 1.17E+08 | 7.74E+04 | 1.51E+03 | 11.29 | 1.25E-02 | 9.03E+02
FACE | 1.19E+08 | 7.59E+04 | 1.57E+03 | 11.56 | 1.25E-02 | 9.25E+02

Table  shows the comparison between and CiM for training and inference for
encoding. As Neurosim 2.1 doesn’t support bit-precision of less than 5 bits
for training, we set the bit-precision to 5 for both CiM and . The
hyperdimension remains the same at 4096. Similar to our previous experiments,
we choose the configuration that minimizes the EDAP for . Primarily, due to
the fast and energy-efficient multi-bit analog computing capability of
photonics, achieves three orders of magnitude speedup over CiM-based
accelerator. In the CiM approach, multi-bit MVM operations in the ReRAM arrays
make the encoding process slow. On top of that, due to the lack of an
efficient batch processing mechanism [lu2021neurosim], the CiM-based
accelerator experiences a high latency when handling a batch of samples. Also,
the long update times of the CHVs in the ReRAM make the bundling step time-
consuming. That is why, even though the CiM-based accelerator consumes very
low power for both training and inference, the high speed-up in leads to four
orders of magnitude better energy efficiency for .