# High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network

Pranav O. Mathews, , Christian B. Duffee, , Abel Thayil,
Ty E. Stovall, Christopher H. Bennett, , Felipe Garcia-Sanchez, ,
Matthew J. Marinella, , Jean Anne C. Incorvia, , Naimul Hassan, , Xuan Hu, ,
Joseph S. Friedman Manuscript submitted XXXX XX, 2021. This research is
sponsored in part by the National Science Foundation under CCF award 1910800
and the Texas Analog Center of Excellence undergraduate internship program.
(Pranav O. Mathews, Christian B. Duffee, and Abel Thayil contributed equally
to this work)(Corresponding author: Xuan Hu)P. O. Mathews, C. B. Duffee, T. E.
Stovall, N. Hassan, X. Hu, and J. S. Friedman are with the Department of
Electrical and Computer Engineering, The University of Texas at Dallas,
Richardson, TX 75080 USA (email: joseph.friedman@utdallas.edu).A. Thayil is
with the Laboratoire de Physique de la Matière Condensée, Ecole Polytechnique,
CNRS, IP Paris, Palaiseau 91128, FranceC. Bennett, M. Marinella are with
Sandia National Laboratories, Albuquerque, NM 87185-1084 USAF. Garcia-Sahnchez
is with Universidad de Salamanca, Departamento de Física Aplicada, Salamanca,
37008, Spain J. A. C. Incorvia is with the Department of Electrical and
Computer Engineering, The University of Texas at Austin, Austin, TX 78712 USA

###### Abstract

Neuromorphic computing systems overcome the limitations of traditional von
Neumann computing architectures. These computing systems can be further
improved upon by using emerging technologies that are more efficient than CMOS
for neural computation. Recent research has demonstrated memristors and
spintronic devices in various neural network designs boost efficiency and
speed. This paper presents a biologically inspired fully spintronic neuron
used in a fully spintronic Hopfield RNN. The network is used to solve tasks,
and the results are compared against those of current Hopfield neuromorphic
architectures which use emerging technologies.

###### Index Terms:

DW-MTJ (four terminal-magnetic tunnel junction), hopfield network,
neuromorphic computing, recurrent networks, spintronics.

##  I Introduction

Recurrent neural networks (RNN) are powerful software architectures that solve
complex tasks beyond everyday computing. These unique problem-solving
capabilities have led to widespread use in areas such as image recognition,
classification, and artificial intelligence, to name a few. However, the size
of today’s problems limits the further use of neural networks; as data sets
become larger, the cost to run and train them increases to unpractical levels
[1, 2].

An answer to these issues is to redesign networks using physical, analog
circuits instead of the current software models. Inspiration can be drawn from
the brain, as it is an example of an analog machine that efficiently solves
the problems that our current networks struggle with while consuming little
power and space [3]. Research shows the brain accomplishes this through a
diverse system of neurons woven together in a complex web of specialized bio-
circuitry that cascades together to solve tasks [3]. By emulating neuronal
behavior and cytoarchitectonics, efficient designs can be created that bolster
the capabilities of neural networks.

Neuron-like elements can be designed using spintronic technology, which
utilizes a combination of magnetic spin and electrical current to store and
transmit information [4, 5]. Spintronic devices have been exploited for
various neural network designs due to their non-volatility, device size, and
compatibility with CMOS technology [6, 7, 8, 9, 10]. By building upon these
physical qualities and current neuromorphic spintronic designs, it is possible
to create complete hardware neural networks.

Current neuromorphic designs draw from conventional CMOS technology and
emerging devices such as spintronics. Basic RNNs have been created using
hybrid memristor-CMOS technology, and fully spintronic reservoir computers
have been designed [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23].
However, the hybrid systems still utilize a significant amount of inefficient
CMOS, lowering the benefits of using emerging devices. The spintronic
reservoir sidesteps this issue but is unable to tune its weights to solve
different problems or create different architectures. A recent proposal of a
SONOS based Hopfield network [24] fixes both issues, using only emerging
devices and having flexible weights, but the technology used is slower and
slightly less energy efficient than spintronics.

This paper proposes a novel RNN neuron based on the domain wall-magnetic
tunnel junction (DW-MTJ) that is efficient and flexible; it is composed solely
of spintronic devices and allows trained weights to be written into the system
as needed. Section II provides background details on neural networks and
spintronic technology. In section III, the neuron structure is explained,
showing how spintronic devices are cascaded together to achieve a flexible
neuron and how to connect these neurons to create an RNN. Simulation results
are then shown in section IV, detailing accuracy, power, and speed. Finally,
section V contains concluding thoughts.

##  II Background

Hardware neural networks must be able to both store the state of a network and
perform calculations based on various input. Because of their non-volatility,
spintronic devices such as the domain wall (DW) and magnetic tunnel junction
(MTJ) are ideal candidates for storing states. These states can be changed
through an input current, allowing these devices to perform computations. Both
of these properties lend themselves well to emulating recurrent neural
networks, which have a fixed set of neurons that update over time towards a
final state.

###  II-A Recurrent Neural Networks

RNNs are a type of neural network architecture that retains a state which
evolves over time in response to varying inputs [25]. These architectures are
commonly used to solve tasks involving classification of spatial data or
temporally related data; however, they suffer from high computational costs,
especially as the number of nodes increases [26]. While actually consisting of
a set number of interconnected neurons, the evolution of the network’s state
can be visualized as a directed graph of arbitrary length, with one time step
separating each layer in the graph.

The earliest example of an RNN is the Hopfield network [27], shown in Fig. 1.
Hopfield networks can store and remember patterns by functioning as
associative memory, an important type of neural computation [28]. However,
because the network size directly scales with the data [26] and the network is
fully connected, calculating the updates through time requires a lot of
energy, meaning they are also costly to run for large data sets.

Figure 1: Illustration of Hopfield network structure. Each triangle represents
the interconnected neurons, and the dashed lines illustrate how the network
steps over time, eventually converging to a final state.

A Hopfield network can be represented as a fully connected graph of neurons,
where each neuron has an excitation state ($S_{i}$): on (one) or off (zero).
Each neuron also sends an output ($O_{ij}$) to every other neuron in the
network based on its current state and the synaptic weight ($W_{ij}$) between
the pair of neurons

$O_{ij}=S_{i}\times W_{ij}.$ (1)

As the network runs forward in time, each neuron’s state is updated according
to a threshold function based off its inputs according to the following
expressions:

$S_{i}=\begin{cases}1\text{ if }\sum_{j=0}^{N-1}O_{ji}>T\\\ S_{i}\text{ if
}\sum_{j=0}^{N-1}O_{ji}=T.\\\ 0\text{ otherwise}\end{cases}$ (2)

The network can be trained to remember a certain pattern by updating the
weights using the following equation:

$W_{ij}=(2S^{{}^{\prime}}_{i}-1)(2S^{{}^{\prime}}_{j}-1),$ (3)

where $S^{{}^{\prime}}_{i}$ is the stored state of neuron $i$, resulting in
$W_{ij}=\pm 1.$

###  II-B Neuromorphic Computing

Standard von Neumann computer architectures are not designed for the
computational requirements of neural networks. To alleviate this issue,
neuromorphic computing has emerged as an alternative way to run these
networks. By creating specialized architectures for different networks,
neuromorphic designs can offer improvements in metrics such as power, speed,
and scalability [29].

Regardless of these advancements, the inefficiency of CMOS in neuromorphic
computing remains a problem. Emerging technologies such as spintronics and
memristors are being explored as alternatives and have been shown to run
efficiently while meeting standard benchmarks in accuracy, power, and speed.
For example, reservoir computers have been designed using spintronics devices,
and memristors combined with CMOS have formed many basic RNNs [11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23].

These current systems can be improved. The spintronic reservoir computer uses
solely emerging technologies [11, 12, 13, 14], but the weights are fixed
causing the network to lack flexibility. On the other hand, the memristor RNNs
[15, 16, 17, 18, 19, 20, 21, 22, 23] compute using solely emerging technology,
but the CMOS overhead slows the system down. An architecture that integrates
both the flexibility of memristor RNNs and the low energy consumption of
emerging technology has been recently proposed [24], but improvements can
still be made in speed and efficiency through the use of different emerging
technologies.

Figure 2: Four terminal DW-MTJ with physical structure labeled. Input current
goes from DWIN to DWOUT , and output current flows from MTJIN to MTJOUT. MTJ
resistance depends on the relative orientation of its two magnets, and the
lower magnet is coupled to the DW track directly beneath it. An input current
can cause the DW to move, changing both the track and magnets’ orientation and
triggering a change in MTJ resistance, therefore changing its output.

###  II-C Four Terminal DW-MTJ

The DW-MTJ is a spintronic device that has been used to implement neuronal and
synaptic functions, offering increases in efficiency and the ability to
cascade into full networks [8, 9, 10, 30, 31]. A DW-MTJ is composed of two
separate spintronic devices: the MTJ and DW.

An MTJ consists of two ferromagnets stacked on top of one another, separated
by a tunnel barrier. The probability of electrons tunneling through the
barrier is determined by the magnets’ orientations. When the two magnets are
oriented in the same direction (parallel), the resistance presented by the MTJ
is less than if the orientation is in the opposite direction (anti-parallel).

A DW lies within a ferromagnetic track between two opposite magnetic
orientations. An externally applied magnetic field, or a current through the
bottom heavy metal layer, can move the DW through the track [30], which also
affects the area of the track under each magnetic orientation. The DW motion
linearly increases with input current, and boundaries are placed at the
track’s edges to stop this motion from carrying a DW off the side.

A four terminal DW-MTJ is composed of a MTJ stacked atop a DW track separated
by an insulating layer, as shown in Fig. 2 [31]. This layer ensures the input
DW current is decoupled from the output MTJ current. The top magnet of the MTJ
is fixed, while the bottom magnet is free and coupled to the magnetization of
the domain wall track directly below it. Pushing the DW past the MTJ through
some external force causes the magnetization of the track directly underneath
the MTJ to change. This, in turn, changes the coupled bottom MTJ ferromagnet,
leading to a switch in MTJ orientation and subsequent change in resistance
between $MTJ_{IN}$ and $MTJ_{OUT}$.

##  III Spintronic Recurrent Network

This paper proposes a functioning recurrent neuron that is made of several
cascaded DW-MTJs, taking advantage of their ability to replicate neuronal and
synaptic functions [8, 9, 10, 30, 31]. Recurrent networks can be built by
interconnecting these neurons, allowing for a fully spintronic RNN that
naturally behaves more efficiently than CMOS because of the neural properties
shown in the DW-MTJs. To illustrate this, we created a Hopfield network with
an all-to-all connection scheme using the proposed recurrent neuron and
trained the network by following the software model’s equations. Also
replicated were the functionality and logic required to run the network;
inputs are applied externally to an already-trained network, and a solution is
reached through convergence in time.

###  III-A Neuron

A neuron in a recurrent neural network needs to update its state based on
inputs and send weighted outputs based on that state.We use a biologically
inspired system to replicate this functionality, as shown in Fig. 3. The state
of the neuron is stored in its body, hereafter referred to as soma. The state
is updated by integrating the inputs it receives at its dendrite from its pre-
synaptic neurons. If the soma is sufficiently excited (i.e. the threshold is
passed), a signal is fired through the different branches of the neuron’s
axon. The signal is modified by the synapses at the end of each axon before it
is received by the dendrites of the postsynaptic neurons.111While the other
terms closely mirror their biological counterparts in form and function, soma
here has been chosen for lack of a better word.

Figure 3: A spintronic recurrent neuron with two axon branches. Input signals
come through the dendrite, into the soma, then into each axon which fires a
synaptically weighted output of $\pm W_{ij}$ .  Figure 4: Schematic of a
3-neuron spintronic Hopfield network showing neuron interconnection. Ini is
the external input to neuron $i$, $V_{DW}$ is the soma to axon voltage, and
$W_{ij}$ is the synaptic weight between neurons $i$ and $j$. The neurons are
connected in an all-to-all scheme, affecting each other over time through
their weighted connections and eventually converging to a stable state.

####  III-A1 Soma

The soma is a single DW-MTJ that integrates input from the DW’s left edge (its
dendrite) and sends signals to the axons through its MTJ. The soma’s
excitation state is physically determined by the location of the DW with
respect to the MTJ – left of the MTJ corresponds to an off state, and right to
an on. Input current moves the DW in either direction across the MTJ. In an on
state, the magnetization of the MTJ is parallel, sending a high current signal
to the axons. In an off state, the MTJ magnetization is anti-parallel, sending
a lower signal and relaxing the axons. The DW takes some time to travel
between states. When it is in this middle region, its output signal is between
its high and low signals; however, once past the MTJ, a full signal is sent.
To prevent the DW from staying in this intermediary state, the soma of the
artificial neuron employs a leaking factor to keep it from becoming stuck. The
leaking has the effect of causing the DW to relax toward one edge (the right
edge) when no input is applied. Biological neurons’ employ a similar method of
maintaining homeostasis with ion leakage channels to create a leaky integrate-
and-fire system. This leaky integrate-and-fire system helps modulate the
neuron’s excitation when insufficiently stimulated and serves as a means of
temporal coincidence detection between stimuli. [32].

####  III-A2 Axons

Each individual axon branch is a DW-MTJ connected to the others in parallel,
as shown in Fig. 3. The synaptic weight voltages on top of the axon branches
function as the synapse as this is where the connection weights are
manipulated. In the brain, information is stored, not in the neurons
themselves, but in their synaptic connections between each other [33]. As
such, the synaptic weight is stored in MTJ voltage and is set externally
during training. This weight voltage depends on the network, and can be any
number that allows for logical operation of the neurons.

Ideally, axons are in the same state as their soma, both low or both high;
however, the soma can only ever send a positive current through its MTJ. An
appropriate threshold leaking value is added to fix this issue [8, 9, 10].
When the soma sends a low signal to the axons, the leaking overtakes it,
keeping the axon’s DW to the right. A high signal is greater than the leaking
and thus pushes the DW towards a high state. In a high state, the axon fully
fires its weighted connection toward another neuron.

###  III-B Spintronic Hopfield Network

To create a Hopfield network, we connected the proposed neurons to each other,
forming a fully connected graph as shown in Fig. 4. Because of this all-to-all
connection scheme, every neuron in an N-neuron network has one soma and N-1
axons. In total, an N-neuron network will have $\text{N}^{2}$ DW-MTJ devices
present.

Training is performed according to the equations outlined in section II,
resulting in the synapse voltages being set to $\pm$W, where W’s value
represents a weight constant chosen based on the resistance of the DW track,
the MTJ resistance, and the tunnel magnetoresistance ratio (TMR) of the MTJ.
For multiple patterns, the formula is applied individually for each and then
the weight matrices are summed to form the final set.

After training, the network’s neuron states can be initiated to some pattern
using voltage sources of constant $\pm V_{C}$. Once these sources are
disconnected from the network, it will attempt to converge to the closest
stored pattern.

###  III-C Parameters

####  III-C1 MTJ Parameters

The DW velocity of a DW-MTJ can be approximated as

$v=I\frac{gP\mu_{B}}{2AM_{sat}e}+L=Ik+L$ (4)

where $g$ is the Landé factor, $P$ is the polarization constant, $\mu_{B}$ is
the Bohr magneton, $A$ is the cross sectional area of the metal track normal
to current flow, $e$ is the electron charge, $Msat$ is the saturation
magnetization, and $L$ is the leak speed [34, 35]. All characterizations of
DW-MTJs will be determined by the manufacturing process and thus are difficult
to tailor to specific implementations.

TABLE I: Device Parameters with Values Used in Simulations Symbol | Parameter | Value | Units
---|---|---|---
$g$ | Landé factor | $2.1$ | -
$P$ | Polarization constant | $0.7$ | -
$\mu_{B}$ | Bohr magneton | $9.274\times 10^{-24}$ | $J/T$
$A$ | Cross sectional area | $50$ | $nm^{2}$
$Len$ | DW track length | $100$ | $nm$
$MTJW$ | MTJ Width | 20 | $nm$
$MTJP$ | MTJ Placement | 50 | $\%$
$e$ | Electron charge | $1.602\times 10^{-19}$ | $C$
$Msat$ | Saturation magnetization | $8\times 10^{5}$ | $A/m$
$L_{syn}$ | Axon leak speed | $-5$ | $m/s$
$L_{axon}$ | Soma leak speed | $0.2$ | $m/s$
$R_{P}$ | MTJ parallel resistance | $500$ | $\Omega$
$R_{AP}$ | MTJ antiparallel resistance | $2000$ | $\Omega$
$R_{M}$ | Metal layer resistance | $2000$ | $\Omega$
$V_{C}$ | Charge-up voltage | $0.25$ | $V$
$W$ | Synaptic weight voltage | $0.1$ | $V$
$V_{DW}$ | Soma to Axon voltage | Varies with N | $V$
Figure 5: A graph showing the bitwise convergence accuracy for spintronic
Hopfield networks of sizes up to 30 neurons when storing one to four patterns.

####  III-C2 Voltage Parameters

The inputs to the system can be easily modified to control network behavior
over a wide range of manufacturing-determined parameters. These inputs are the
charge-up voltage magnitude $V_{C}$, the synaptic weight voltage magnitude
$W$, and the Soma voltage $V_{DW}$. Note that in the system, we use voltages
of $\pm V_{C}$, $\pm W$, and $V_{DW}$.

The charge-up voltage, $V_{C}$, is only connected for a brief period while the
state of the network is initiated. Increasing $V_{C}$ shortens the time needed
to charge up the somata; however, this is only a small fraction of the total
charge-up time. A higher $V_{C}$ would also increase the power consumption of
the charge-up stage. To ensure each soma charges up properly, $V_{C}\gtrapprox
W$.

$W$ determines how quickly the pre-synaptic neurons can change the excitation
state of the post-synaptic neurons. Increasing $W$ will increase power
consumption and decrease the needed time for the network to converge on
average. Additionally, there is an inverse relationship between the magnitude
of $W$ and the relative effect of the leak constant.

$V_{DW}$ controls how the axons in a neuron respond to the state of their
soma. The velocity of an axon’s DW can be represented as

$v=k\frac{V_{DW}}{(N+1)(R_{A}+\frac{R_{M}}{N+1})}+L_{syn},$ (5)

where $N$ is the number of neurons, $R_{A}$ is the resistance of the soma’s
MTJ, and $R_{M}$ is the resistance of the metal layer. To have the axons
mirror the soma’s state, we need a leftward DW velocity when the soma is in
the antiparallel state and a rightward velocity when it is in the parallel
state. The middle of this range can be found by

$0=k\frac{V_{DW}}{(N+1)(\frac{R_{AP}+R_{P}}{2}+\frac{R_{M}}{N+1})}+L_{syn}$
(6)

where $R_{P}$ and $R_{AP}$ are the antiparallel and parallel resistances of
the MTJs, respectively. By rearranging this expression, we find

$V_{DW}=\frac{L_{syn}}{k}(N-1)(\frac{R_{AP}+R_{P}}{2})$ (7)

or

$V_{DW}=\frac{LR_{P}}{k}(N-1)(1+\frac{T}{2})$ (8)

where $T$ is the tunnel magnetoresistance (TMR). Table I lists the parameters
used for simulations used in this paper.

##  IV Results

The network was initially simulated in Cadence using models that followed DW-
MTJ behavior [36, 37, 38]. Larger network sizes took a prohibitively long time
to simulate, so a specialized simulation program was created which was able to
perform the calculations significantly faster. The values calculated at each
step of this program were verified against those generated by Cadence to
confirm simulation correctness. Simulations were then run to solve the
associative memory problem over multiple network sizes and the max-cut problem
for a 60 neuron network.

###  IV-A Single Pattern Recall

The weight matrix of a Hopfield network is identical when storing a pattern or
its inverse. For example, storing the pattern “110” or its inverse “001” would
result in identical Hopfield networks. Therefore in simulations, an output was
considered accurate if it matched the stored pattern or its inverse.

Networks with a size of three, four, and five neurons had every input-pattern
combination tested and evaluated in Cadence for accuracy following this
criterion. The odd sizes (three and five) showed 100% accuracy; perfect
recollection of the stored pattern. The even size (four) showed lower, failing
to converge in certain cases where the network ”froze,” and was not able to
converge further. Freezing occurred when the network became stuck in a global
minimum with the same number of high and low neurons (Ex. 1100). This is only
possible under unique circumstances: there must be an even number of neurons
in the network and the weights must be symmetric.

###  IV-B Multiple Pattern Recall

Due to the exponentially increasing demands of simulating larger network
sizes, Cadence became impractical to use. A specialized program was created
that performed identically to the Cadence simulations but scaled to larger
networks. Using this simulator, networks of up to 30 neurons had their
accuracy tested on 1000 random test cases, as shown in Fig. 5. These tests
also stored more than one pattern in the network. To be considered accurate,
the network had to converge to any one of the stored patterns or their
inverse.

Results show that the network continues to perform well for single pattern
cases, showing perfect recall for odd network sizes. In addition recall was
accurate for two patterns being stored in the network, eventually settling at
perfect recall. The three and four pattern storage suffers on complete
convergence, but resolves more than 94% of the bits in a pattern.

(a)

(b)

(c)

Figure 6: (a) Three separate 10x10 binary images stored in a spintronic
Hopfield network. (b) Sample inputs to the network with a distortion of 10%.
(c) A graph showing the number of pixels different between network output and
the true undistorted image.

###  IV-C Binary Image Distortion

One of the many uses of Hopfield networks is to reconstruct images affected by
some noise. Three separate 10x10 binary images were created and converted to
vectors for input to the network to illustrate this functionality as shown in
in Fig. 6(a). Each image was then subjected to various noise levels, where
noise was added by flipping a percentage of unique pixels; an example is shown
in Fig. 6(b). The average accuracy of the spintronic network was then plotted
against distortion level, as shown in Fig. 6(c). A distortion of 50%, or
flipping half the pixels, is the greatest amount of distortion possible
because inverse patterns are intrinsically stored.

Perfect recall was shown for low levels of distortion, but as noise increased,
recollection got worse. While not perfectly accurate for higher levels of
distortion, the spintronic network was usually able to converge to only a few
pixels from the true solution. This behavior shows that the network is
distinguishing between stored patterns and converging to the closest image.
The true pattern could be unrecognizable at distortion levels of 33% or more;
the network resembled other patterns more closely causing false convergence
and lower accuracy.

Figure 7: (a) Approximate medium convergence time and energy consumption of a
60 Neuron network with a $V_{C}=0.25V$ and a varying $W$. (b) Approximate
medium convergence time and energy consumption of 100 trials of a 60 Neuron
network with a varying $V_{C}$ and a $W=0.1V$. Medium convergence time varies
very weakly on $V_{C}$, and thus was excluded.

###  IV-D Efficiency

The efficiency of the spintronic network depends on both device parameters and
voltage levels. Device variables such as the MTJ dimensions, metal track
resistance, and TMR depend on manufacturing technology and are hard to change.
On the other hand, voltage levels in the inputs and weights are easily
modified. These voltage levels can significantly affect power consumption, as
illustrated in Fig. 7. In general, increased synaptic weight voltages benefit
the network by increasing convergence speed but hinder the network by
requiring greater power consumption. Increased charge up voltages have a
negligible effect on convergence time but increase power consumption.

A recent study [21] described a memristive Hopfield network that could be used
to find solutions to the max-cut problem. In this work, a switch matrix and
drivers circuit was used to select rows of a memristor array to perform
multiplication. The result is then filtered, to produce a threshold function.
This result is then fed back into the input/output buffers, to be loaded in
during the next cycle. Noise is modeled to prevent convergence to a non-
optimal state. The work estimates that for a network of 60 neurons with 50%
connectivity, 50 cycles of the device would require 72 nJ over 6.6 $\mu$s or
600 ns. These values correspond to between a 30 and 40% chance of converging
to the correct solution.

In contrast, our spintronic network does not include cycles, and is composed
of only DW-MTJ devices and voltage sources. This allows a faster convergence
time and less energy use. To run the max-cut problem, the weights between
disconnected nodes were set to $+W$ while weights between connected nodes were
set to $-1.05W$. 222This 5% difference was chosen empirically to introduce
asymmetry thereby improving performance for this problem. The initial states
of the DW-MTJs were set to the anti-parallel state before release. The state
of the DW-MTJ after the network has converged represents which of the two
graphs each node will be split into after the cut. Using 10 standard 50%
connected graphs in the Biq Mac Library [39], a 60 neuron spintronic Hopfield
network reached an approximate solutions with 92.8% of cuts compared to the
ideal solution. Compared to the memristive Hopfield network, the spintronic
network converged at a faster average speed of 355 ns. The spintronic network
also uses less energy, consuming an average of 61.7 mW and using 21.9
nJ.333All power calculations are performed by dividing the total sum of the
energy use by the total sum of the run time across all trials. The worst-case
energy consumption is an outlier at 55.4 nJ, but still lower than the
memristive network. Variation of power consumption between runs in the
spintronic network resulted from varying current draws in different MTJ states
and the high power used during the initiation of neurons compared to the lower
power used during convergence.

Another work has modeled a SONOS transistor Hopfield based network as a
memristor crossbar [24]. They calculated their energy to solution using the
same 60 by 60 graphs from the BiqMac library as 33 nJ. This work also involves
external circuitry to read the output of a cycle in order to feed it as the
input to the next. While this work did not provide exact cycle times, it
discusses a SONOS ramp-up times of a microsecond for a different
demonstration. As such, we suspect our network is significantly faster.

The associative memory task used considerably less energy due to its quicker
convergence time. Over 100 trials, a 60 neuron spintronic Hopfield network
reached an approximate solution at a faster average speed of 81.1 ns with no
trial taking longer than 118 ns to converge. The network consumed an
approximate average of 83.1 mW and used 6.75 nJ, having a worst case energy
consumption of 8.65 nJ.

Additionally, while we did not consider it in this paper due to
manufacturability concerns, reducing the synaptic weight voltage to 0 during
the charge-up stage would eliminate the $V_{C}\gtrapprox W$ constraint. A
significant reduction of $V_{C}$ can then occur with only minimal impact on
the total convergence time due to the fact that the charge up stage takes far
less than a nanosecond with our parameters. This could drastically mitigate
the charge-up state’s energy consumption, which consumes around half of the
total energy used by a 60 neuron network.

##  V Conclusion

This paper presents a biologically inspired, asynchronous, fully spintronic
recurrent neural network built using DW-MTJs. Neurons are cascaded into a
Hopfield network, demonstrating the first fully spintronic RNN with
reconfigurable weights that we are aware of. The network solved both the
associative memory and max-cut problems in testing, resulting in a high
percentage of convergence for both. While solving these problems, the
spintronic Hopfield network converged faster and with less energy than current
hardware designs. These results support the efficiency of spintronic devices
in neuromorphic computing and can lead to architectures that eliminate CMOS
overhead and fully take advantage of emerging devices.

## Acknowledgment

The authors thank R. Iyer for editing, E. Laws, J. McConnell, N. Nazir, L.
Philoon, and C. Simmons for technical support, and H.-J. Drouhin for arranging
the research exchange. This research is sponsored in part by the National
Science Foundation under CCF award 1910800 and the Texas Analog Center of
Excellence undergraduate internship program.

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