IEEEexample:BSTcontrol

# Aging-Aware Request Scheduling for Non-Volatile Main Memory

Shihao Song  Drexel UniversityUSA ,  Anup Das  Drexel UniversityUSA ,  Onur
Mutlu  ETH ZürichSwitzerland and  Nagarajan Kandasamy  Drexel UniversityUSA

(2021)

###### Abstract.

Modern computing systems are embracing non-volatile memory (NVM) to implement
high-capacity and low-cost main memory. Elevated operating voltages of NVM
accelerate the aging of CMOS transistors in the peripheral circuitry of each
memory bank. Aggressive device scaling increases power density and
temperature, which further accelerates aging, challenging the reliable
operation of NVM-based main memory. We propose HEBE, an architectural
technique to mitigate the circuit aging-related problems of NVM-based main
memory. HEBE is built on three contributions. First, we propose a new
analytical model that can dynamically track the aging in the peripheral
circuitry of each memory bank based on the bank’s utilization. Second, we
develop an intelligent memory request scheduler that exploits this aging model
at run time to de-stress the peripheral circuitry of a memory bank only when
its aging exceeds a critical threshold. Third, we introduce an isolation
transistor to decouple parts of a peripheral circuit operating at different
voltages, allowing the decoupled logic blocks to undergo long-latency de-
stress operations independently and off the critical path of memory read and
write accesses, improving performance. We evaluate HEBE with workloads from
the SPEC CPU2017 Benchmark suite. Our results show that HEBE significantly
improves both performance and lifetime of NVM-based main memory.

††journalyear: 2021††copyright: acmcopyright††conference: 26th Asia and South
Pacific Design Automation Conference; January 18–21, 2021; Tokyo,
Japan††booktitle: 26th Asia and South Pacific Design Automation Conference
(ASPDAC ’21), January 18–21, 2021, Tokyo, Japan††price: 15.00††doi:
10.1145/3394885.3431529††isbn: 978-1-4503-7999-1/21/01

##  1\. Introduction

DRAM has been the technology choice for implementing main memory due to its
relatively low latency and low cost. However, DRAM is a fundamental
performance and energy bottleneck in almost all computing systems, and it is
experiencing significant technology scaling challenges (Kim et al., 2014,
2020; Mandelman et al., 2002; Mutlu, 2013, 2017; Mutlu and Kim, 2019; Das et
al., 2018). Recently, DRAM-compatible, yet more technology-scalable
alternative non-volatile memory (NVM) technologies such as Phase-Change Memory
(PCM), are being explored (Lee et al., 2009, 2010a, 2010b; Yoon et al., 2014;
Mutlu and Subramanian, 2015; Qureshi et al., 2010, 2009; Qureshi, 2011; Song
et al., 2019; Kültürsay et al., 2013; Song et al., 2020a, b; Wong et al.,
2010; Meza et al., 2013).111NVMs are also used for synaptic storage in
neuromorphic computing (Burr et al., 2017; Mallik et al., 2017; Balaji et al.,
2020a, b; Song et al., 2020c).

Compared to DRAM, NVM requires higher voltages to read and program memory
cells. We investigate the internal architecture of the peripheral circuitry of
each memory bank and find that such circuitry consists of transistors built
using CMOS and FinFET (Hisamoto et al., 2000). When operated at high voltage
and temperature, over time the transistor’s parameters can strongly drift from
their nominal values. This is called _aging_. In fact, in scaled technology
nodes, aging happens even under nominal conditions from the very start of
device use. The most important breakdown mechanism is the Bias Temperature
Instability (BTI) (Weckx et al., 2014; Kraak et al., 2019). Strongly depending
on the workload, BTI is highly variable and largely reversible under nominal
conditions upon removal of the stress voltage. However, if the peripheral
circuitry is used continuously for long durations at elevated operating
conditions, the BTI induced parameter drifts in peripheral circuitry cannot be
reversed (Yilmaz et al., 2013), leading to permanent functional degradation
and hardware faults.

As process technology scales down to smaller dimensions due to NVM’s CMOS-
compatible scaling (Xiong et al., 2016), aging issues are expected to get
exacerbated due to the increase in the electric field and power density, which
leads to higher chip temperatures and, consequently, the acceleration of BTI.
Current methods for improving aging are overly conservative, since they
estimate transistor aging in a peripheral circuitry _statically_ , assuming
worst-case operating conditions (Jiang et al., 2014). Based on such worst-case
estimates, these methods de-stress each peripheral circuitry periodically at a
fixed interval, without tracking its actual aging. Therefore, these methods
significantly and unnecessarily constrain performance.

Our goal is to design a dynamic policy to track the aging in the peripheral
circuitry of each memory bank based on the operating voltages needed to serve
read and write requests from the bank, and dynamically schedule its de-stress
operation only when its aging exceeds a critical threshold. Our architectural
approach to mitigate aging in NVM, called HEBE,222In Greek mythology, Hebe
(pronounced hee.bee) is the goddess of youth (Wikipedia contributors, 2020).
is built on three contributions.

Contribution 1. We develop a new, accurate analytical model to estimate
transistor aging in peripheral circuitry of each memory bank. Our model
dynamically tracks aging in response to a memory controller’s request
scheduling decisions such as serving a read (which requires $2.85V$) vs. a
write (which requires $3.7V$). To use this model at run time, we leverage the
associative property of our analytical formulation, a direct reflection of the
underlying physical failure mechanism, allowing us to express aging in terms
of offline-computed _unit aging_ parameters (described in Section 3). Our
memory controller uses these parameters to estimate aging in a peripheral
circuitry based on the number of read and write requests that are served via
the circuitry.

Contribution 2. We develop a new, intelligent memory request scheduler that
prioritizes requests to banks whose peripheral circuits are currently active
but not serving any memory request, over other requests, including the long-
outstanding ones. This straightforward and greedy policy is controlled in two
ways. First, the memory controller uses our new aging model to track the aging
of a peripheral circuitry, de-stressing the circuitry only when its aging
exceeds a critical threshold. Second, the memory controller uses thresholding
to avoid starvation of memory requests.

Contribution 3. We introduce an isolation transistor in each peripheral
circuitry to decouple its logic blocks operating at different supply voltages
during read and write accesses (see Fig. 1). The decoupled architecture allows
these logic blocks to be de-stressed based on their respective aging levels.
Our request scheduler exploits this decoupled architecture to schedule the
long-latency de-stress operations off the critical path of accesses, reducing
bank occupancy and improving performance.

We evaluate HEBE with workloads from the SPEC CPU2017 Benchmark suite (Bucek
et al., 2018). Our results show that HEBE significantly improves both
performance and lifetime of NVM-based main memory.

##  2\. Background

NVM, like DRAM (Kim et al., 2012; Seshadri and Mutlu, 2019; Das et al., 2018;
Lee et al., 2013), is organized hierarchically (Redaelli et al., 2017; Song et
al., 2019, 2020a, 2020b; Meza et al., 2012a, 2018; Yoon et al., 2014). For
example, a 128GB NVM can have 2 channels, 1 rank/channel and 8 banks/rank. A
bank can have 64 partitions (Song et al., 2019). Each bit in NVM is
represented by the resistance of an NVM cell: low resistance is logic ‘1’ and
high resistance is logic ‘0’. An NVM cell is read and programmed by driving
current through it using per bank peripheral circuitry (see Fig. 1).
Peripheral circuitry consists of sense amplifiers (SA) to read and write
drivers (WD) to program. WD consists of the write pulse shaper (PS) logic,
which generates the current pulses necessary for SET and RESET operations, and
the verify (VF) logic, which verifies the correctness of these operations
(Frulio, 2016).

Figure 1. Architecture of NVM peripheral circuitry (Song et al., 2019).

In addition to the regular read and write mode of operations, peripheral
circuitry can also be in 1) idle mode, where it does not serve any request,
and 2) de-stress mode, where it is powered down. Table 1 reports the operating
voltages of the three logic blocks in a peripheral circuitry during read,
write, idle, and de-stress operations (Redaelli et al., 2017). Voltages higher
than the nominal $1.2V$ supply are generated using the two on-chip charge
pumps shown in Figure 1. These high voltages induce aging of the transistors
in the peripheral circuitry logic blocks. We focus on BTI failures.

Figure 2. Threshold voltage ($V_{\text{th}}$) shift due to BTI.

BTI is a failure mechanism in a transistor, where positive charge is trapped
in the oxide-semiconductor boundary underneath the gate (Gao et al., 2017).
BTI manifests as 1) decrease in drain current and transconductance, and 2)
increase in off current and threshold voltage $V_{\text{th}}$. Figure 2
illustrates the stress and recovery of the threshold voltage of a transistor
on application of a high ($V_{\text{read}}/V_{\text{write}}$) and a low
($V_{\text{de-stress}}$) voltage. We observe that both stress and recovery
depends on the time of exposure to the corresponding voltage level. This
implies that when peripheral circuitry is de-stressed, the BTI aging of its
transistors partially recovers from stress. To compute the overhead due to de-
stress operations, we assume that the memory controller issues a de-stress
command to a memory bank once every $tDSI$, the de-stress interval. Each de-
stress operation completes within a time interval $tDSC$, the de-stress cycle
time. Hence, the performance overhead (i.e., data throughput loss) due to
periodic de-stress is

(1) $\scriptsize\text{de-stress overhead}=tDSC/tDSI.$

The overhead due to periodic de-stress (as implemented in conservative
approaches such as (Jiang et al., 2014)) is significant in current NVM
devices, and it is expected to become even more performance-critical in the
future as NVM chip capacity increases (Redaelli et al., 2017).

Operating mode | Operating voltage
---|---
pulse shaper | verify | sense amplifier
(PS) | (VF) | (SA)
Read | 1.2V | 1.2V | 2.85V
Write (program) | 3.7V | 2.85V | 1.2V
Idle | 1.2V | 1.2V | 1.2V
De-stress | $<V_{\text{th}}$ | $<V_{\text{th}}$ | $<V_{\text{th}}$
Table 1. Operating voltage of the three logic blocks in peripheral circuitry
during read, write, idle, and de-stress (Redaelli et al., 2017). The threshold
voltage ($V_{th}$) of a CMOS transistor is between 0.7V and 1V at scaled
nodes.

Figure 3 shows the shift in threshold voltage of a transistor in a memory
bank’s peripheral circuitry when executing a microbenchmark with $tDSI$ set to
$10$ and $100$ requests, respectively.333The microbenchmark we use for this
evaluation consists of alternating read and write requests to randomly
selected PCM locations.

We observe that the shift in the threshold voltage is higher for larger de-
stress interval $tDSI$. This is because when we set $tDSI$ to a large value,
the transistor is exposed to a stress voltage for a long duration between two
consecutive de-stress operations. Therefore, the large parameter drift it
encounters in this duration cannot be reversed during the next de-stress
operation. The parameter drift continues to accumulate over time, resulting in
a large shift in the threshold voltage as shown in the figure. Therefore, it
is better to set the $tDSI$ to a small value, which allows most of the
parameter drifts to be reversed during each de-stress operating, resulting in
a lower threshold voltage shift.

Figure 3. Shift in $V_{\text{th}}$ for $tDSI=10$ and $100$.

However, setting a lower $tDSI$ leads to a higher de-stress related
performance overhead, which we formulate in Equation 1. HEBE exploits this
performance-reliability trade-off using its new intelligent memory request
scheduler (see Sec. 5).

##  3\. New Aging Model of HEBE

In this section, we introduce the new aging model of HEBE. The BTI lifetime
(Song and Das, 2020; Song et al., 2020d; Balaji et al., 2019; Song et al.,
2020a; Das et al., 2014a, b, c, d) of a transistor is

(2)
$\footnotesize\text{MTTF}_{\text{BTI}}=\frac{A}{V^{\gamma}}e^{\frac{E_{a}}{KT}},$

where $A$ and $\gamma$ are material-related constants, $E_{a}$ is the
activation energy, $K$ is the Boltzmann constant, $T$ is the temperature, and
$V$ is the overdrive gate voltage of the transistor.444Overdrive voltage is
defined as the voltage between transistor gate and source ($V_{GS}$) in excess
of the threshold voltage ($V_{\text{th}}$), where $V_{\text{th}}$ is the
minimum voltage required between gate and source to turn the transistor on.
BTI failures can also be modeled using the Weibull distribution with a scale
parameter $\alpha$ and a slope parameter $\beta$. The reliability, defined as
the probability of correct operation of the transistor, at time $t$ is given
by (Das et al., 2015; Huang et al., 2011; Bolchini et al., 2014; Srinivasan et
al., 2004)

(3) $\scriptsize R(t)=e^{-\left(\frac{t}{\alpha(V)}\right)^{\beta}},$

with the corresponding MTTF computed as

(4) $\scriptsize
MTTF=\int_{0}^{\infty}R(t)dt=\alpha(V)\Gamma\left(1+\frac{1}{\beta}\right),$

where $\Gamma$ is the Gamma function. Using the expressions for MTTF from
Equations 2 and 3, and rearranging, we obtain the expression for the scale
parameter $\alpha$ as

(5)
$\scriptsize\alpha(V)={\frac{A}{V^{\gamma}}e^{\frac{E_{a}}{KT}}}\bigg{/}{\Gamma\left(1+\frac{1}{\beta}\right)}.$

Figure 4 shows the operating voltage of PS, VR, and SA blocks in the
peripheral circuitry of a memory bank when serving read and write requests
from the bank. We observe that the operating voltage of the logic blocks in a
memory bank’s peripheral circuit changes over time based on whether the
peripheral circuit is idle or serving read or write requests. Existing aging
models such as (Srinivasan et al., 2004; Das et al., 2015, 2013a) assume
constant operating voltage for the logic blocks. Therefore, these models
cannot be effectively used to estimate the aging in a memory bank’s peripheral
circuitry.

We illustrate how we formulate aging of each of these three logic blocks in
peripheral circuitry, starting with the PS logic. Let $[t_{i},t_{i+1})$ be the
$(i+1)$th time interval with $\Delta t_{i}=t_{i+1}-t_{i}$ and $V_{i}$ be the
gate overdrive voltage in this time interval $t_{i}$. The reliability of the
PS logic at the start of execution is

(6) $\scriptsize R(t)|_{t=t_{0}}=1.$

At the end of the first interval (i.e, after servicing the first read
request), the reliability of the PS logic is

(7) $\scriptsize
R(t_{1}^{-})=e^{-\left(\frac{t_{1}}{\alpha(V_{0})}\right)^{\beta}}.$

Using the term $\theta$ to represent reliability degradation during this
interval $[t_{o},t_{1})$, the reliability at the beginning of the second
interval (i.e., right after the start of the first idle period) is

(8) $\scriptsize
R(t_{1}^{+})=e^{-\left(\frac{t_{1}+\theta}{\alpha(V_{1})}\right)^{\beta}}.$

Due to the continuity of the reliability function, we can equate Equations 7 &
8 to compute $\theta$ as

(9)
$\scriptsize\theta=\left(\frac{\alpha(V_{1})}{\alpha(V_{0})}-1\right)t_{1}.$

Substituting Eq. 9 in Eq. 8, reliability at time $t_{2}$ is

(10) $\scriptsize R(t_{2})=e^{-\left(\frac{\Delta
t_{1}}{\alpha(V_{1})}+\frac{\Delta t_{0}}{\alpha(V_{0})}\right)^{\beta}}.$

We can extend this equation to compute the reliability of the PS logic at the
end of execution (i.e., after servicing the last write request from the bank
in Fig. 4) as

(11) $\scriptsize R(t_{s})=e^{-\left(\sum_{i=1}^{n}\frac{\Delta
t_{i}}{\alpha(V_{i})}\right)^{\beta}},$

Figure 4. Operating voltage of PS, VR, and SA logic blocks in peripheral
circuitry of a bank when serving read and write requests. (Overdrive voltage =
operating voltage - $V_{\text{th}}$).

The aging $\mathcal{A}_{\text{PS}}$ of the PS logic is

(12) $\scriptsize\mathcal{A}_{\text{PS}}=\sum_{i=1}^{n}\frac{\Delta
t_{i}}{\alpha(V_{i})},\text{ such that
}R(t_{s})=e^{-(\mathcal{A}_{\text{PS}})^{\beta}},$

where the scaling factor $\alpha(V_{i})$ can be calculated using Eq. 5.

We observe that Eq. 12 follows the associative property, a direct reflection
of the underlying BTI failure mechanism. In other words, the aging accrued in
each bank’s peripheral circuitry is independent of the order in which the
reads and writes are scheduled to the bank. Eq. 12 can be rewritten using
memory timing parameters as

(13)
$\scriptsize\mathcal{A}_{\text{PS}}=n_{r}\cdot\mathcal{U}_{r}+n_{w}\cdot\mathcal{U}_{w}+n_{i}\cdot\mathcal{U}_{i},\text{
where }$
$\displaystyle\mathcal{U}_{r}=\frac{tRC_{r}}{\alpha(1.2)},\mathcal{U}_{w}=\frac{tRC_{w}}{\alpha(3.7)},\text{
and }\mathcal{U}_{i}=\frac{1}{\alpha(1.2)}$

where, $tRC$ is the row cycle time, $n_{r}$ and $n_{w}$ are the number of read
and write requests, respectively, and $n_{i}$ is the number of memory clock
cycles for which the PS logic is idle. $\mathcal{U}_{r}$ and $\mathcal{U}_{w}$
represent respectively, the aging accrued in peripheral circuitry when serving
a read and a write request, and $\mathcal{U}_{i}$ represents the aging accrued
per clock cycle when the peripheral circuitry is idle.
$\mathcal{U}_{r},\mathcal{U}_{w}$, and $\mathcal{U}_{i}$ are called unit aging
parameters, which the memory controller uses to track the aging of the PS
logic in peripheral circuitry by simply recording 1) the number of read and
write requests that are served from the bank, and 2) the number of idle clock
cycles during workload execution. We note that these factors (read/write
requests and the idle periods) cannot be known with certainty at design-time.
Therefore, design-time aging estimates are not accurate.

The aging of VR and SA logic blocks (represented as $\mathcal{A}_{\text{VR}}$
and $\mathcal{A}_{\text{SA}}$, respectively) can be computed in a similar way
using Eq. 13. To obtain the overall aging, we combine these individual aging
values considering the peripheral circuitry to be a series failure system,
where the first instance of any logic block failing causes the entire
peripheral circuit to fail. Therefore, the overall aging is

(14)
$\footnotesize\mathcal{A}=\max\\{\mathcal{A}_{\text{PS}},\mathcal{A}_{\text{VR}},\mathcal{A}_{\text{SA}}\\}.$

##  4\. Decoupled Peripheral Circuit Architecture of HEBE

In the baseline system, when peripheral circuitry is de-stressed, its three
logic blocks (PS, VR, and SA) are de-stressed simultaneously. Once de-
stressed, these logic blocks take several memory cycles ($tDSC$) before they
can be used to serve memory requests again. In recent designs, $tDSC=10$
cycles (Redaelli et al., 2017). Therefore, frequent de-stress operations can
lead to high performance overhead (Eq. 1). To reduce this overhead, we analyze
the average aging of the PS, VR, and SA blocks in a memory bank’s peripheral
circuitry at the time when they are de-stressed during workload execution.
Figure 5 plots these results for the workloads described in Section 6 with
$tDSI$ set to $100$. We make the following two key observations.

Figure 5. Average aging in arbitrary units (a.u.) of the PS, VR, and SA logic
blocks in peripheral circuitry, at the time when they are de-stressed for our
evaluated workloads.

First, the average aging of these logic blocks varies widely across different
workloads due to the difference in memory requests. Second, at the time when a
de-stress is initiated, the average aging for these three logic blocks are
different and lower than the aging threshold. This is because in the baseline
design, a peripheral circuit is de-stressed at its entirety, when the aging in
any one of its three logic blocks exceeds the aging threshold.

Based on these observations and the connectivity of the logic blocks to the
two charge pumps (see Fig. 1), we introduce an isolation transistor (M) to
decouple the VR logic from the PS logic inside the write driver, allowing us
to track and de-stress the logic blocks individually, as opposed to de-
stressing the entire peripheral circuitry at once. Table 2 summarizes the new
controls, which we enable using the isolation transistor.

Using these new decoupled control mechanism, HEBE’s request scheduler (Section
5) can de-stress logic blocks in a bank’s peripheral circuitry off the
critical path of accesses, lowering bank occupancy and improving performance.
We observe that the read charge pump is shared between the SA and VR logic
blocks (see Figure 1). Therefore, when HEBE de-stresses the SA because SA’s
aging exceeds the critical aging threshold, the VR logic also gets de-
stressed, preventing the write driver from serving write requests. To address
this, we exploit the decoupled program and verify-based write operations in
PCM (Frulio, 2016). If a write request needs to be scheduled concurrently with
the de-stress operation of SA, HEBE schedules only the program step of the
write operation (which utilizes the PS block) concurrently with the de-stress
operation, while the verify step is scheduled after the de-stress operation
completes.

Charge Pump Control | Peripheral Circuit Action
---|---
Read | Write | PS | VR | SA
Baseline Control
Active | Active | Active | Active | Active
Discharged | Discharged | De-stress | De-stress | De-stress
Proposed Decoupled Control
Active | Active | Active | Active | Active
Discharged | Active | Active | De-stress | De-stress
Active | Discharged | De-stress | Active | Active
Discharged | Discharged | De-stress | De-stress | De-stress
Table 2. Controlling de-stress ops. using charge pumps.

##  5\. Intelligent Memory Request Scheduler of HEBE

We design a new memory request scheduling policy to control the aging in the
peripheral circuitry within each memory bank using our new aging model
(Section 3) and the decoupled peripheral circuit architecture (Section 4).

###  5.1. High-level Overview

We describe HEBE in the context of DRAM-PCM hybrid memory, where embedded DRAM
(eDRAM) is used as a write cache to PCM main memory as shown in Figure
6.555Even though we use eDRAM as cache to PCM in our implementation and
evaluations, HEBE is applicable to any type of hybrid memory or standalone PCM
memory. The baseline memory controller architecture consists of a read-write
queue (rwQ) to buffer PCM requests. The key idea of HEBE’s scheduling policy
is to 1) improve performance by lowering the de-stress overhead, 2) minimize
wasted memory cycles during which a bank is idle with its peripheral circuitry
accruing BTI aging, and 3) prevent a request from being delayed too much.

Figure 6. Request and de-stress scheduling in HEBE.

###  5.2. Detailed Design of HEBE

Figure 6 shows the detailed design of HEBE, which introduces five new
components to the baseline memory controller design as highlighted in the
figure.

The first component is the _status table_ (sTab). HEBE uses this table to
record if a memory bank is available to serve a PCM request. sTab requires one
1-bit entry for each PCM bank. For 128 banks in a 128GB PCM (see our
simulation parameters in Table 3), HEBE requires 128 bits of storage for sTab.

The second component is the _access table_ (aTab). HEBE uses this table to
record the number of memory cycles for which a memory bank’s peripheral
circuitry is active since the last de-stress operation of the bank. Since
peripheral circuitry operates at a different voltage when it is idle than when
it is serving a read or a write request, the aging model of HEBE requires the
exact number of cycles for which a peripheral circuit is idle and serving read
and write requests. Therefore, each aTab entry contains one 16-bit field for
recording the idle cycles, and two 4-bit fields for recording the number of
read and write requests. For 128GB PCM with 1GB per bank, HEBE requires 3Kb (=
128 x 24 bits) of storage.

The third component is the unit aging table (uTab). HEBE uses this table to
store the unit aging parameters (Eq. 13). Since the three unit aging
parameters are the same for every peripheral circuitry in PCM, there are only
three 32-bit entries in this table, one for each of these parameters,
requiring a total of 96 bits for uTab.666For simplicity, we have not
considered process variation across different peripheral circuitry of
different PCM banks.

The fourth component is the request selection. HEBE uses this component to
select a request from the rwQ to schedule to PCM. Figure 7 shows the flowchart
of HEBE’s request selection mechanism. After scheduling a request from the
rwQ, the memory controller checks to see if the number of clock cycles for
which a request is outstanding in the rwQ is smaller than the backlogging
threshold ($th_{b}$). If the backlogging threshold is exceeded, the request is
de-queued and served next. Otherwise, the memory controller selects an
outstanding request from the rwQ that is to a bank whose peripheral circuitry
has the highest number of idle cycles since the time it served a request from
the bank.

Figure 7. Memory request and de-stress selection in HEBE.

The final component is the de-stress selection logic. HEBE uses this component
to schedule de-stress operations in PCM banks. For this purpose, HEBE uses two
thresholds – the aging threshold ($th_{a}$) and the idle threshold ($th_{i}$).
The aging threshold is used to control the aging of peripheral circuitry in
PCM in order to achieve a target lifetime. The idle threshold is used to limit
the duration during which a peripheral circuit accrues aging without doing any
useful work. The de-stress selection logic is also shown in Figure 7. If the
selected memory request is to a bank whose peripheral circuitry exceeds either
of the two thresholds, the memory controller schedules a de-stress operation
to the bank. Otherwise, the request is scheduled to PCM.

###  5.3. Overhead of HEBE

HEBE requires a total storage of 3.2Kb for a PCM memory of 128GB capacity and
128 banks. The timing overhead of the request and de-stress selection is
overlapped with the timing of an ongoing read or a write request, incurring
minimal impact on the critical path of PCM read and write accesses. Therefore,
HEBE’s request scheduling introduces marginal performance overhead. On the
contrary, HEBE improves performance compared to other approaches by reducing
the de-stress related performance bottleneck (see Section 7.1).

##  6\. Evaluation Methodology

We evaluate HEBE for phase-change memory (PCM), one of the matured NVM
technologies. We configure PCM as main memory with eDRAM as its write cache.
This is similar to the architecture of IBM POWER 9 (Sadasivam et al., 2017).
Our simulation framework includes the following components with parameters
listed in Table 3.

  * •

Cycle-level in-house x86 multi-core simulator. We configure this to simulate 8
out-of-order cores.

  * •

Main memory simulator, closely matching the JEDEC Nonvolatile Dual In-line
Memory Module (NVDIMM) specifications (Lalam and Shen, 2019). This simulator
is composed of Ramulator (Kim et al., 2016), to simulate DRAM and an cycle-
level in-house NVM simulator, based on NVMain (Poremba et al., 2015).

  * •

Power and latency for DRAM and NVM are based on Intel/Micron’s 3D Xpoint
specification (Redaelli et al., 2017). Energy is modeled for DRAM using
DRAMPower (Chandrasekar et al., 2012) and for NVM using NVMain with parameters
from (Redaelli et al., 2017).

Processor |  8 cores, 3 GHz, out-of-order
---|---
L1-I/D cache |  Private 64KB per core, 4-way
L2 cache |  Shared, 4MB, 8-way
DRAM |  8GB, Micron DDR3
Main Memory |  1 channel, 8 rank/channel, 8 banks/rank, 128 sub-arrays/bank, 512 rows/sub-array
PCM |  128GB, Micron DDR3 (Redaelli et al., 2017)
Main Memory |  2 channels, 1 rank/channel, 8 banks/rank, 64 partitions/bank, 128 tiles/partition, 4096 rows/tile
Table 3. Major simulation parameters.

Table 4 reports the timing parameters for PCM reads and writes. These
parameters are based on Micron’s 128GB PCM module (Redaelli et al., 2017).

| tRCD | tRAS | tRP | tRC |
---|---|---|---|---|---
Read | 3.75ns | 55.25ns | 1ns | 56.25ns |
| tRCD | tBURST | tWR | tRP | tRC
Write | 75ns | 15ns | 190ns | 1ns | 209.75ns
Table 4. PCM timing parameters based on (Redaelli et al., 2017).

We evaluate 10 billion instructions of ten workloads from the SPEC CPU2017
benchmarks (Bucek et al., 2018) (see Table 5).

We evaluate the following techniques.

  * •

Baseline (Song et al., 2020b) de-stresses peripheral circuitry of each NVM
bank with a fixed $tDSI$ of 100, without tracking their aging. Memory requests
are scheduled using the FR-FCFS policy (Rixner et al., 2000; Zuravleff and
Robinson, 1997).

  * •

HEBE tracks the aging in CMOS transistors in peripheral circuitry of each bank
and de-stresses them only when their aging exceeds the aging threshold. A
peripheral circuitry is de-stressed based on the maximum aging of its logic
blocks.

  * •

Decoupled-HEBE is based on HEBE. Each peripheral circuitry is decoupled to de-
stress its logic blocks independently.

single-core |  8 copies each of blender, bwaves, cactuBSSN, cam4, gcc, mcf, omnetpp, parset, roms, xalancbmk
---|---
Table 5. Evaluated workloads.

###  6.1. Aging Parameters

To compute aging, the slope parameter of Weibull distribution is set to
$\beta=2$, and the operating temperature is set to $300K$. Other fitting
parameters are adjusted to achieve an MTTF of 2 years in the baseline system,
corresponding to a threshold voltage shift of 10%. This is what is typically
accepted as the maximum allowed $V_{\text{th}}$ degradation before timing
errors begin to appear (Balaji et al., 2019; Song and Das, 2020; Song et al.,
2020d; Titirsha and Das, 2020a, b; Das et al., 2012, 2013b; Das and Kumar,
2012; Das et al., 2015, 2013a).

##  7\. Results and Analyses

###  7.1. Overall System Performance

Figure 8 plots the execution time of each workload for the evaluated systems
normalized to Baseline. We make the following two key observations.

First, the average execution time of HEBE is 12% lower than Baseline. This
improvement is because HEBE has lower de-stress overhead than Baseline due to
HEBE’s dynamic policy to opportunistically de-stress each peripheral circuitry
only when its aging exceeds the aging threshold. Baseline, on the other hand,
uses a fixed de-stress interval of 100 without tracking the exact aging.
Second, the average execution time of Decoupled-HEBE is 6% lower than HEBE.
This improvement is because Decoupled-HEBE de-stresses the logic blocks in a
memory bank’s peripheral circuits off the critical path of read and write
accesses from the bank, reducing bank occupancy and improving performance.

Figure 8. Execution time, normalized to Baseline.

###  7.2. Overall MTTF

Figure 9 plots the MTTF of each workload for the evaluated systems normalized
to Baseline. We make the following two key observations.

Figure 9. MTTF, normalized to Baseline.

First, the average MTTF of HEBE is 16% higher than Baseline. This improvement
is because 1) HEBE does not allow the aging of any peripheral circuitry in PCM
to exceed the aging threshold and 2) the aging-aware access scheduling policy
of HEBE minimizes the number of wasted memory cycles for which a peripheral
circuitry accrues aging while being idle. Second, the average MTTF of
Decoupled-HEBE is 3.4% higher than HEBE. This improvement is because HEBE
needs to wait for an ongoing PCM read or write request to complete before it
can schedule the de-stress operation of a peripheral circuitry. Therefore, the
circuitry continues to age before it is eventually de-stressed, lowering its
MTTF. On the other hand, Decoupled-HEBE can schedule the de-stress operation
of a logic block in a bank’s peripheral circuitry independently and in
parallel to ongoing read and write requests to the bank. Therefore, the MTTF
of Decoupled-HEBE is higher than HEBE.

###  7.3. De-stress Overhead

Figure 10 plots the de-stress overhead (Eq. 1) of each workload for each
evaluated system normalized to Baseline. We make the following two key
observations.

Figure 10. De-stress overhead, normalized to Baseline.

First, the average de-stress overhead of HEBE is 6.6% lower than Baseline.
This improvement is because HEBE increases the de-stress interval ($tDSI$) by
accurately tracking the aging of each peripheral circuitry dynamically, de-
stressing it only when aging exceeds a threshold. Baseline uses a fixed $tDSI$
of 100. Second, the average de-stress overhead of Decoupled-HEBE is 35% lower
than HEBE. This improvement is due to the reduction of the de-stress cycle
time ($tDSC$), which is achieved by de-stressing the logic blocks in a bank’s
peripheral circuitry independently and in parallel to ongoing read and write
requests to the bank.

###  7.4. Effect of Aging Threshold

Figure 11 reports the execution time and aging of each of our workloads using
HEBE, normalized to Baseline. The height of a bar represents HEBE’s result
with the default aging threshold of 1000 units. An error bar represents the
variation obtained by changing the aging threshold from 500 units to 2000
units. We make the following observation.

Figure 11. Execution time and aging of HEBE, normalized to Baseline, as a
function of the aging threshold.

When we set a stricter aging threshold (e.g., 500 units), execution time
increases and aging decreases. This is because when the aging threshold is
lowered, the high-voltage exposure time of the peripheral circuitry in each
memory bank reduces, reducing the accrued aging. However, performance degrades
due to the high de-stress overhead (see Eq. 1). Conversely, when we relax the
aging threshold (e.g., 2000 units), the de-stress interval increases, reducing
the de-stress overhead and increasing performance. However, aging is now
higher because of longer exposure to high-voltage stress.

###  7.5. Temperature Dependency

Figure 12 plots MTTF of Decoupled-HEBE at 300K, 325K, and 350K normalized to
Baseline at 300K for each evaluated application. We observe that MTTF
decreases with increase in temperature. MTTF at 325K and 350K are higher than
at 300K by an average of 7% and 26%, respectively. These results follow
directly from our aging formulation, which incorporates temperature using the
scaling parameter $\alpha$ in Eq. 5. This parameter grows exponentially with
temperature, resulting in a corresponding exponential increase in aging. More
aging leads to larger shift in threshold voltage.

Figure 12. MTTF at 325K and 350K normalized to Baseline.

##  8\. Related Works

To our knowledge, this is the first work that exploits a workload’s access
characteristics to _dynamically_ control the length of the de-stress interval
of peripheral circuitry in each memory bank, improving both performance and
MTTF of PCM-based main memory. Many works propose optimizations for PCM.
Recent examples include architecture optimization (Qureshi et al., 2009; Lee
et al., 2009; Yavits et al., 2020), performance and energy optimization (Yoon
et al., 2012, 2014; Song et al., 2019, 2020b; Kim et al., 2019a; Arjomand et
al., 2016), wear leveling (Song et al., 2020a; Zhang and Sun, 2017; Zhang et
al., 2018), and memory controller optimizations (Zhao et al., 2014). See (Xia
et al., 2015) for a survey of these and other similar approaches. HEBE can be
combined with most of these techniques.

Many works propose memory latency reduction, refresh optimization, energy
reduction, and request scheduling methods to enhance system performance,
fairness, quality of service, or security (Ren et al., 2015; Seshadri et al.,
2015; Subramanian et al., 2014, 2016; Chang et al., 2017; Khan et al., 2016;
Chang et al., 2016; Liu et al., 2012; Usui et al., 2016; Ausavarungnirun et
al., 2012; Rixner et al., 2000; Chang et al., 2014; Kim et al., 2010a; Mutlu
and Moscibroda, 2008; Kim et al., 2010b; Meza et al., 2012b; Lu et al., 2014;
Pelley et al., 2014; Ipek et al., 2008; Hassan et al., 2016; Lee et al., 2015;
Qureshi et al., 2015; Patel et al., 2017; Deng et al., 2011; David et al.,
2011; Kim et al., 2018a, b, 2019b; Mutlu and Moscibroda, 2007; Nesbit et al.,
2006; Rixner, 2004). None of these works consider aging of phase change memory
in their scheduling decisions. Our aging-aware scheduling mechanism can be
incorporated into other memory controller designs that aim to improve other
metrics.

##  9\. Conclusions

We introduce HEBE, a new mechanism that can dynamically track and control the
aging of transistors in peripheral circuitry of each memory bank, improving
both performance and aging of NVM-based main memory. HEBE is built on three
novel contributions. First, we propose a new, accurate analytical model to
dynamically track aging in response to the memory controller’s request
scheduling decisions. Second, we develop a new, intelligent request scheduler
that exploits this aging model at run time to decide when peripheral circuitry
in NVM must be de-stressed. Third, we decouple logic blocks in peripheral
circuitry operating at different voltages, allowing these blocks to be de-
stressed independently and off the critical path of execution, improving
performance. We evaluate HEBE for DRAM-NVM hybrid main memory and show the
significant performance and MTTF improvement. We conclude that HEBE is a
_simple yet powerful_ mechanism to dynamically manage the aging in non-
volatile main memory, and improve both performance and lifetime via its
intelligent request scheduling decisions.

## Acknowledgments

This work is supported by the National Science Foundation Faculty Early Career
Development Award CCF-1942697 (CAREER: Facilitating Dependable Neuromorphic
Computing: Vision, Architecture, and Impact on Programmability).

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