XX X Year

Corresponding authors. Email<EMAIL_ADDRESS>Equally contributed to this
work.

# Darwin3: A large-scale neuromorphic chip with a Novel ISA and On-Chip
Learning

De Ma1,2,3,4† Xiaofei Jin1,2† Shichun Sun2 Yitao Li1,3 Xundong Wu2 Youneng Hu1
Fangchao Yang2 Huajin Tang1,2,3,4 Xiaolei Zhu5,2 Peng Lin1,3,4 Gang
Pan1,2,3,4∗ 1College of Computer Science and Technology, Zhejiang University,
Hangzhou 310058, China  2Research Center for Intelligent Computing Hardware,
Zhejiang Lab, Hangzhou 311121, China  3The State Key Lab of Brain-Machine
Intelligence, Zhejiang University, Hangzhou 310027, China  4MOE Frontier
Science Center for Brain Science and Brain-machine Integration, Zhejiang
University, Hangzhou 310027, China  5College of Micro-Nano College of Micro-
Nano Electronics, Zhejiang University, Hangzhou 311200, China

(XX XX Year; XX XX Year; XX XX Year)

###### Abstract

[ABSTRACT] Spiking Neural Networks (SNNs) are gaining increasing attention for
their biological plausibility and potential for improved computational
efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic
chips are highly desired to execute SNNs in hardware-based neuron and synapse
circuits directly. This paper presents a large-scale neuromorphic chip named
Darwin3 with a novel instruction set architecture(ISA), which comprises 10
primary instructions and a few extended instructions. It supports flexible
neuron model programming and local learning rule designs. The Darwin3 chip
architecture is designed in a mesh of computing nodes with an innovative
routing algorithm. We used a compression mechanism to represent synaptic
connections, significantly reducing memory usage. The Darwin3 chip supports up
to 2.35 million neurons, making it the largest of its kind in neuron scale.
The experimental results showed that code density was improved up to 28.3x in
Darwin3, and neuron core fan-in and fan-out were improved up to 4096x and
3072x by connection compression compared to the physical memory depth. Our
Darwin3 chip also provided memory saving between 6.8X and 200.8X when mapping
convolutional spiking neural networks (CSNN) onto the chip, demonstrating
state-of-the-art performance in accuracy and latency compared to other
neuromorphic chips.

###### doi:

XXX/XXX/XXXX

###### keywords:

neuromorphic computing, spiking neural networks, instruction set architecture,
connectivity compression

##  1 INTRODUCTION

Spiking neural networks (SNNs) have garnered significant attention from
researchers due to their ability to process spatial-temporal information in an
efficient event-driven manner. To exploit the capabilities of SNNs, several
spiking neural network simulation platforms have been introduced, such as
Brian2[1], NEST[2], and SPAIC[3]. Nevertheless, the dependence of these
platforms on using extensive GPU and CPU resources to mimic the spiking
dynamics with a high count of timing steps potentially diminish the intrinsic
advantages of SNNs. Neuromorphic chips are designed for efficient execution of
spiking neural networks, which have demonstrated promising performance in
brain simulation and specific ultra-low power scenarios. However, several
limitations prevent them from fully leveraging the advantages of spiking
neural networks. To better leverage the benefits of the SNN models, we should
emphasize the three aspects when designing neuromorphic chips:

Flexibility of Neural Models: One of the key functions of neuromorphic chips
is to simulate diverse biological neurons and synapses. However, many
neuromorphic chips only support a single type of neuron model, as evidenced in
platforms like Neurogrid[4], which is based on analog neuron circuits. Some
works introduce a degree of configurability to accommodate various neuron
models. Loihi[5] achieved enhanced learning capabilities through configurable
sets of traces and delays. FlexLearn[6] has conceived a versatile data path
that amalgamates key features from diverse models. Moreover, endeavors have
been undertaken to develop fully configurable neuronal models using
instructions. SpiNNaker’s multi-core processors[7], based on conventional ARM
cores, provide significant flexibility. However, it is associated with reduced
performance and energy efficiency compared to other accelerators. While
Loihi2[8] presents an instruction set incorporating logical and mathematical
operations similar to RISC instructions. However, instruction sets designed
for conventional neural networks lack efficiency for SNNs despite their
flexibility.

Synapse Density: To further unlock the potential of SNNs, neuromorphic chips
need to support the representation of large-scale SNNs with more complex
topologies[9]. However, current neuromorphic chips pay less attention to this
aspect, primarily concentrating on simulating the behavior of neurons and
synapses. For instance, TrueNorth[10] employs a crossbar design for synaptic
connections, but it suffers from limited and fixed fan-in/fan-out capacity.
Loihi [5] takes an approach by using axon indexes to encode topology, thereby
enhancing flexibility. Loihi2 [8] proposes optimizing for convolutional and
factorized connections but gives less attention to other connection types.
Unicorn [11] introduces a technique for merging synapses from multiple cores
to extend the synaptic scale of a single core. Thus, improving synapse density
for various topologies under limited storage conditions is crucial for
optimizing the cost-effectiveness of the chip.

On-chip Learning Ability: Learning capability is a critical feature of
biological neural networks. Currently, only a few neuromorphic chips support
on-chip learning. Among those, the supported learning rules are pretty
restricted. For instance, BrainscaleS2[12] only accommodates fixed learning
algorithms. Loihi[5] supports programmable rules for pre-, post-, and reward
traces. Loihi2[8] extends its capabilities of the programmable rules applied
to pre-, post-, and generalized ”third-factor” traces. However, even with the
enhanced flexibility exhibited by Loihi2[8], it cannot accommodate novel
learning rules that might emerge. The latest research achievements in the
field of electrochemical memory array[13] also provide new reference
solutions.

In this paper, we design a large-scale neuromorphic chip with a domain-
specific Instruction Set Architecture (ISA), named Darwin3, to support model
flexibility, system scalability, and on-chip learning capability of the chip.
Darwin3 is the third generation of our Darwin [14] family of neuromorphic
chips, which was successfully taped out and lit up in December 2022. Our main
contributions are as follows.

1) We propose a domain-specific instruction set architecture (ISA) for
neuromorphic systems, capable of efficiently describing diverse models and
learning rules, including the integrate-and-fire (LIF) family[15],
Izhikevich[16], and STDP[17], among others. The proposed architecture excels
in achieving high parallelism during computational operations, including
loading parameters and updating state variables such as membrane potential and
weights.

2) We design a novel mechanism to represent the topology of SNNs. This
mechanism effectively compresses the information required to describe synaptic
connections, thereby reducing overall memory usage.

The article is organized as follows: Firstly, we introduce the topic and
briefly overview the article’s contents. Second, we present the neuromorphic
computing domain-specific ISA. Then, we offer the overall architecture of the
neuromorphic chip and the implementation of each part, including the
architecture of neuron nodes and the mechanism of topology representation.
Lastly, we demonstrate the experiment results.

##  2 THE DARWIN3 DOMAIN-SPECIFIC ISA

###  2.1 Model Abstraction of Neurons, Synapses, and Learning

Many neuron models have been proposed in the field of computational
neuroscience. The leaky integrate-and-fire (LIF) family[18][19][20][15] is a
group of spiking neuron models that can be described by one or two-dimensional
differential equations and were widely implemented on hardware accelerators.
These models have been developed for use in many real-world applications
various applications. The Hodgkin-Huxley model[21][22] is considered
biologically plausible and accurately captures the intricacies of neuron
behavior with four-dimensional differential equations that represent the
transfer of ions across the neuron membrane. However, this model can cause
very high computational costs. The Izhikevich model[16], specifically designed
to replicate bursting and spiking behaviors observed in the Hodgkin-Huxley
model, is represented with two-dimensional differential equations.

All these neuron models are represented using systems of differential
equations, with variations occurring only in the number of equations and the
variables and parameters in each equation. The primary operators needed to
solve them are the same. Therefore, it can be a practical approach to identify
the common features shared by complex LIF models and utilize them to construct
more complex models by introducing additional state variables and computation
steps. We chose the Adaptive Leaky Integrate-and-Fire (AdLIF) model[20] as the
baseline with relatively more variables and parameters. Mathematically, it can
be expressed by Equation2.1, which captures the dynamics of the model and its
adaptation properties.

$\displaystyle{}{\tau_{m}}\frac{{d{v_{m}}}}{{dt}}=-({v_{m}}-{E_{L}})-\frac{1}{g}({v_{adp}}-I)$
$\displaystyle{\tau_{adp}}\frac{{d{v_{adp}}}}{{dt}}=a({v_{m}}-{E_{L}})-{v_{adp}}$
(1) $\displaystyle if({v_{m}}>{v_{th}}):{v_{m}}={v_{0}},{v_{adp}}={v_{adp}}+b$

Where $v_{m}$ is the membrane potential, $\tau_{m}$ is the membrane time
constant, $E_{L}$ is the leak reversal potential, $g$ is synapse conductance,
$v_{adp}$ is adaptation current, $\tau_{adp}$ is time constant of the
adaptation current, $a$ is the sensitivity to the sub-threshold fluctuations
of the membrane potential, $b$ is the increment of $v_{adp}$ produced by a
spike,$v_{0}$ is the reset potential after spike and $I$ is synaptic spike
current.

Similar to the various designs of neuron models with different computational
complexity, there are also multiple synapse models, such as the delta and
alpha synapse models[23]. One of the complex and commonly used models is the
conductance-based(COBA) dual exponential model[24][23], as shown in Equation
2.1, which has a similar computational complexity to that of Equation 2.1. We
chose this model as our representative synapse model.

$\displaystyle{}\frac{{dh}}{{dt}}=\frac{{-h}}{{{\tau_{rise}}}}+\delta({t_{0}}-t)$
$\displaystyle\frac{{dg}}{{dt}}=\frac{{-g}}{{{\tau_{decay}}}}+h$ (2)
$\displaystyle I=g({v_{m}}-{E_{L}})$

Where $\delta$ is a spike at time $t_{0}$, $h$ is the gating variable of the
ion channel, $g$ is synapse conductance, $\tau_{decay}$ is the time constant
of the synaptic decay phase, $\tau_{rise}$ is the time constant of the
synaptic rise phase, $I$ is synaptic spike current, $v_{m}$ is the membrane
potential and $E_{L}$ is the leak reversal potential.

Synaptic plasticity[25], the ability of synapses to change their strength, was
first proposed as a mechanism of learning and memory by Donald Hebb[26]. After
that, numerous learning rules have been proposed ever since. The STDP
rule[17], and their variants are the most widely used. One relatively complex
variant considers triplet[27] interactions and is reward-modulated[28]. We
select this model as the baseline, and through the selection of different
state variables and parameters, the same equation can describe most STDP and
its variant rules. The rule can be expressed mathematically as Equation 2.1.

$\displaystyle{}{\tau_{pre_{0}}}\frac{{d{x_{0}}}}{{dt}}=-{x_{0}}+{a_{pre_{0}}}\delta(t-{t_{pre_{0}}})$
$\displaystyle{\tau_{post_{0}}}\frac{{d{y_{0}}}}{{dt}}=-{y_{0}}+{a_{post_{0}}}\delta(t-{t_{post_{0}}})$
$\displaystyle{\tau_{post_{1}}}\frac{{d{y_{1}}}}{{dt}}=-{y_{1}}+{a_{pos{t_{1}}}}\delta(t-{t_{post_{1}}})$
$\displaystyle{\tau_{rwd}}\frac{{dr}}{{dt}}=-r+{a_{rwd}}\delta(t-{t_{rwd}})$
(3) $\displaystyle dw(t)={A_{pre}}r{x_{0}}(t)\delta(t-{t_{pos{t_{0}}}})$
$\displaystyle-{A_{pos{t_{0}}}}r{y_{0}}\delta(t-{t_{pre}})-{A_{pos{t_{1}}}}r{y_{1}}\delta(t-{t_{pre}})$

Where $x_{0}$ is the pre-synaptic spike trace, $y_{0}$ is the first post-
synaptic spike trace, $y_{1}$ is the second post-synaptic spike trace, $r$ is
the reward to modulate the synaptic traces, $\tau_{*}$ are time constants of
$x_{0}$, $y_{0}$, $y_{1}$ and $r$.

Equations 2.1 to 2.1 described three representative models. To implement the
models using digital circuits, we need to convert the differential equations
to a discrete form. By applying the Euler method, Equations 2.1 and 2.1, are
converted to Equation 2.1 and 2.1.

$\displaystyle{}v(t+1)={p_{0}}v(t)+{p_{1}}I(t+1)+{p_{2}}{v_{adp}}(t+1)+{c_{0}}$
$\displaystyle{v_{adp}}(t+1)={p_{3}}{v_{adp}}(t)+{p_{4}}v(t)+{c_{1}}$ (4)
$\displaystyle
if(v(t+1)>{v_{{\rm{th}}}}):\left\\{\begin{array}[]{l}v(t+1)={v_{0}}\\\
{v_{adp}}(t+1)={v_{adp}}(t+1)+{c_{2}}\end{array}\right.$
$\displaystyle{}h(t+1)={p_{8}}h(t)+{w_{ij}}{\rm{H}}[t-{t^{s}}]$ $\displaystyle
I(t+1)={\rm{g}}(t+1)v(t)+{p_{7}}g(t+1)$ (5) $\displaystyle
g(t+1)={p_{5}}g(t)+{p_{6}}h(t+1)$

Where $p_{0}$ to $p_{7}$ are fixed coefficient parameters, $c_{0}$ to $c_{2}$
are constants. Similarly, Equation 2.1 can be converted to the form shown in
Equation 2.1.

$\displaystyle{}{x_{0}}(t+1)=P_{3}^{*}x(t)+C_{0}^{*}{x_{2}}(t)$
$\displaystyle{y_{0}}(t+1)=P_{4}^{*}{y_{0}}(t)+C_{1}^{*}{y_{2}}(t)$
$\displaystyle{y_{1}}(t+1)=P_{5}^{*}{y_{1}}(t)+C_{2}^{*}{y_{2}}(t)$
$\displaystyle{r_{0}}(t)=P_{6}^{*}{r_{0}}(t)+C_{3}^{*}{r_{2}}(t)$ (6)
$\displaystyle w(t+1)=w(t)+P_{0}^{*}{r_{0}}(t){x_{0}}(t){y_{2}}(t)$
$\displaystyle+P_{1}^{*}{r_{0}}(t){y_{0}}(t){x_{2}}(t)+P_{2}^{*}{r_{0}}(t){y_{1}}(t){x_{2}}(t)$

Where $P_{0}^{*}$ to $P_{6}^{*}$ are fixed coefficient parameters, $C_{0}^{*}$
to $C_{3}^{*}$ are constants.

Equations 2.1, 2.1, and 2.1 reveal that both complex LIF models and STDP
variants can be expressed as polynomials involving multiple multiplication and
addition operations. To implement these polynomial computations in digital
circuits, we map them to corresponding data paths for further analysis. Figure
1 (a) (b) and (c) illustrates that the data paths of $v_{adp}$, and $v_{m}$ in
Equations 2.1, 2.1 and $w$ in Equation 2.1 are almost identical, except for
different control signals from selectors and input sources, which allows us to
efficiently implement these computations in circuits using a unified data
path, where parameters can be pre-configured statically, and state variables
are updated continuously over time steps. For more complex cases such as
Izhikevich model[16], the parameter that multiplies the state variables in the
computation process is also a state variable. Therefore, we obtain the unified
data path shown in Figure 1 (d).

(a)  (b)  (c)  (d)

Figure 1: Typical Data Path. (a) The Data Path of $v_{adp}$. (b) The Data Path
of $v_{m}$. (c) The Data Path of $w$. (d) The Common Data Path for State
Variables. Table 1: Registers and Instruction Set

(a) Registers for State Variables and Parameters
Name Description Name Description $v_{m}$, $S_{0}$ The membrane potential
$X_{0}$-$X_{1}$ Two presynaptic spike traces $LS_{0}$-$LS_{1}$ g, $S_{1}$ The
synaptic conductance $X_{2}$ Flag for spike from pre-synapse $L_{2}$ I,
$S_{2}$ The synaptic current $Y_{0}$-$Y_{1}$ Two postsynaptic spike traces
$LS_{3}$-$LS_{4}$ h, $S_{3}$ The gating variable $Y_{2}$ Flag for spike from
post-synapse $LS_{5}$ $v_{adp}$, $S_{4}$ The adaptive voltage $R_{0}$-$R_{1}$
traces to do reward and punishment $LS_{6}$-$LS_{7}$ $v_{th}$, $S_{5}$ The
threshold voltage $R_{2}$ Reward and Punishment $LS_{8}$ w The synaptic weight
$LP_{0}$-$LP_{7}$ Eight parameters for learning stage, corresponding to
$P^{*}$ in Equation 2.1 $v_{0}$ The reset membrane potential value
$LC_{0}$-$LC_{7}$ Eight constants for learning stage, corresponding to $C^{*}$
in Equation 2.1 $IP_{0}$-$IP_{7}$ Eight parameters for inference stage,
corresponding to $p_{0}$-$p_{7}$ in Equations 2.1 and 2.1 $TR_{0}$-$TR_{7}$
Temporary registers for parameters and states $IC_{0}$-$IC_{2}$ Three
constants for inference stage, corresponding to $c_{0}$-$c_{2}$ in Equation
2.1 and 2.1 - -

(b) Neuromorphic Specific Instruction Set
Opcode (5 bits) Operand (11 bits) LSIS LS (1-bit) Reserve NHIS (6-bit) LS
indicates whether an operation is a load or store operation, and NHIS is a
6-hot code corresponding to the state variables $S_{0}$-$S_{5}$, indicating
whether each state variable needs to be loaded or stored during the operation.
LDIP NHIP(8-bit) NHIC(3-bit) NHIP is an 8-hot code corresponding to the
parameters $p_{0}$-$p_{7}$, and NHIC is a 3-hot code corresponding to
$c_{0}$-$c_{2}$, indicating whether each needs to be loaded during the
operation. LSLS LS(1-bit) NHLS(10-bit) A one hot code LS bit indicates whether
an operation is a load or store operation, and a 10-hot code NHLS
corresponding to the state variables $LS_{0}$ to $LS_{9}$ indicates whether
each state variable needs to be loaded or stored during the operation. LDLP
NHLP(7-bit) NHLC(4-bit) A 7-hot code NHLP corresponding to the parameters
$LP_{0}$-$LP_{6}$ and a 4-hot code NHLC corresponding to $LC_{0}$-$LC_{3}$,
indicate whether each parameter needs to be loaded during the operation. UPTIS
Reserve OHIS (3-bit) NHIP (6-bit) OHIS is a one-hot code indicating whether
$I$, $g$, or $v_{adp}$ to be calculated and NHIP is a 6-hot code corresponding
to $p_{3}$-$p_{7}$ and $c_{1}$, indicating whether each needs to participate
in the calculation according to Equation 2.1 and 2.1. UPTVM Reserve
NHVM(4-bit) NHVM is a 4-hot code to determine whether $v_{m}$, $I$, $v_{adp}$,
or $c_{0}$, needs to participate in the calculation to update $v_{m}$
according to Equation 2.1 and 2.1. UPTLS k(3-bit) l(3-bit) m(3-bit) n(2-bit)
The variables k, l, m, and n determine the selected state variable $LS_{k}$
that needs to update according to the equation:
$LS_{k}$(t+1)=$LP_{l}$*$LS_{m}$(t)+$LC_{n}$. UPTWT m(2-bit) n(9-bit) A binary
code m and n-hot code n determine the synaptic weight to update according to
the equation: WT(t+1)=WT(t)+$L{P_{m}}\prod\limits{L{S_{n}}}$. UPTTS k(3-bit)
l(3-bit) m(3-bit) n(2-bit) The variables k, l, m, and n determine the selected
temporary state variable $RT_{k}$ that needs to update according to the
equation: $RT_{k}$(t+1)=$P_{l}$*$S_{m}$(t)+$C_{n}$. GSPRS Reserve NHSP(4-bit)
A 4-hot code NHSP respectively determines whether to fire a spike, whether to
perform threshold comparison, whether to involve adaptive operation, and
whether membrane potential needs to reset to $v_{0}$.

(c) Extended Instruction List
Type Instructions Type Instructions Arithmetic ADD SUB MUL ADDI Jump CMP JMP
Bitwise SHIFT LOGIC Memory SA, TS, LOAD/PUSH STORE/POP SP Move MOV WMOV Pseudo
DIV EXP

###  2.2 The Proposed Darwin3 ISA

To effectively manage the data path and maximize performance and concurrency,
it is crucial to design an efficient controller. First, we map state variables
and parameters into a set of registers, as indicated in Table 1(a). It covers
the state variables and parameters related to neurons and synapses, in which
constants are static parameters. To provide users with the flexibility to
implement different models, we propose a specialized instruction set
architecture (ISA), as shown in Table 1 (b).

The core principle of this ISA is to amalgamate common operations into a
single instruction, taking into account the computational characteristics of
SNNs. By doing so, it not only reduces the memory usage required for
instructions but also minimizes the time needed for instruction decoding
during the computation process. We defined a set of instructions outlined in
Table 1 (b). This instruction set comprises ten primary commands. The first
group, which focuses on load and store operations, consists of LSIS, LDIP,
LSLS, and LDLP. Specifically, LSIS and LSLS cater to loading or writing back
state variables for both the inference and learning processes, executed in
parallel. On the other hand, LDIP and LDLP are designated for loading
parameters in parallel for inference and learning phases, respectively.

The second group, tailored for updating state variables, includes UPTIS,
UPTVM, UPTLS, UPTWT, and UPTTS. Among these, UPTIS updates state variables,
excluding the membrane potential. UPTVM is exclusively for adjusting the
membrane potential. UPTLS emphasizes state variables specific to the learning
stage, while UPTWT manages the adjustments of synaptic weights. UPTTS oversees
the updating of temporary state variables. Lastly, the GSPRS instruction is
dedicated to generating spikes. With these instructions, we can effectively
manage the computing units and support the process required for constructing
flexible SNN models.

Models such as AdEx[20] and HH[21] necessitate intricate operations, including
exponential and division functions. These are not directly supported by the
instructions outlined in Table 1 (b). The design enables users to perform
division and exponentiation operations using computational units like shift,
multiplication, and lookup tables, thus conserving hardware resources.
Consequently, we’ve augmented our instruction set with several instructions
typically found in reduced instruction set architectures, as detailed in Table
1 (c).

In Table 2, we present a range of code examples beyond basic loading and
storing operations to illustrate the efficacy of the proposed ISA. This
selection demonstrates that simple LIF models and more complex Triplet STDP
rules can be concisely represented using minimal instructions. Additionally,
specialized rules such as SDSP[29] can be efficiently encoded through a
strategic combination of instructions. This versatility underscores the high
flexibility and effectiveness of our instruction set design, establishing it
as a viable tool for researchers and developers engaged in implementing
diverse models in SNNs.

Table 2: Code Examples for Widely Used Models

Model | Code | Model | Code
---|---|---|---
LIF  | [18]
---
| UPTVM 0xD
---
GSPRS 0xA
Basic STDP  | [17]
---
| UPTLS 0x20
---
UPTLS 0x08
UPTWT 0x108
UPTWT 0x260
QIF  | [15]
---
| UPTTS 0x021
---
MOV P0, RT0
UPTVM 0xD
GSPRS 0xA
Triplet STDP  | [27]
---
| UPTLS 0x20
---
UPTLS 0x08
UPTLS 0x04
UPTWT 0x10C
UPTWT 0x264
UPTWT 0x454
ExpIF  | [15]
---
| UPTTS 0x061
---
EXP RT1 RT0
UPTTS 0x48A
MOV C0 RT2
UPTVM 0xD
GSPRS 0xA
RSTDP  | [28]
---
| UPTLS 0x20
---
UPTLS 0x08
UPTLS 0x02
UPTWT 0x10C
UPTWT 0x264
Izhikevich  | [16]
---
| UPTTS 0x143
---
MOV P0, RT0
UPTIS 0x38
UPTVM 0x0F
GSPRS 0xE
S-TP  | [30]
---
| LayerH:
---
UPTTS 0x15A
MOV LP0 RT0
UPTWT 0xC0
LayerO:
UPTWT 0x228
- | - | SDSP  | [29]
---
| UPTLS 0x20
---
CMP RT0 S0
JMP Keep
CMP RT1 LS1
JMP Keep
CMP LS1 RT3
JMP Keep
CMP LS1 RT2
JMP UP
SUB W RT4
NOP
Up: ADD W RT4
Keep: NOP

##  3 THE DARWIN3 CHIP ARCHITECTURE

###  3.1 Overview

The Darwin3 chip architecture is characterized by a two-dimensional mesh of
computing nodes, forming a 24*24 grid, interconnected via a Network on Chip
(NoC), shown in Figure 2(a). The node at position (0,0) features a RISC-V
processing core for chip management, while the other nodes, functioning as
neuron cores, handle the majority of computations, with each supporting up to
4096 spiking neurons. Inter-chip communication modules are placed at four
edges of the chip connected with peripheral routers, acting as compression and
decompression units. This design enables the NoC to extend connections to
other chips in all four cardinal directions, enhancing system scalability.

This work implements a low-latency NoC architecture, which employs XY routing
as detailed in [31]. The design is further improved by integrating the CXY
[32] and OE-FAR [33] routing strategies to tackle congestion issues.
Additionally, a new routing algorithm is introduced in this work that uses the
relative offsets between the source and destination addresses as the basis for
its routing scheme. This strategic decision simplifies the data packet
transmission process to neighboring chips, eliminating the need for complex
routing protocols and address translation.

The asynchronous communication interfaces, denoted by green circles in the
figure, interconnect local synchronous modules, establishing Darwin3 as a
global asynchronous local synchronous system. This enhances the capability of
each node on the chip to operate independently at a high-performance level.

(a)  (b)

(c)  (d)

Figure 2: The Architecture of The Chip Top and Main Blocks. (a) The Top
Architecture of The Proposed Chip. (b) The Architecture of a Neuron Core. (c)
The Architecture for Inference and Learning Process. (d) The Architecture of
The Synapses.

###  3.2 Architecture of Neuron Cores

The architecture of a neuron core, illustrated in Figure 2 (b), comprises five
components: the controller unit, the model execution unit, the time management
unit, the register and memory units, and the spike event processing unit.

The controller unit is responsible for fetching, decoding, and executing flow
control. The model execution unit can perform various arithmetic and logical
operations. As defined in Table 1 (a), registers store state variables,
parameters, constants, and temporary variables.

The time management unit has two primary responsibilities. First, it generates
an internal tick signal based on global time-step information, indicating the
progression of time steps within the core. Second, it implements time-division
multiplexing for 1-4096 logical neurons based on configuration information.

Each neuron core has memories for different things like axon-in, axon-out,
neuron state variables, synapse state variables, and instructions.
Instructions are only used to describe how neurons and synapses work. The
neuron’s ID determines the address of instructions and related state
variables. The memories for axon-in and axon-out store how neurons are
connected, and their organization is shown in Figure 2 (d). When the chip
starts, we need to set up the memories for the working nodes. Configuration
data will be transported from the external controller (e.g., a PC or an FPGA)
to the corresponding nodes through the Inter-Chip Communication module.

Unlike conventional processors that fetch instructions in every cycle using a
clock, Darwin3’s neuron cores are driven by spike events. When a neuron gets a
spike, AER IN queries the corresponding axon-in entry to find the neuron ID
and weight, calculating the state variable h. When a time step advances, the
controller unit performs computations for each neuron’s inference or learning
stage based on the instructions. And if a neuron fires a spike, the AER OUT
gets the address and ID of the post-synaptic neuron from the axon-out,
packaging this into a spike data packet.

The dashed lines in Figure 2 (b) illustrate the process of a neuron core
receiving, processing, generating, and transmitting spikes. Multiplication
operations take two cycles, while addition operations take one cycle. For
example, the commonly used LIF neuron model requires four cycles (two
multiplication and two addition operations), while the CUBA Delta model
requires three cycles (one multiplication and one addition operation).
Transmission delay is expressed as 2*N + 2*(N+1), where 2*N is for delay
through N routers, and 2*(N+1) is for delay through N+1 asynchronous
interconnections between pre-synaptic and post-synaptic neurons.

Figure 2 (c) shows the architecture tailored for inference and learning based
on the proposed ISA. In the inference mode, the controller unit updates the
state variables of each neuron described by the instructions within the
current time step. In the learning mode, the controller unit extracts learning
parameters and state variables to execute necessary calculations and updates,
calculating new weights. The axon-in memory area has been reconfigured to
accommodate learning-related parameters and state variables to optimize
hardware resources.

###  3.3 Representation of Neuronal Connections

A flexible connection representation mechanism is essential in pursuing the
development of neuromorphic computing chips capable of supporting complex
networks. Several connection topologies find frequent application in SNNs:

  1. 1.

Multiple neuron groups connect to a group of neurons, similar to the
Convolutional Neural Network (CNN) arrangement with shared weights.

  2. 2.

A single neuron connects to an entire group of neurons.

  3. 3.

A group of neurons fully connect to another group of neurons.

Upon a comprehensive examination of commonly employed connection expression
mechanisms (as summarized in Table 3), we discovered that the approach used by
Loihi[5] stands out for its exceptional flexibility, featuring substantial
fan-in and fan-out capability. Combining these advantageous attributes, we
have introduced a novel scheme that enables a highly compressed representation
of connection topology, as depicted in Figure 2 (d). To efficiently represent
the topology of connections, each neuron core has independent memories for
axon-out and axon-in within this framework.

Spikes are conveyed utilizing the address-event representation (AER) method.
Following the generation of a spike by a pre-synaptic neuron, it accesses
axon-out to retrieve the target node’s address and axon-in index information
of the target node. Subsequently, the AER OUT module encapsulates and
transmits this information to the router through the local connection port.
The router, in turn, directs the data packet towards the designated target
node. Upon reception of the data packet, the target node queries axon-in to
acquire pertinent information concerning the target neuron and connection
weights.

Within the framework of the axon-out structure, each operational neuron is
associated with a Linker. The Linker’s entries retain the address of the entry
containing detailed connection information and the specific index of the
neuron. This index distinguishes cases in which multiple neurons are connected
to the same target node. This structural configuration optimizes the
compression of information for connection types extending beyond point-to-
point scenarios:

  1. 1.

The last flag (LF) is set to 0 when a neuron connects to multiple nodes,
indicating non-terminal nodes and facilitating efficient compression of
redundant information. As shown in Figure 2 (d), the situation is represented
by $1{{}^{\\#}}$.

  2. 2.

When multiple neurons connect to the same node(s), a single entry suffices for
their connectivity information. As shown in Figure 2 (d), the situation is
represented by $2{{}^{\\#}}$.

Table 3: Different Connectivity Mechanisms

Connectivity mechanism | Max. fan-in/core | Max. fan-out/core
---|---|---
Crossbar[10] | C | R
Normal index[6] | D1 | D2
Synaptic expansion[11] | D1 | D2*M
Population-based index[5] | D1*N | D2
Flexible compression for Darwin3 | (D1-1)*N | (D2-N)*N
$D_{1}$ represents fan-in memory depth (commonly associated with axon-in
structures), $D_{2}$ represents fan-out memory depth (commonly linked to axon-
out structures), M represents the number of neuron cores, and N represents the
number of neurons within a neuron core. R and C represent the dimensions of
the crossbar, with R being equivalent to $D_{1}$ (rows) and C being equivalent
to $D_{2}$ (columns).

Each received axon-in index aligns with a corresponding Linker within the
axon-in structure context. The entries in the Linker encapsulate the address
of the entry, housing detailed connection information and the type of
connection. This structure is strategically designed to optimize information
compression, particularly tailored for connection types extending beyond
point-to-point scenarios:

  1. 1.

When all 4096 neurons within the node are connected to one pre-synaptic
neuron, there is no necessity to store neuron indexes individually. In such
cases, 4096 weights can be stored sequentially. As depicted in Figure 2 (d),
the case is denoted by $1{{}^{*}}$.

  2. 2.

In instances where multiple neurons are connected to a specific neuron within
the node and share the same weights, storing a single neuron index along with
the corresponding weight suffices. As depicted in Figure 2 (d), the case is
denoted by $2{{}^{*}}$.

  3. 3.

When neurons from a remote cluster are connected to a group of neurons within
the target node, it is necessary to have only one instance of neuron indexes,
and weights can be stored systematically based on the order of the source
neurons. As depicted in Figure 2 (d), the case is denoted by $3{{}^{*}}$.

  4. 4.

When the target neurons are organized sequentially, it becomes sufficient to
store only the index of the initial neuron and the count of the target
neurons, further reducing storage demands. As depicted in Figure 2 (d), the
case is denoted by $4{{}^{*}}$.

This structure also facilitates the incorporation of weights with different
bit widths, allowing diverse weights to be accommodated within a shared entry,
consequently improving storage density.

Table 4:  Performance and Specifications of State-of-The-Art Neuromorphic
Chips

Chip name |  Neurogrid [4] |  DYNAPs [34] |  Brainscales2 [12] |  SpiNNaker [7] |  SpiNNaker2#1 [35] |  TrueNorth [10] |  Loihi [5] |  FlexLearn[6] |  ISSCC 2019 [36] |  ODIN [37] |  Loihi2 [8] |  Unicorn [11] |  ANP-I [30] |  Darwin3
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---
Implementation |  Mixed |  Mixed |  Mixed |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital |  Digital
Technology(nm) |  180 |  180 |  65 |  130 |  22 |  28 |  14 |  45 |  65 |  28 |  7#2 |  28 |  28 |  22
Die area(mm2) |  - |  43.79 |  - |  102 |  8.76 |  430 |  60 |  410.5 |  10.08#3 |  - |  31 |  500 |  1.628 |  358.527
Neuron cores |  |  4 |  4 |  18 |  8 |  4k |  128 |  128 |  1 |  1 |  128 |  36 |  64 |  575
Neurons per core |  64k |  256 |  128 |  Programmable |  Programmable |  256 |  max. 1k |  max. 35 |  400 |  256 |  max. 8k |  1k |  8 |  max. 4k
Fan in/out per core |  |  64/4k |  512/256 |  Programmable |  Programmable |  256/256 |  4k-4M/4k |  - |  - |  - |  -#4 |  256-256k/- |  - |  28k-256M /12k-48M
Synaptic weight |  4-bit |  12-bit |  6-bit |  Programmable |  Programmable |  1-bit |  1- to 9-bit |  - |  14-bit |  3-bit |  1- to 9-bit |  4-bit |  8,10-bit |  1/2/4/8/16-bit
Neuron models |  LIF |  AdEx-IF |  AdEx-IF |  Programmable |  Programmable |  LIF |  LIF |  configurable |  - |  LIF |  Programmable |  LIF |  LIF#5 |  Programmable
Synapse models |  COBA Delta |  COBA NMDA |  CUBA/COBA Alpha |  Programmable |  Programmable |  CUBA Delta |  CUBA Delta |  configurable |  CUBA Delta |  CUBA Delta |  - |  CUBA Delta |  CUBA Delta |  Programmable
On-chip learning |  No |  No |  STP/STDP/R-STDP |  Programmable |  Programmable |  No |  STDP based |  configurable |  Mod.SD |  SDSP |  Programmable |  No |  S-TP |  Programmable
Energy per SOP |  941pJ @3.0V |  417fJ[38] @1.8V |  - |  11.3nJ[39] @1.2V |  10pJ @0.5V |  26pJ[40] @0.775V |  23.6pJ#6 @0.75V |  - |  - |  8.4pJ @0.55V |  - |  - |  1.5pJ @0.56V |  5.47pJ @0.8V
|  |  |  |  |  |  |  |  |  |  |  |  |  |
#1 Darwin3 allows nodes to operate at different frequencies, with internal
modules typically running at 300-400MHz. #2 A test chip contains 2 QPEs with 8
PEs, while a full SpiNNker2 has 38 QPEs with 152 PEs. #3 Loihi2 has been
implemented in Intel 4, equivalent to the 7nm process. #4 This data is
obtained through a digital synthesis flow, not from the final silicon tape-out
data. #5 Loihi2’s “Axon Routing”, which refers to fan-out or fan-in, has a
topology compression of 256x. #6 Its output layer consists of ten integrate-
and-fire(IF) neurons. #7 A minimum SOP energy of 23.6 pJ at 0.75 V is
extracted from pre-silicon simulations.

##  4 EXPERIMENTAL RESULTS

Figure 3: The Test Chip and System Board

To evaluate the proposed ISA and architecture, we first implemented the entire
architecture in Verilog at the RTL level. Using the GLOBAL FOUNDRIES 22nm
FDSOI process, we generated a GDSII file that meets the sign-off requirements
after completing physical design and verification.

After the initial Chip-on-Board(COB) testing in December 2022, the chip was
repackaged using Flip-Chip BGA, and a dedicated test system board was
assembled, featuring a Xilinx 7-Series FPGA. Figure 3 illustrates the system
board, chip layout, and main blocks. The chip’s structure is organized into a
grid of 6*6 groups, each consisting of 4*4 tiles. Each tile comprises a node
connected to a router. Except for the RISC-V node, all nodes on the chip are
neuron cores, collectively driving their computational functions. Notably, two
distinct tile types exist, primarily differing in the size of their axon-in
memory. We first compare some important metrics with the current state-of-the-
art works, and then we run some application demonstrations to verify the
chip’s functionalities and performance.

###  4.1 Comparison with The State-of-the-Art Neuromorphic Chips

Table 4 summarizes the performance and specifications of state-of-the-art
neuromorphic chips. Mixed-signal designs with analog neurons and synapse
computation and high-speed digital peripherals are grouped on the
left[4][34][12], and digital designs, including Darwin3, are grouped on the
right[7][35][10][5][11][6][8]. The critical metrics for efficient spiking
neuromorphic hardware platforms are the scale of neurons and synapses, model
construction capabilities, synaptic plasticity, and energy per synaptic
operation.

####  4.1.1 Neuron Number

The quantity of neurons and synapses directly determines the size and
complexity of the spiking neural network that a neuromorphic chip can support,
which is extremely important. However, a direct comparison with the SpiNNaker
chips[7][35] is not feasible due to its use of ARM processors, where the scale
is tied to the size of the off-chip memory. Among other chips, NeuroGrid[4]
has the largest number of neurons in a single neuron core, reaching 64K.
Loihi[5], Unicorn[11], Loihi2[8], and Darwin3 are at a similar level, boasting
neuron counts exceeding 1K. At the chip level, Darwin3 can support up to 2.35
million neurons, surpassing the scale of TrueNorth and Loihi2 by more than two
times.

####  4.1.2 Synapse Capacity

The capabilities of fan-in and fan-out within each neuron core profoundly
impact the chip’s overall capacity of synapses, as detailed in Table 3.
Darwin3 distinguishes itself with its adaptive axon-out and axon-in memory
configuration, coupled with efficient compression mechanisms, enabling
remarkable fan-in and fan-out capacities of up to ($D_{1}$-1) * M * N and
($D_{2}$-N) * N2, respectively. In the case of Darwin3, the compression
mechanism yields a maximum fan-in improvement of 1024x and a maximum fan-out
improvement of 2048x when compared to the physical memory depth.

(a)  (b)

Figure 4: Comparison of Code Density and Memory Usage. (a) Comparison of
Required Weight Memory Across Typical Networks. (b) Comparison of Code
Density.

While the previous discussion delved into fan-in and fan-out capabilities,
focusing on the synaptic connectivity potential, the challenge of efficiently
storing synaptic weight parameters remains crucial. In Figure 4 (a), we
present a comparative analysis of weight storage requirements, highlighting
the stark contrast between Darwin3 and existing approaches when applied to
typical networks converted from Convolutional Neural Networks (CNNs). Chips
lacking specialized compression mechanisms exhibit dense weight matrices,
making memory usage 6.8 to 200 times larger than the original approach. In
crossbar designs, neurons consistently occupy their unique space, contributing
to additional inefficiencies.

Darwin3 employs a versatile mechanism by classifying convolutional connections
into weight-sharing multi-to-multi forms and obtains storage parity with the
initial parameters, thereby achieving efficiency comparable to Loihi2[8].
Importantly, this advantage extends to non-convolutional connections featuring
shared weight parameters. Darwin3 enables instructional access to the complete
axon-in, thus realizing the factorized attribute, which is also supported by
Loihi2[8], through multiplication operations. Furthermore, Darwin3 offers
compatibility with diverse weight-bit widths, enhancing its adaptability and
storage efficiency.

Table 5: Performance Comparison with Other Chips

(a) Inference Mode
Platform TrueNorth[41][42] Loihi[43][44] SpiNNaker[39] ReckOn[45] ANP-I[30]
Darwin3 Weight Preciency#1 8-bit 8-bit 16-bit 9-bit 8-bit 8-bit 8,10-bit#2
8-bit 16-bit 8-bit 8-bit#3 8-bit Frequency - - 150 MHz 13MHz 210MHz 333MHz
DateSet MNIST CIFAR-10 MNIST IBM Gesture MNIST IBM Gesture N-MNIST IBM Gesture
MNIST MNIST MNIST IBM Gesture CIFAR-10 Network Topology LeNet Mod. VGG VGG-9
cNet DBN RNN - LeNet VGG-9 RNN cNet Mod. VGG Accuracy 99.40% 83.41% 99.79%
89.64% 95.01% 87.30% 96.00% 92.00% 99.10% 99.79% 87.51% 89.60% 90.17% Latency
5.74ms - 6.13ms - 20ms 15ms - 5.7ms 6.48ms 2.7ms 6.08 ms 9.88ms #1 The weight
precision here refers to the precision of the network run in the experiment
rather than the maximum weight precision of the chip. #2 The synaptic weights
of its ten neurons in the output layer are 10-bit. #3 Darwin3 cannot support
9-bit of weight precision.

(b) Learning Mode
Platform SpiNNaker[39] Loihi[46] ISSCC’2019[36] ODIN[37] ANP-I[30] Darwin3
Frequency 150 MHz - 20 MHz 150 MHz 40 MHz 333MHz DataSet MNIST Learning
Algorithm CD EMSTDP Mod.SD SDSP S-TP RSTDP Weight Preciency #1 16-bit 8-bit
14-bit 3-bit 8-bit#2 16-bit Network Topology 784-500-500-10 - (784)-200-200-10
(256)-10 (1024)-512-10 (784)-100-100-10 Accuracy 95.01% 94.70% 97.83% 84.50%
96.00% 96.00%

####  4.1.3 Code Density

Code density is a meaningful ISA metric, so we compare the code density of
Darwin3 with the SpiNNaker chips[7][35] and Loihi2[8], the outstanding
neuromorphic chips based on ISA. We use the C code to describe a model and the
spinnaker tools integrated by SpyNNaker[47] to generate assembly code for the
SpiNNaker chips. Then, we compare the length of the assembly code in Figure 4
(b). Loihi2’s RISC instruction set is similar to ARM’s Thumb, where spike
instructions aid in curtailing spike-related instruction codes, offering a
slight edge over SpiNNaker. Darwin3 shows an advantage in code density because
of our proposed instructions. This instruction set concurrently loads
parameters and expedites multiplication and addition with multiple parameters.
Impressively, Darwin3 gets a remarkable 2.2x to 28.3x code density advantage
across distinct models.

####  4.1.4 Inference and Learning Performance

For researchers working on SNNs, after finalizing the model, the primary focus
lies on evaluating the chip’s performance during application execution, with
particular attention to latency and accuracy. To evaluate the capabilities of
Darwin3, we conducted several experiments under two distinct scenarios:
inference and learning. Table 5 (b) compares the performance of Darwin3 to
state-of-the-art neuromorphic chips in typical applications. These
applications were SNNs converted from trained and quantified ANNs. We
implemented the same type of network models on Darwin3, and the performance
metrics indicate that Darwin3 is in the leading position regarding accuracy
and latency. The accuracy is up to 6.76% higher, and the latency is up to 4.5x
better than others. Darwin3 exhibits advantages because it has a flexible and
efficient connection construction ability, which is very friendly to the
converted convolutional networks. Due to the high efficiency of connection
storage, it does not increase redundant spike transmission latency. The
asynchronous interconnection method employed by Darwin3 has significantly
reduced the communication delay between neuron cores. Darwin3 utilizes click
elements[48] to construct a cross-clock domain structure, enabling the
completion of cross-clock domain data transfer in just two cycles.
Furthermore, the related topological structures can be split and computed in
parallel with more neuron cores. We attribute the observed discrepancies to
the quantization operations while mapping these models to hardware, and the
quantization methods employed may vary among different approaches. It’s
important to note that there is still room for improving latency performance
by optimizing the mapping approach.

To further evaluate the on-chip learning capability of Darwin3, we constructed
a network based on the architecture proposed by Diehl and Cook[49]. We added a
supervision layer, which provides positive or negative rewards based on
comparing the network’s output and the target during the training process,
achieving the overall implementation of the RSTDP rule. The network was
trained directly on Darwin3 with a weight precision of 16-bit and we achieved
a classification accuracy of 96.0% Table 5 (a) presents the experimental
results compared with prior works, demonstrating that Darwin3 is in the
leading position regarding accuracy. Mod.SD algorithm is hardware-specific and
performs slightly better, while Darwin3 allows flexible construction of
multiple learning rules. We plan to optimize the current learning algorithm or
introduce new ones to improve performance.

####  4.1.5 Energy Efficiency

The energy consumption of each synaptic operation (SOP) is the most critical
energy consumption metric for neuromorphic chips. We measured the energy
consumption of the Darwin3 chip when running a two-layer neural network, where
the neurons in the first layer can fire spikes without inputs, and the neurons
in the second layer receive spikes and perform calculations. We select the
common approach[39] to evaluate energy consumption, as detailed in Equation 7.

$\displaystyle{}P_{total}=P_{I}+P_{B}+(P_{N}*n)+(P_{S}*s)$ (7)

Where $P_{I}$ is the power dissipated by a Darwin3 chip after the power-up
process with no applications configured, $P_{B}$ is the baseline power, which
consists of the power dissipated by all nodes enabled without running any
neurons on it, $P_{N}$ is the power required to simulate a LIF neuron with a 1
ms time-step, n is the total number of neurons, $P_{S}$ is the energy consumed
per synaptic event (activation of neural connections) and s are the total
synaptic events. The chip operates at a frequency 333MHz with a core voltage
supply of 0.8v and an IO voltage supply of 1.8v, as shown in Table 4. The
measured average SOP power consumption is 5.47pj/SOP. This metric is directly
influenced by factors such as the manufacturing process, power supply voltage,
and operating frequency, making fair comparison challenging. However, based on
the data released by prior works under typical scenarios, Darwin3 boasts a
leading achievement. Darwin3’s advantage lies in its internal asynchronous
interconnection circuit, which enables the chip to consume very low power when
there is no spike transmission or calculation. Additionally, all memories of
Darwin3 will shut down during the idle phase, reducing power consumption.

###  4.2 Applications with A Million of Neurons

To further illustrate the chip’s efficacy, we developed two extensive
applications implemented on Darwin3, spiking VGG-16 ensembling and directly-
trained[50] SNN-based maze solving, shown in Figure 5. We ensembled outputs of
five VGG-16 models obtained through ANN2SNN[51] using a voting mechanism[52],
culminating in a composite model comprising approximately 1.05 million neurons
and employing 8-bit weight precision. We applied random transformations to the
input and used five independent VGGs in the hidden layers for the
classification tasks. The voting layer produces the final classification
outcome based on the collective votes from the individual outputs of the
hidden layers. Compared to the original single VGG-16, accuracy testing on the
CIFAR-10 dataset witnessed an increase from 92.98% to 93.48%.

We also developed an application for maze solving. We mapped the maze onto a
set of neurons, where excitatory neurons represent the free-walking grid
points, and inhibitory neurons represent obstacles. The interconnected
excitatory neurons can transmit spikes in sequence, and under the action of
STDP rules, the synaptic weights are continuously increased to form a stable
synaptic strength. However, synapses connected to inhibitory neurons cannot be
strengthened, and the transmission of spikes will be terminated when
encountering inhibitory neurons. After learning, the model can quickly find
the path by observing the path along which the spikes propagate. We conducted
experiments using mazes of different sizes, comparing the time it takes to
search for a path on our chip versus a CPU server. A map of size 15434*1534
requires over 2.35 million neurons, approaching the upper limit of neurons
that Darwin3 can simulate. The result is shown in Table 6. With the STDP-based
SNN method, the time consumed increases linearly with the maze size. In
contrast, the traditional search method on the CPU server consumes a lot of
time because it relies on many recursive operations.

Table 6: Time Cost for Maze Solving Application

Maze Size (Neuron #) |  Time of Intel Xeon Gold 6248R @ 3GHz, 205W (ms) |  Time of Darwin3 @ 400Mz, 1.8W (ms)
---|---|---
63*63 |  83 |  128
125*125 |  296 |  412
250*250 |  1132 |  1375
500*500 |  4744 |  4200
600*600 |  7968 |  6248
700*700 |  11283 |  7706
900*900 |  FAIL |  9654
1534*1534 |  FAIL |  22089
The mazes are randomly generated, and the running time is an average of five
measurements.

(a)

(b)

(c)

Figure 5: Two Large-scale Applications with A Million of Neurons. (a) Spiking
VGG-16 Ensembling. (b) Directly-trained SNN-based Maze Solving.

##  5 CONCLUSION

The article proposes a new instruction set and a connectivity compression
mechanism to create a chip that can support large-scale neural networks. This
chip has been designed to be more efficient in terms of the number of neurons
it can accommodate and its synaptic computing performance, compared to
existing works. The experimental results show that the chip has reached the
same leading level as the state-of-the-art works in terms of accuracy and
latency performance metrics, both for inference and learning modes. The
practical effectiveness of the chip has also been demonstrated by running a
maze-searching application on it.

Due to the chip’s versatile chip communication mechanism, different Darwin3
chips can be integrated onto a single board and interconnect several boards to
configure a big chassis. These chassis can be interconnected through a network
infrastructure to support the construction of extensive SNNs. This
configuration can support the construction of extensive SNNs when coupled with
suitable software frameworks.

##  6 FUNDING

This work is supported by the National Key R&D Plan of China (No.
2022YFB4500100), the National Natural Science Foundation of China (No.
61925603, U20A20220, 62076084), the Key Research Project of Zhejiang Lab (No.
2021KC0AC01), the Key Research and Development Program of Zhejiang Province in
China (No. 2020C03004), the grants from Key R&D Program of Zhejiang (No.
2022C01048).

##  7 AUTHOR CONTRIBUTIONS

G.P. and D. M. proposed the idea. D. M., X. J., S. S., and Y. L. proposed the
chip’s architecture and implemented the design. X. J., S. S., Y. H., F. Y., H.
T., P. L., and X. Z. built the experimental system. D. M., X. J., and S. S.
completed the experiment. D. M., X. J., and X. W. wrote the article. All
authors analyzed the data, discussed the results, and commented on the
manuscript.

## References

  * [1] Marcel Stimberg, Romain Brette, and Dan FM Goodman.  Brian 2, an intuitive and efficient neural simulator.  Elife, 8:e47314, 2019.
  * [2] Markus Diesmann and Marc-Oliver Gewaltig.  Nest: An environment for neural systems simulations.  Forschung und wisschenschaftliches Rechnen, Beiträge zum Heinz-Billing-Preis, 58:43–70, 2001.
  * [3] Chaofei Hong, Mengwen Yuan, Mengxiao Zhang, Xiao Wang, Chegnjun Zhang, Jiaxin Wang, Gang Pan, Zhaohui Wu, and Huajin Tang.  Spaic: A spike-based artificial intelligence computing framework.  IEEE Computational Intelligence, 2022.
  * [4] Ben Varkey Benjamin, Peiran Gao, Emmett McQuinn, Swadesh Choudhary, Anand R Chandrasekaran, Jean-Marie Bussat, Rodrigo Alvarez-Icaza, John V Arthur, Paul A Merolla, and Kwabena Boahen.  Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations.  Proceedings of the IEEE, 102(5):699–716, 2014.
  * [5] Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, et al.  Loihi: A neuromorphic manycore processor with on-chip learning.  Ieee Micro, 38(1):82–99, 2018.
  * [6] Eunjin Baek, Hunjun Lee, Youngsok Kim, and Jangwoo Kim.  Flexlearn: fast and highly efficient brain simulations using flexible on-chip learning.  In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 304–318, 2019.
  * [7] Eustace Painkras, Luis A Plana, Jim Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R Lester, Andrew D Brown, and Steve B Furber.  Spinnaker: A 1-w 18-core system-on-chip for massively-parallel neural network simulation.  IEEE Journal of Solid-State Circuits, 48(8):1943–1953, 2013.
  * [8] Garrick Orchard, E Paxon Frady, Daniel Ben Dayan Rubin, Sophia Sanborn, Sumit Bam Shrestha, Friedrich T Sommer, and Mike Davies.  Efficient neuromorphic signal processing with loihi 2.  In 2021 IEEE Workshop on Signal Processing Systems (SiPS), pages 254–259. IEEE, 2021.
  * [9] Ouwen Jin, Qinghui Xing, Ying Li, Shuiguang Deng, Shuibing He, and Gang Pan.  Mapping very large scale spiking neuron network to neuromorphic hardware.  In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, pages 419–432, 2023.
  * [10] Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, Yutaka Nakamura, Pallab Datta, Gi-Joon Nam, et al.  Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip.  IEEE transactions on computer-aided design of integrated circuits and systems, 34(10):1537–1557, 2015.
  * [11] Zhijie Yang, Lei Wang, Yao Wang, Linghui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, and Weixia Xu.  Unicorn: A multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons.  In Proceedings of the 59th ACM/IEEE Design Automation Conference, pages 943–948, 2022.
  * [12] Christian Pehle, Sebastian Billaudelle, Benjamin Cramer, Jakob Kaiser, Korbinian Schreiber, Yannik Stradmann, Johannes Weis, Aron Leibfried, Eric Müller, and Johannes Schemmel.  The brainscales-2 accelerated neuromorphic system with hybrid plasticity.  Frontiers in Neuroscience, 16:795876, 2022.
  * [13] Peng Chen, Fenghao Liu, Peng Lin, Peihong Li, Yu Xiao, Bihua Zhang, and Gang Pan.  Open-loop analog programmable electrochemical memory array.  Nature Communications, 14(1):6184, 2023.
  * [14] De Ma, Juncheng Shen, Zonghua Gu, Ming Zhang, Xiaolei Zhu, Xiaoqiang Xu, Qi Xu, Yangjing Shen, and Gang Pan.  Darwin: A neuromorphic hardware co-processor based on spiking neural networks.  Journal of systems architecture, 77:43–51, 2017.
  * [15] Anthony N Burkitt.  A review of the integrate-and-fire neuron model: I. homogeneous synaptic input.  Biological cybernetics, 95:1–19, 2006.
  * [16] Eugene M Izhikevich.  Simple model of spiking neurons.  IEEE Transactions on neural networks, 14(6):1569–1572, 2003.
  * [17] Natalia Caporale and Yang Dan.  Spike timing–dependent plasticity: a hebbian learning rule.  Annu. Rev. Neurosci., 31:25–46, 2008.
  * [18] Gregory D Smith, Charles L Cox, S Murray Sherman, and John Rinzel.  Fourier analysis of sinusoidally driven thalamocortical relay neurons and a minimal integrate-and-fire-or-burst model.  Journal of neurophysiology, 83(1):588–610, 2000.
  * [19] Bard Ermentrout.  Type i membranes, phase resetting curves, and synchrony.  Neural computation, 8(5):979–1001, 1996.
  * [20] Romain Brette and Wulfram Gerstner.  Adaptive exponential integrate-and-fire model as an effective description of neuronal activity.  Journal of neurophysiology, 94(5):3637–3642, 2005.
  * [21] Alan L Hodgkin and Andrew F Huxley.  A quantitative description of membrane current and its application to conduction and excitation in nerve.  The Journal of physiology, 117(4):500, 1952.
  * [22] Alan L Hodgkin.  The local electric changes associated with repetitive action in a non-medullated axon.  The Journal of physiology, 107(2):165, 1948.
  * [23] Daniel Choquet and Antoine Triller.  The dynamic synapse.  Neuron, 80(3):691–703, 2013.
  * [24] Arnd Roth, Mark CW van Rossum, et al.  Modeling synapses.  Computational modeling methods for neuroscientists, 6:139–160, 2009\.
  * [25] Ami Citri and Robert C Malenka.  Synaptic plasticity: multiple forms, functions, and mechanisms.  Neuropsychopharmacology, 33(1):18–41, 2008.
  * [26] Terrence J Sejnowski and Gerald Tesauro.  The hebb rule for synaptic plasticity: algorithms and implementations.  In Neural models of plasticity, pages 94–103. Elsevier, 1989.
  * [27] Weiran Cai, Frank Ellinger, and Ronald Tetzlaff.  Neuronal synapse as a memristor: Modeling pair-and triplet-based stdp rule.  IEEE transactions on biomedical circuits and systems, 9(1):87–95, 2014.
  * [28] Fernando M Quintana, Fernando Perez-Pena, and Pedro L Galindo.  Bio-plausible digital implementation of a reward modulated stdp synapse.  Neural Computing and Applications, 34(18):15649–15660, 2022.
  * [29] Joseph M Brader, Walter Senn, and Stefano Fusi.  Learning real-world stimuli in a neural network with spike-driven synaptic dynamics.  Neural computation, 19(11):2881–2912, 2007.
  * [30] Jilin Zhang, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, and Hong Chen.  Anp-i: A 28nm 1.5 pj/sop asynchronous spiking neural network processor enabling sub-o. 1 $\mu$j/sample on-chip learning for edge-ai applications.  In 2023 IEEE International Solid-State Circuits Conference (ISSCC), pages 21–23. IEEE, 2023.
  * [31] Alireza Monemi, Chia Yee Ooi, and Muhammad Nadzir Marsono.  Low latency network-on-chip router microarchitecture using request masking technique.  International Journal of Reconfigurable Computing, 2015:2–2, 2015\.
  * [32] Rabab Ezz-Eldin, Magdy A El-Moursy, and Hesham FA Hamed.  Process variation delay and congestion aware routing algorithm for asynchronous noc design.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3):909–919, 2015.
  * [33] Lu Liu, Zhangming Zhu, Duan Zhou, and Yintang Yang.  A fair arbitration for network-on-chip routing with odd-even turn model.  Microelectronics Journal, 64:1–8, 2017.
  * [34] Saber Moradi, Ning Qiao, Fabio Stefanini, and Giacomo Indiveri.  A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps).  IEEE transactions on biomedical circuits and systems, 12(1):106–122, 2017.
  * [35] Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, et al.  The spinnaker 2 processing element architecture for hybrid digital neuromorphic computing.  arXiv preprint arXiv:2103.08392, 2021.
  * [36] Jeongwoo Park, Juyun Lee, and Dongsuk Jeon.  A 65nm 236.5 nj/classification neuromorphic processor with 7.5% energy overhead on-chip learning using direct spike-only feedback.  In 2019 IEEE International Solid-State Circuits Conference-(ISSCC), pages 140–142. IEEE, 2019.
  * [37] Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, and David Bol.  A 0.086-mm2 12.7-pj/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm cmos.  IEEE transactions on biomedical circuits and systems, 13(1):145–158, 2018.
  * [38] Giacomo Indiveri, Federico Corradi, and Ning Qiao.  Neuromorphic architectures for spiking deep neural networks.  In 2015 IEEE International Electron Devices Meeting (IEDM), pages 4–2. IEEE, 2015.
  * [39] Evangelos Stromatias, Daniel Neil, Francesco Galluppi, Michael Pfeiffer, Shih-Chii Liu, and Steve Furber.  Scalable energy-efficient, low-latency implementations of trained spiking deep belief networks on spinnaker.  In 2015 International Joint Conference on Neural Networks (IJCNN), pages 1–8. IEEE, 2015.
  * [40] Paul A Merolla, John V Arthur, Rodrigo Alvarez-Icaza, Andrew S Cassidy, Jun Sawada, Filipp Akopyan, Bryan L Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface.  Science, 345(6197):668–673, 2014.
  * [41] Chenglong Zou, Xiaoxin Cui, Yisong Kuang, and Xinan Wang.  Mapping convolutional neural networks onto neuromorphic chip for spike-based computation.  In 2021 China Semiconductor Technology International Conference (CSTIC), pages 1–3. IEEE, 2021.
  * [42] KE Steven, PA Merolla, JV Arthur, and AS Cassidy.  Convolutional networks for fast, energy-efficient neuromorphic computing.  Proc. Natl. Acad. Sci. USA, 27:201604850, 2016.
  * [43] Peyton Chandarana, Mohammadreza Mohammadi, James Seekings, and Ramtin Zand.  Energy-efficient deployment of machine learning workloads on neuromorphic hardware.  In 2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC), pages 1–7. IEEE, 2022.
  * [44] Riccardo Massa, Alberto Marchisio, Maurizio Martina, and Muhammad Shafique.  An efficient spiking neural network for recognizing gestures with a dvs camera on the loihi neuromorphic processor.  In 2020 International Joint Conference on Neural Networks (IJCNN), pages 1–9. IEEE, 2020.
  * [45] Charlotte Frenkel and Giacomo Indiveri.  Reckon: A 28nm sub-mm2 task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales.  In 2022 IEEE International Solid-State Circuits Conference (ISSCC), volume 65, pages 1–3. IEEE, 2022.
  * [46] Amar Shrestha, Haowen Fang, Daniel Patrick Rider, Zaidao Mei, and Qinru Qiu.  In-hardware learning of multilayer spiking neural networks on a neuromorphic processor.  In 2021 58th ACM/IEEE Design Automation Conference (DAC), pages 367–372. IEEE, 2021.
  * [47] Oliver Rhodes, Petruţ A Bogdan, Christian Brenninkmeijer, Simon Davidson, Donal Fellows, Andrew Gait, David R Lester, Mantas Mikaitis, Luis A Plana, Andrew GD Rowley, et al.  spynnaker: a software package for running pynn simulations on spinnaker.  Frontiers in neuroscience, 12:816, 2018.
  * [48] Ad Peeters, Frank Te Beest, Mark De Wit, and Willem Mallon.  Click elements: An implementation style for data-driven compilation.  In 2010 IEEE Symposium on Asynchronous Circuits and Systems, pages 3–14. IEEE, 2010.
  * [49] Peter U Diehl and Matthew Cook.  Unsupervised learning of digit recognition using spike-timing-dependent plasticity.  Frontiers in computational neuroscience, 9:99, 2015.
  * [50] Lang Feng, Qianhui Liu, Huajin Tang, De Ma, and Gang Pan.  Multi-level firing with spiking ds-resnet: Enabling better and deeper directly-trained spiking neural networks.  Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence (IJCAI-22), 14(1):2471–2477, 2022.
  * [51] Yangfan Hu, Qian Zheng, Xudong Jiang, and Gang Pan.  Fast-snn: Fast spiking neural network by converting quantized ann.  IEEE Transactions on Pattern Analysis and Machine Intelligence, 45(12):14546–14562, 2023.
  * [52] Mohammad Hashem Haghighat and Jun Li.  Intrusion detection system using voting-based neural network.  Tsinghua Science and Technology, 26(4):484–495, 2021.