# Assessing the Role of Communication in Scalable Multi-Core Quantum
Architectures

Maurizio Palesi  University of Catania
Catania, Italy
<EMAIL_ADDRESS>Enrico Russo  University of Catania
Catania, Italy
<EMAIL_ADDRESS>Davide Patti  University of Catania
Catania, Italy
<EMAIL_ADDRESS>Giuseppe Ascia  University of Catania
Catania, Italy
<EMAIL_ADDRESS>Vincenzo Catania  University of Catania
Catania, Italy
<EMAIL_ADDRESS>
###### Abstract

Multi-core quantum architectures offer a solution to the scalability
limitations of traditional monolithic designs. However, dividing the system
into multiple chips introduces a critical bottleneck: communication between
cores. This paper introduces qcomm, a simulation tool designed to assess the
impact of communication on the performance of scalable multi-core quantum
architectures. Qcomm allows users to adjust various architectural and physical
parameters of the system, and outputs various communication metrics. We use
qcomm to perform a preliminary study on how these parameters affect
communication performance in a multi-core quantum system.

###### Index Terms:

Quantum Computing, Many-core Quantum Computers, Quantum Communications,
Quantum Computers Scalability

##  I Introduction

Quantum computing holds immense potential to revolutionize problem-solving,
surpassing the capabilities of classical computers. Algorithms like Shor’s
[19] showcase this potential. However, building large-scale quantum computers
with thousands of qubits remains a significant challenge, as evidenced by
limitations in current models [1].

Current quantum computers are based on monolithic single-chip architectures
that make them difficult to scale beyond a few thousand qubits due to the
impracticality of integrating control circuits and per-qubit wiring while
maintaining low error rates [10]. As millions of qubits are predicted to be
needed for worthy quantum algorithms [17], there is a need for scalable
solutions able to mitigate crosstalk errors and other issues associated with
densely packed qubits on monolithic single-chip quantum processors. A viable
solution in this direction is interconnecting multiple quantum chips in a
multi-core configuration [20].

This approach, pioneered by Grover [9] and Cleve and Buhrman [5], allows
quantum circuits to be run on separate quantum cores even though they are
physically apart. Of course, to take advantage of such a distributed
architecture, a communication infrastructure is needed to serve both the
quantum and classical communication [2]. The quantum communication sub-system
allows the transfer of qubit states among cores to perform operations
involving qubits mapped onto different cores. The classical communication sub-
system allows the transfer of traditional bits mainly used for control and
synchronization purposes and overall orchestration of the system.

Several methods have been proposed to build inter-core communication networks
for modular quantum computing architectures, such as integrating quantum links
to interconnect superconducting chips [3], ion-shuttling for ion-trapped
computers [11], photonic networks [13], and the teleportation protocol setup
for state transfer [18]. In this paper, we focus on a multi-core quantum
architecture in which qubits among cores are transferred by means of the
teleportation protocol [8] and a Network-on-Chip (NoC) is used to transmit the
control bits to support the protocol. We present qcomm [15], an open-source
simulator which allows analysis of the different components that form the
overall communication time in multi-core quantum architectures. To the best of
our knowledge, this is the first simulator specifically designed to
investigate the role played by the classical communication infrastructure in
multi-core quantum architectures. By using qcomm, users can explore the
interplay between various architectural parameters, physical parameters, and
circuit properties to assess the impact of classical communication on the
performance of multi-core quantum architectures. This makes it a valuable tool
for researchers and designers to explore the communication challenges in these
architectures.

The rest of the paper is organized as follows. Sec. II provides the background
by introducing the reference system architecture and the basic mechanisms
considered for performing operations acting on qubits mapped into different
quantum cores. Sec. III presents qcomm focusing on its inputs and outputs and
on the considered communication model. Sec. IV presents the results of
experiments aimed at assessing the role played by the classical communication
system. Finally, Sec. V concludes the work and draws directions for future
developments.

##  II Background

###  II-A System Architecture

The considered architecture is shown in Fig. 1. It is formed by a mesh of
quantum cores (QCs) interconnected by means of a network-on-chip (NoC). An EPR
pair generator allows to generate EPR pairs in parallel [4] that are
transmitted to different QCs by means of point-to-point connections.

Figure 1: Multi-core quantum architecture.

###  II-B Teleportation Protocol

In this paper, we consider intercore communication among QCs achieved through
the teleportation protocol, as in [18, 7]. In fact, the qubit is not
physically transfered from the source QC to the destination QC. Instead the
status of the source qubit is reconstructed into a destination qubit.

Figure 2: Teleportation protocol.

The teleportation protocol involves five sequential phases, namely, EPR
generation, EPR distribution, pre-processing, classical communication, and
post-processing that are graphically shown in Fig. 2. In EPR generation
phases, an entanglement pair of qubits is generated. The two entangled qubits
are distributed by means of quantum channels to the two communicating QCs: one
to the source QC, namely, $\mathit{EPR}_{tx}$, and one to the destination QC,
namely, $\mathit{EPR}_{rx}$. The quantum channels are point-to-point links
connecting the EPR pair generator with QCs as shown in Fig. 1 (blue wires). In
the pre-processing phase the qubit to be transmitted, namely $q_{tx}$, and
$\mathit{EPR}_{tx}$ are pre-processed and measured thus generating two bits of
classical information. These two bits are sent to the destination QC by the
NoC in the classical communication phase. Finally, in the post-processing
phase, the two-bits are used to select one of the four different quantum
operation on $\mathit{EPR}_{rx}$ that results in the transfer of the status of
$q_{tx}$ to $\mathit{EPR}_{rx}$.

###  II-C Remote Gate Operation

Figure 3: Quantum Teleportation for inter-core CNOT execution: (a) A circuit
containing a CNOT operation on qubits $\ket{x}$ and $\ket{y}$. (b) Mapping of
the circuit onto a multi-core architecture. Qubits $\ket{x}$ and $\ket{y}$
reside on different cores (core 1 and core 2). (c) Teleportation is used to
transfer the state of $\ket{x}$ to core 2, enabling the CNOT operation. (d)
Breakdown of the teleportation process: creation of entangled qubits,
classical communication, and state recovery using the received classical
information. (e) Asuming direct connections between all qubits within the
core, the CNOT operation can be performed.

Circuits being mapped on multi-core quantum architectures often involve gates
that must operate on qubits located on different cores [7]. Suppose we want to
execute a CNOT operation on two qubits, $\ket{x}$ and $\ket{y}$, on such an
architecture, as shown in Fig. 3(a). If $\ket{x}$ and $\ket{y}$ are mapped
onto different cores (core 1 and core 2, for example, as in Fig. 3(b)), to
execute the gate, both qubits must be located on directly connected physical
qubits within the same core.

Since we assume all physical qubits within a core are directly connected,
either the state of $\ket{x}$ must be transferred to core 2 or the state of
$\ket{y}$ must be transferred to core 1. This can be achieved using
teleportation, as shown in Fig. 3(c) where the state of $\ket{x}$ is
transferred to a qubit in core 2. The different phases involved in the
teleportation process are shown in Fig. 3(d). The two entangled qubits
generated are transmitted via quantum channels and stored in communication
qubits within core 1 and core 2. The pre-processing block in core 1 determines
the 2 bits of classical information that are sent to core 2 through the NoC.
These two bits are then used by the post-processing block in core 2 to recover
the quantum state of $\ket{x}$. However, the original state of qubit $\ket{x}$
in core 1 is lost due to the no-cloning theorem.

At this point, with both $\ket{x}$ and $\ket{y}$ residing in the same core and
assuming direct connections between all qubits within the core, the CNOT
operation can be performed, Fig. 3(e).

##  III qcomm Simulator

Figure 4: Inputs and output of qcomm.

The inputs and output of the simulator are shown in Fig. 4. Qcomm gets in
input the description of the quantum circuit, the description of the
architecture, and the physical parameters. It produces in output the execution
statistics. Each of the above elements, is presented in the following.

###  III-A Circuit Representation

Figure 5: Example of the circuit representation.

A quantum circuit is described as a sequence of time slices. Each slice
defines a set of gates that can be executed concurrently. Gates within a slice
can be executed simultaneously if they share no input qubits. An example
circuit description is provided in Fig. 5. Each line in the circuit file
represents a slice, encoded as a list of gates. An $n$-input gate is
represented by a tuple containing the qubit indices. For example, in Fig. 5,
the second line represents the second slice. This slice includes a single-
input gate involving qubit $q_{2}$ and a three-input gate involving qubits
$q_{3}$, $q_{7}$, and $q_{8}$.

###  III-B Architecture Description

The architecture file specifies the the resources of the QCs and the
characteristics of the NoC describing how these QCs are interconnected. The
following parameters are specified in the architecture file:

  * •

mesh_x and mesh_y: These define the number of QCs in the horizontal and
vertical dimensions, respectively. The total number of QCs is the product of
mesh_x and mesh_y.

  * •

link_width: This defines the width (number of data lines) of the NoC link. It
also determines the flit size (a unit of data transferred over the NoC). A
communication packet of $n$ bits is divided into $n/$link_width flits, each
with a size of link_width bits.

  * •

qubits_per_core: This specifies the total number of physical qubits per QC.
Thus, the total number of physical qubits in the system is mesh_x $\times$
mesh_y $\times$ qubits_per_core.

  * •

ltm_ports: This defines the number of LTM ports per QC. It determines the
maximum number of concurrent teleportations that can involve the same QC.

  * •

wireless_enabled: This parameter indicates whether the communication system is
implemented by a NoC or a wireless NoC (WiNoC) [6].

  * •

radio_channels: This specifies the number of radio channels available in the
WiNoC (if enabled by wireless_enabled).

###  III-C Parameters

The parameters file specifies the physical parameters used in the simulation.
These parameters include the gate delay and the delay and data rate figures
for the classical communication system (NoC and WiNoC). Specifically, the
following parameters are defined:

  * •

gate_delay: Delay of a gate. In the current implementation, all gates are
considered to have the same delay regardless of their type or number of
inputs.

  * •

hop_delay: Delay of a hop in the NoC. This includes both the router delay and
the link delay.

  * •

epr_delay: Mean of the EPR pair generation time.

  * •

dist_delay: EPR pair distribution time.

  * •

pre_delay and post_delay: Delay of the pre-processing and post-processing
block for teleportation, respectively.

  * •

wbit_rate: This parameter specifies the WiNoC bit-rate used only if the
wireless_enabled flag in the architecture file is set.

  * •

token_pass_time: When the communication system is a WiNoC, the medium access
control mechanism is based on token passing [6], where only the wireless
interface (WI) holding the token can transmit. This parameter represents the
time spent by the token to be moved from one WI to another.

###  III-D Statistics

The output of the simulation is a report containing various execution
statistics. These statistics include:

  * •

Executed gates: The number of gates in the circuit that have been executed.

  * •

Intercore communications: The total number of qubits transferred from one QC
to another to perform gates involving qubits located on different QCs.

  * •

Throughpunt (peak and average): Peak and average rate of classical
communication observed during the execution of the circuit. This refers to the
communication overhead (either on the NoC or WiNoC) required to implement the
teleportation protocol.

  * •

Core utilization (average, minimum, and maximum): The average, minimum, and
maximum number of qubits in a QC. Initially, the logical qubits of the circuit
are uniformly mapped to the QCs. In other words, in a circuit with $n$ qubits,
each QC will host $m=n$/(mesh_x $\times$ mesh_y) qubits, where $m$ must be
less than or equal to qubits_per_core. As the simulation progresses, some
qubits are redistributed from one QC to another, thus varying the distribution
of qubits across the QCs.

  * •

Communication time: The portion of the execution time spent on communication.
It is further divided into five components representing the time spent for EPR
pair generation, EPR pair distribution, pre-processing, classical
communication, and post-processing.

  * •

Computation time: The portion of the execution time spent on computation,
i.e., gate execution.

  * •

Execution time: Total execution time, which is the sum of the communication
time and computation time.

  * •

Coherence: Based on the experimental results from [14], the decoherence time
of electron spin qubits (without implementing the dynamic decoupling technique
for extending qubit lifetime) is $T_{2}=268\ \mu$s. Assuming an exponential
decay of the qubit coherence over time, the qubit coherent state after $t$
$\mu$s is obtained as $e^{-t/T_{2}}$.

###  III-E Communication Model

The communication time to transfer the state of a qubit from a core $s$ to a
core $d$, $\mathit{CT}_{s\rightarrow d}$, is computed as the sum of the times
spent in each phase of the teleportation protocol:

$\mathit{CT}_{s\rightarrow
d}=\mathit{EPRG}+\mathit{EPRD}+\mathit{PRE}+\mathit{CC}_{s\rightarrow
d}+\mathit{POST}$

where $\mathit{EPRG}$ is the EPR generation time, $\mathit{EPRD}$ is the EPR
distribution time, $\mathit{PRE}$ is the pre-processing time,
$\mathit{CC}_{s\rightarrow d}$ is the classical communication time, and
$\mathit{POST}$ is the post-processing time. Please, refer to Sec. II-B for a
refresh of the meaning of the above terms. In our model, apart from the
classical communication time which depends on the location of the cores $s$
and $d$ in the NoC, the other terms are considered to be constant.

We implemented two models for computing $\mathit{CC}_{s\rightarrow d}$
contribution: one for the NoC and the other for the WiNoC.

####  III-E1 NoC Communication Model

The classical communication time for the NoC is the time spent for sending a
packet from a source QC $s$ to a destination QC $d$. It is computed as the
product between the hop distance between $s$ and $d$ and the hop time. The hop
distance refers to the number of routers and links traversed by the packet
assuming minimum routing. The hop time is the sum between router latency and
link latency. The link transmission time is the time spent for a packet to
traverse the link and depends on the packet size, the link width and clock
frequency.

The packet size in bits is computed as
$2\lceil\log_{2}\mathit{nqubits}\rceil+2$, where the first term represents the
bits needed to encode the source and the destination address. The constant 2
accounts for the 2 bits needed to support the teleportation protocol. Because
the packet carries source and destination addresses, the number of bits needed
to encode them depends on the total number of physical qubits in the system,
that is:

$\mathit{nqubits}=\texttt{mesh\\_x}\times\texttt{mesh\\_y}\times\texttt{qubits\\_per\\_core}$

All the above information is derived from the parameters specified in the
physical parameter file in input to the simulator (Sec. III-C).

Executing a circuit slice can generate multiple concurrent communication
streams. However, our communication model is not a simple zero-contention
model. In a zero-contention model, each communication would be independent and
have full access to network resources. Instead, our simulator considers the
potential overlap of routing paths for these concurrent communications, thus
allowing for a more accurate estimation of the classical communication time.
When communication streams share the same network link, data packets from
these streams are serialized, which increases the overall classical
communication time.

####  III-E2 WiNoC Communication Model

The classical communication time for the WiNoC is the time spent for sending a
packet from a source QC $s$ to a destination QC $d$ using the radio channel.
In this scenario, there are no wired connections between routers; instead,
wireless interfaces (WIs) using radio channels replace them. The packet is
serialized and transmitted at a specific data rate.

Only one WI can use the radio medium at a time. A medium access control (MAC)
technique based on a token passing mechanism, as described in [16], is used.
Only the WI holding the token can transmit on the radio channel for a duration
sufficient to complete the packet transmission.

The simulator supports the use of multiple radio channels that thus allow the
transmission of multiple packets simultaneously, each on a different radio
channel.

###  III-F Parallel Teleportation

Multiple teleportations can be performed in parallel between separate QC
pairs. Additionally, if QCs are equipped with multiple LTM ports, parallel
teleportations can also be performed between the same QC pair.

Consider the circuit in Fig. 6(a), where the two CNOT gates can be executed in
parallel. Qubits $q_{0}$ and $q_{2}$ are mapped to core 1, while $q_{1}$ and
$q_{3}$ are mapped to core 2. Since each CNOT gate requires qubits from
different cores, neither CNOT can be executed until both qubits are in the
same core.

To achieve this, two teleportations are necessary, as shown in Fig. 6(b).
First, the state of $q_{0}$ is teleported to core 2, allowing the CNOT between
$q_{0}$ and $q_{1}$ to proceed. Then, the state of $q_{3}$ is teleported to
core 1, enabling the execution of the second CNOT between $q_{2}$ and $q_{3}$.

In essence, even though the CNOT gates can theoretically be executed
concurrently because they involve separate qubits, practical limitations arise
due to the single LTM port per core. This single port restricts teleportation
to a serial process, preventing true parallel execution of the CNOT gates.

Figure 6: The execution of the two CNOT must be serialized as they involve two
teleportation among the same cores that cannot be executed in parallel. The
original slice is thus serialized into two slices. In the first slice, the
$q_{0}$ state is transferred to core 2 and the first CNOT is executed. In the
second slice, the $q_{3}$ state is transferred to core 1 and the second CNOT
is executed.

Now, consider the scenario in Fig. 7(a) where each core has two LTM ports. In
this case, both CNOT gates can be executed simultaneously because the
transfers of $q_{0}$ to core 2 and $q_{3}$ to core 1 can be parallelized, as
shown in Fig. 7(b). Qcomm factors in the availability of LTM ports when
scheduling the execution of gates that involve qubits on different cores. It
then splits the time slice based on this availability to optimize scheduling.

Figure 7: Both CNOT can be executed in parallel as two teleportation, one that
transfers the state of $q_{0}$ to core 2 and the other that transfers the
state of $q_{3}$ to core 0, can be performed in parallel each using a
different LTM pair.

##  IV Experiments

In this section, we use qcomm to conduct a series of experiments to assess the
role of communication in multi-core quantum architectures. We specifically
investigate how communication time varies with different architectural
parameters and circuit properties. Tab. I reports the parameters used in the
experiments, which are based on transmon superconducting qubit technology used
in [12].

TABLE I: Parameters used for the experiments [12]. Parameter | Value
---|---
Mean of EPR pair generation time |  $10^{3}$ ns
EPR pair distribution time | 0.01 ns
Pre-processing time | 390 ns
Classical transfer time (hop delay) | 1 ns
Post-processing time | 30 ns

###  IV-A Impact of LTM Ports

In our first experiment, we investigate how communication time changes with
the number of LTM ports. We consider a $4\times 4$ mesh architecture with 16
QCs interconnected by a wired NoC, as shown in Fig. 1. The NoC utilizes 8-bit
links and operates at a clock speed of 1 GHz. Each QC integrates 10 physical
qubits, resulting in a total of 160 physical qubits for the entire system.

To analyze communication under varying traffic conditions, we use three
randomly generated circuits, each containing 100 qubits and 1,000 gates. These
circuits differ in the ratio of 1-input and 2-input gates. The percentage of
2-input gates directly affects communication traffic because these gates
require communication when the involved qubits reside on separate QCs. The
three circuits have the following ratios: 75% 1-input gates and 25% 2-input
gates, 50% of each type, and 25% 1-input gates and 75% 2-input gates.

Fig. 8 shows the total communication time for different numbers of LTM ports.
Circuits with a higher proportion of 2-input gates experience increased
communication traffic. This is because these gates necessitate communication
when the qubits reside on separate QCs, leading to a rise in communication
time. Conversely, as the number of LTM ports increases, communication time
decreases due to the increased potential for parallelizing communication
between the same QCs. Interestingly, while the decrease in communication time
with more LTM ports is an expected outcome, we observe that there’s no further
improvement beyond 3 LTM ports.

Figure 8: Impact of the number of LTM ports on communication time.

Our results show that communication improvement plateaus after 3 LTM ports,
regardless of the network size (number of QCs). To verify this, we measured
communication time as the network size increased (i.e., more QCs). We also
proportionally scaled the circuit complexity with the system size. For the
single-QC baseline system with 15 physical qubits, the mapped circuit has 10
logical qubits and 100 gates. When simulating an $n$-QC system, we map a
circuit with $10n$ logical qubits and $100n$ gates. Fig. 9 confirms this
observation. It shows communication time for different LTM port counts as the
number of QCs increases. Consistent with our findings in Fig. 8 for the 16-QC
system, communication time saturates when LTM ports exceed 3, irrespective of
network size.

Figure 9: Communication time _vs._ NoC size for different number of LTM ports.

###  IV-B Communication Time Breakdown

In the second experiment, we analyze how different NoC architecture
characteristics contribute to the overall communication time.

We use a $4\times 4$ NoC (16 QCs) with 8-bit links and 2 LTM ports per QC. The
mapped circuit is randomly generated, containing 100 logical qubits and 1,000
2-input gates. Fig. 10 shows a breakdown of communication time as the NoC
clock frequency varies from 100 MHz to 1 GHz. Across all frequencies, the
classical communication latency has a minimal impact on the total
communication time. The dominant factors are EPR generation time and
preprocessing time.

Figure 10: Breakdown of communication time by NoC clock frequency.

Fig. 11 analyzes the impact of NoC link width, which varies from 2 to 10 bits.
Even with the lowest-performing option (a 2-bit link width), classical
communication still has a minimal impact on the total communication time. Here
too, EPR generation and preprocessing time remain the dominant factors. In the
worst case, classical communication only affects the total communication time
by a mere 12%.

Figure 11: Breakdown of communication time by NoC link width.

Finally, Fig. 12 presents a breakdown of communication time for different NoC
sizes. We use the same mapped circuit for all NoC sizes. As expected,
communication time decreases with increasing NoC size due to the potential for
greater parallelism. Interestingly, the contribution of classical
communication becomes increasingly relevant as the NoC size grows. This is
because unlike other factors that influence communication time (e.g., EPR
generation, preprocessing), classical communication depends on the distance
between communicating nodes. As the NoC size increases, the average
communication distance also increases, making classical communication a more
significant cost factor.

Figure 12: Breakdown of communication time by NoC size.

Across all scenarios examined, classical communication appears to have a
minimal impact compared to the time spent on EPR generation and preprocessing.
However, it is important to note that this breakdown is specific to the
quantum technology used in our setup (see Tab. I). In the next subsection, we
will explore how advancements in quantum technology could alter this scenario,
potentially making the classical communication system the bottleneck.

###  IV-C Previsional Trends

The previous analysis of the communication system’s role is based on current
quantum technology parameters, summarized in Tab. I. In this scenario,
classical communication plays a secondary role compared to other components
affecting the total communication time. This subsection explores when
classical communication becomes the bottleneck.

To investigate this, we progressively scale quantum-related parameters (EPR
generation time, pre-processing time, and post-processing time) by the same
factor. We aim to identify the point at which classical communication becomes
the limiting factor. We consider two communication systems: a traditional
wired NoC architecture clocked at 1 GHz and an emerging wireless NoC
architecture (WiNoC) [6] with a data rate of 12 Gbps. Fig. 13 presents the
results, with the improvement factor on the x-axis. As observed in the figure,
a 20x improvement in quantum parameters makes the wired NoC the bottleneck,
accounting for over 75% of the total communication time. For the WiNoC, the
same improvement factor leads to it accounting for 95% of the communication
time. Even a 10x improvement reveals a substantial contribution from the
WiNoC, at 44% of the total time.

Overall, while classical communication appears marginal compared to other
components in the current scenario, this may change as quantum technology
advances. Future improvements could make classical communication the
bottleneck, highlighting its importance for further research.

Figure 13: Fraction of the total communication time accounted by the different
contributors when a wired NoC (top) and a wireless NoC (bottom) are used for
supporting the classical communication.

##  V Conclusion

This paper presents qcomm, a novel open-source simulator specifically designed
to analyze the impact of classical communication on the performance of multi-
core quantum architectures. Qcomm allows users to explore the interplay
between various architectural parameters, physical parameters, and circuit
properties to assess communication overhead.

The results of our experiments using qcomm show that:

  * •

Impact of LTM Ports: Communication time decreases significantly with an
increasing number of LTM ports per core, facilitating parallel communication.
However, the benefit plateaus after three LTM ports due to limitations in the
communication workload generated by the circuits used in our experiments.

  * •

Communication Time Breakdown: In the current quantum technology landscape,
classical communication has a minimal impact on the total communication time
compared to factors like EPR generation and preprocessing.

  * •

Future Bottlenecks: We anticipate that advancements in quantum technology will
reduce the time spent on tasks like EPR generation and preprocessing,
potentially making the classical communication system the performance
bottleneck. This emphasizes the need for further research on optimizing
classical communication strategies for multi-core quantum architectures.

In conclusion, qcomm offers a valuable tool for researchers and designers to
explore the communication challenges in multi-core quantum architectures. As
classical communication may become a critical factor in future quantum
systems, qcomm paves the way for further research on efficient communication
protocols and network architectures for high-performance quantum computing.

## Acknowledgement

Authors gratefully acknowledge funding from the European Commission through
HORIZON-EIC-2022-PATHFINDEROPEN01-101099697 (QUADRATURE)

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