#  Impedance Leakage Vulnerability and its Utilization in Reverse-engineering
Embedded Software

Md Sadik Awal and Md Tauhidur Rahman
Security, Reliability, Low-power, and Privacy (SeRLoP) Research Lab
ECE Department, Florida International University, Miami, Florida, USA
E-mail: {mawal003 and<EMAIL_ADDRESS>
###### Abstract

Discovering new vulnerabilities and implementing security and privacy measures
are important to protect systems and data against physical attacks. One such
vulnerability is impedance, an inherent property of a device that can be
exploited to leak information through an unintended side channel, thereby
posing significant security and privacy risks. Unlike traditional
vulnerabilities, impedance is often overlooked or narrowly explored, as it is
typically treated as a fixed value at a specific frequency in research and
design endeavors. Moreover, impedance has never been explored as a source of
information leakage. This paper demonstrates that the impedance of an embedded
device is not constant and directly relates to the programs executed on the
device. We define this phenomenon as impedance leakage and use this as a side
channel to extract software instructions from protected memory.

Our experiment on the ATmega328P microcontroller and the Artix 7 FPGA
indicates that the impedance side channel can detect software instructions
with 96.1% and 92.6% accuracy, respectively. Furthermore, we explore the dual
nature of the impedance side channel, highlighting the potential for
beneficial purposes and the associated risk of intellectual property theft.
Finally, potential countermeasures that specifically address impedance leakage
are discussed.

###### Index Terms:

Hardware security, impedance leakage, switching activity, instruction reverse
engineering

##  I Introduction

Integrated circuits and systems have become essential components in various
domains, managing sensitive data and attracting adversaries aiming to extract
unauthorized access or information [1]. Intriguingly, the internal operations
of these systems give rise to physical side channel signals—subtle traces of
information that can be exploited to obtain sensitive information. In this
context, physical side channel analysis (SCA) arises as a potent technique
based on the physical properties of a system [2]. The phenomenon of physical
side channel leakages resulting from the computation and storage operations on
integrated circuits reveals itself through measurable quantities such as power
consumption, electromagnetic (EM) radiation, and even thermal radiation. The
attackers exploit these quantities to compromise the security of cryptographic
implementations [2]. Although numerous countermeasures have been proposed and
developed to limit SCA-based attacks, SCA has demonstrated their effectiveness
despite standard security measures [3, 4, 5]. The persistence and adaptability
of side channel vulnerabilities continue to pose new challenges [6, 4].

Contrary to conventional security measures, which often focus on mitigating
vulnerabilities, side channel analysis presents an intriguing perspective: It
can be employed to enhance hardware security [7, 8, 9, 10]. By integrating
side channel information into device design, intrusion detectors can be
developed to monitor the side channels of a device for indications of an
attack. These detectors can identify deviations from expected patterns and
initiate preventive measures if an attack is detected [10]. Moreover, external
detectors can discreetly observe device activity without relying on its inputs
and outputs, thus foiling an attacker’s attempts to evade detection by
controlling those elements.

While many vulnerabilities resulting from the physical properties of devices
are known, one often overlooked aspect is impedance—a fundamental property
[11]. Yet, this seemingly innocuous factor can be exploited as an unintended
side channel, posing significant risks to security and privacy. Traditionally,
impedance is treated as a fixed value at a specific frequency [11, 12],
limiting its exploration. In contrast to the prevailing assumption, our
research studies the relationship between device impedance and sensitive
information. We demonstrate that impedance serves as a side channel leaking
valuable information from an embedded device and define this phenomenon as
impedance leakage. In this study, conducted on two different hardware
platforms, we use impedance leakage to extract information about the executed
software instructions on the target devices. By shedding light on this
overlooked characteristic, impedance, we open a new direction for
understanding and securing systems in the face of emerging physical SCA.

In this article, we explore the potential of impedance leakage in reverse
engineering software instructions. Disassembling software instructions
provides insights into the internal behavior of an embedded device, making it
a potential defense against a wide range of software-based attacks, e.g.,
software modification-based attacks. We discover that the impedance of an
embedded device changes when it executes different software instructions.
Leveraging this observation, we analyze and investigate the feasibility of
utilizing device impedance as an emerging side channel for software
instruction disassembly. Thus, this work addresses the question: “Does device
impedance leak information of the executed software instructions and emerge as
a promising side channel?”—or in other words: Can we use the device impedance
to reverse engineering executed software instructions? Our contributions in
this paper are summarized as follows:

  * •

We explore a novel impedance side channel generated by the switching
activities of a device.

  * •

We present a unique approach to analyzing device impedance as a source of
information leakage in extracting distinctive fingerprints for classifying
program instructions.

  * •

We demonstrate the existence of impedance leakage by reverse engineering the
software instructions on different embedded platforms.

The remaining sections of the paper are organized as follows. Section II
briefly addresses existing side channels along with impedance as a side
channel. Section III discusses the research motivation. The experimental setup
of this study has been discussed in Section IV, which includes the hardware
setup, software setup, and impedance signal measurement. In Section V, the
analysis of the signals and the classification results are presented. Section
VI addresses the related works. The conclusion of the work is provided in
Section VII.

##  II Background

The security and privacy of digital systems are not solely dependent on the
efficacy of mathematically secure algorithms and protocols, as the physical
properties of a system can unintentionally leak internal information. These
unintended physical characteristics, known as physical side channels, can be
exploited by attackers to gain access to sensitive data and assets. Two
popular types of physical side channels are power SCA and EM SCA.

Power SCA involves analyzing variations in power consumption during system
operations. An attacker can deduce sensitive information like cryptographic
keys by measuring the power consumption of a target component, such as a
processor. Differential power analysis (DPA) is commonly used in this context
to detect subtle changes in power consumption, providing insights into data-
dependent variations that may otherwise be imperceptible. Alternatively, EM
SCA relies on capturing the EM radiation emanating from a device during its
functioning. As the device executes its operations, the dynamic changes in the
current flow within its components give rise to distinct EM waves. Through the
careful analysis of these EM leakages, attackers can glean valuable
information about the events occurring throughout each clock cycle, allowing
them to potentially infer internal processes and sensitive data.

Despite their effectiveness, both power and EM SCAs have limitations. Power
SCA requires the modification of the original device with a shunt resistor,
which may not always be feasible or practical. Additionally, EM SCA can be
challenging due to the need for specialized equipment like near-field probes
or antennas and the necessary signal processing steps to extract exploitable
information. To address these limitations and strengthen the security of
digital systems against emerging physical SCAs, exploration is required to
understand their unintended correlations with sensitive information.

###  II-A Impedance Leakage

Impedance side channels, in contrast to EM and power side channels, emerge
from changes in impedance caused by switching circuits within a complementary
metal–oxide semiconductor (CMOS) device. This unique side channel presents a
modulated signal of internal device events, wherein the two-state impedance of
transistors in the CMOS device undergoes changes during operation. Our
previous works [11, 13] represent a mathematical formulation of this
phenomenon in transistor-level. In this work, we consider a two-input CMOS
NAND gate as of Figure 1(a) to present the idea of information leakage through
impedance in gate-level. We consider the NMOS and PMOS to have widths of 2 and
3, respectively, and $C_{0}$ denotes the fanout capacitance. Depending on the
input $A$ and $B$, the metal oxide semiconductor field effect transistors
(MOSFETs) can be in the active or cutoff region. Let $Z_{3c}$ be the impedance
of $3C$ capacitance and $Z_{eq,0}$ be the impedance of the combined
capacitance of $7C$ and $C_{0}$.

(a)

(b)

(c)

Figure 1: (a) 2-input NAND gate, (b) PMOS/NMOS with the parasitic capacitance,
(c) truth table with relative impedance.

In the cutoff mode, a MOSFET functions as an open switch with very high
resistance between the source and drain. Despite this state, a low leakage
current exists due to the presence of reverse-biased P-N junctions between the
source and drain. The impedance in cutoff mode is dependent on specific device
specifications and operating conditions, which can be calculated by measuring
the leakage current ($I_{DS,L}$) while considering the drain-to-source voltage
($V_{DS}$). The leakage current $I_{DS,L}$ has an expression of [14]:

$\displaystyle
I_{DS,L}=W.C.B^{-B.L_{G}}\exp{\left(\frac{\Delta\Phi}{V_{t}}\right)}\left[\exp{\left(\frac{A.V_{DS}}{V_{t}}\right)}-1\right]$
(1)

Thus, the cutoff region impedance, $Z_{C}$, is expressed as:

$\displaystyle Z_{C}$ $\displaystyle=\frac{V_{DS}}{I_{DS,L}}$
$\displaystyle=\frac{V_{DS}}{W.C.B^{-B.L_{G}}\exp{\left(\frac{\Delta\Phi}{V_{t}}\right)}\left[\exp{\left(\frac{A.V_{DS}}{V_{t}}\right)}-1\right]}$
(2)

In the linear and saturation mode, let $R_{lin,p/n}$ and $R_{sat,p/n}$ be the
effective on-resistance for the PMOS/NMOS, respectively. The expression of
$R_{lin,p/n}$ and $R_{sat,p/n}$ can be represented as [15],

$\displaystyle R_{lin,p/n}$
$\displaystyle=\frac{\frac{1}{2}(V_{D}-V_{S}-V_{t,p/n})}{\frac{3}{8}k^{\prime}_{p/n}(\frac{W}{L})_{p/n}(V_{D}-V_{S}-V_{t,p/n})^{2}}$
(3) $\displaystyle R_{sat,p/n}$
$\displaystyle=\frac{V_{D}-V_{S}}{\frac{1}{2}k^{\prime}_{p/n}(\frac{W}{L})_{p/n}(V_{D}-V_{S}-V_{t,p/n})^{2}}$
(4)

Here, $k^{\prime}_{p/n}$ represents the trans-conductance, $(W/L)_{p/n}$
represents the aspect ratio, and $V_{t,p/n}$ represents the threshold voltage
of the PMOS/NMOS. The voltage at the drain is denoted by $V_{D}$, while the
voltage at the source is denoted by $V_{S}$. Let $R_{p/n}$ be the effective
on-resistance of the PMOS/NMOS. Using (3) and (4), $R_{p}$ and $R_{n}$ can be
estimated as follows:

$\displaystyle R_{p/n}=\frac{1}{2}(R_{lin,p/n}+R_{sat,p/n})$ (5)

Fig. 1(b) depicts an equivalent circuit of PMOS/NMOS containing parasitic
capacitances. Based on the input $X$ at the gate, the MOSFET changes its
operating state from cut-off to saturation following the linear state. Let
$C_{gdp/n}$ represent the gate to drain capacitance, $C_{dbp/n}$ represent the
drain to bulk parasitic capacitance (the diffusion capacitance) for the
PMOS/NMOS [16, 17]. The equivalent capacitance value, $C_{eq,p/n}$,
aggregating the parasitic capacitance for the PMOS/NMOS, respectively [15] can
be expressed as,

$\displaystyle C_{eq,p/n}=\sum(C_{gdp/n},C_{dbp/n})$ (6)

Let $X_{p/n}$ be the equivalent reactance of NMOS/PMOS, respectively.
Interestingly, the parasitic capacitance of the PMOS/NMOS dominates the
equivalent reactance $X_{p/n}$ [16]. Hence, the equivalent reactance $X_{p/n}$
follows,

$\displaystyle X_{p/n}\approx\frac{-1}{\omega C_{eq,p/n}}$ (7)

Here, $\omega=2\pi f$ and $f$ is the signal frequency. The equivalent
impedance, $Z_{p/n}$ for PMOS/NMOS, consists of equivalent resistance
$R_{p/n}$ and equivalent reactance $X_{p/n}$. The expression of the equivalent
impedance $Z_{p/n}$ can be expressed as,

$\displaystyle Z_{p/n}=R_{p/n}+jX_{p/n}$ (8)

Using (8), we can calculate the impedance for the PMOS and NMOS working in the
linear and saturation regions. The physical parameters for the PMOS and NMOS
are distinct. Therefore, the impedance values for the PMOS and NMOS operating
in the linear and saturation regions are not identical.

To demonstrate how information is leaked through impedance in the gate-level,
we consider a simple two-input NAND gate (Fig. 1(a)). Let $Z_{P,a}$, $Z_{N,a}$
be the active region impedance and $Z_{P,c}$, $Z_{N,c}$ be the cutoff region
impedance for the PMOS and NMOS of the NAND gate, respectively. Equation (8)
can be used to estimate $Z_{P,a}$ and $Z_{N,a}$. Equation (2), on the other
hand, can be used to estimate $Z_{P,c}$ and $Z_{N,c}$. Using $Z_{P/N,a/c}$,
the impedance values for all four possible input patterns to the two-input
NAND gate can be estimated.

Case $A=0$, $B=0$: Here, the two PMOS remain active while the two NMOS remain
inactive. Let, the impedance between $V_{DD}$ and ground node be $Z_{00}$ and
it can be expressed as,

$\displaystyle Z_{00}$
$\displaystyle=Z_{P,a}||Z_{P,a}+(Z_{N,c}||Z_{3C}+Z_{N,c})||Z_{eq,0}$
$\displaystyle=\frac{Z_{P,a}}{2}+\frac{(Z_{N,c}Z_{3C}+Z_{N,c}(Z_{N,c}+Z_{3c}))Z_{eq,0}}{Z_{N,c}Z_{3C}+(Z_{N,c}+Z_{eq,0})(Z_{N,c}+Z_{3c})}$
(9)

Similarly, for Case $A=0$, $B=1$, Case $A=1$, $B=0$, and Case $A=1$, $B=1$,
the impedance from the supply voltage side can be expressed in terms of
$Z_{01}$ (10), $Z_{10}$ (11), and $Z_{11}$ (12), respectively.

$\displaystyle Z_{01}$
$\displaystyle=Z_{P,a}||Z_{P,c}+(Z_{N,c}||Z_{3C}+Z_{N,a})||Z_{eq,0}\hskip
10.0pt$ (10) $\displaystyle Z_{10}$
$\displaystyle=Z_{P,c}||Z_{P,a}+(Z_{N,a}||Z_{3C}+Z_{N,c})||Z_{eq,0}\hskip
10.0pt$ (11) $\displaystyle Z_{11}$
$\displaystyle=Z_{P,c}||Z_{P,c}+(Z_{N,a}||Z_{3C}+Z_{N,a})||Z_{eq,0}\hskip
10.0pt$ (12)

This section considers a simple two-input NAND gate to demonstrate the concept
of different input combinations producing distinct impedance values. The
equivalent impedance between $V_{DD}$ and ground nodes as expressed by
(9)-(12) are distinct for all the possible input combinations of $A$ and $B$.
Although this is a simple scenario, a digital system contains different types
of logic gates to carry out different types of functions.

##  III Exploiting Impedance Leakages to Reverse-engineer Embedded Software

Unlike conventional side channels such as power and electromagnetic (EM)
emissions that monitor fluctuations in power consumption or EM radiation,
impedance side channels directly characterize the intrinsic impedance of a
device across a range of frequencies. This novel perspective of impedance side
channel transcends the conventional understanding of impedance, which
typically focuses on its role in circuit design and signal transmission.
Instead, the impedance side channel considers impedance as a dynamic and
evolving parameter that can inadvertently leak sensitive information about the
internal operations of embedded systems Section II-A. Consequently, the
impedance side channel can be utilized in detecting counterfeit hardware and
printed circuit boards (PCBs) by profiling authentic components and
identifying impedance mismatches [18, 12]. Moreover, variations in device
impedance during cryptographic operations can be exploited to extract secret
encryption keys [19]. Remarkably, even the execution of different program
instructions induces discernible impedance changes that can be leveraged to
monitor software behavior [11].

Our previous work [11] demonstrates the potential of impedance side channel
for classifying program instruction types, such as data transfer, arithmetic,
logical, and branch instructions. Distinct impedance profiles are observed
during the execution of each instruction type. Building on these insights,
this paper explores the use of device impedance as a side channel specifically
for reverse engineering individual software instructions. By observing device
impedance variations during software instruction execution, it may be possible
to identify the exact sequence of instructions being run on a device.
Moreover, reverse engineering software instructions via impedance side
channels can enable numerous hardware security applications. It can be used to
validate the integrity of program execution or detect the presence of
malicious instructions, such as those injected through malware. Additionally,
identifying instruction sequences can help expose counterfeit systems lacking
developer fingerprints. Overall, impedance side channel analysis promises to
unlock new perspectives on the vulnerability landscape of embedded systems
[11].

The motivation of this research is to evaluate the reliability and potential
of adopting impedance side channel analysis, a hardware-based approach, for
disassembling individual software instructions. By transforming impedance from
a static, passive property into an active information source, we can bridge
the gap between hardware characteristics and software security. The ability to
link impedance profiles to instruction behavior can revolutionize reverse
engineering and greatly empower the protection of connected systems against
evolving cyber threats [20, 21].

##  IV Experimental Setup

The experiment proceeds in three steps. In this section, we describe the
physical hardware setup, detailing the equipment configuration. Next, the
software code and instructions executed are outlined. Finally, the signal
acquisition process is elucidated, explaining how data is collected.

###  IV-A Hardware Setup

Our goal in this experiment is to observe if impedance side channel can help
reverse engineer software instructions. We also to study the impact of
hardware complexity on this new side channel. To do this, we conduct
experiments on two different platforms: the Arduino Uno [22], which uses an
8-bit AVR ATmega328P microcontroller, and the Alchitry AU with an Artix 7 FPGA
[23]. We choose these platforms due to their differing levels of complexity
and configurability. The main differences between microcontrollers like the
Arduino and FPGAs like the Alchitry are:

  * •

FPGAs can process multiple inputs in parallel, while microcontrollers execute
instructions one at a time sequentially.

  * •

FPGA hardware can be reconfigured and customized, but microcontroller hardware
has limited flexibility.

Figure 2: Hardware setup: measurement of impedance signals.

Figure 2 illustrates the hardware setup for our experiments on the Arduino and
Alchitry systems. For both devices, we target the 3.3V power domain since it
is closer to the central processing unit (CPU) voltage level. The Arduino and
Alchitry both have onboard 3.3V pins, so no physical modification or tampering
is required to tap into this domain and monitor impedance changes near the
core of each device. By leveraging the 3.3V pins, we observe the impedance
side channel on both platforms non-invasively. This highlights a key benefit
of impedance side channel—the ability to monitor signals without direct
hardware access or modification. The use of native 3.3V pins enables
aboveboard measurements, avoiding tampering.

We use a Rigol RSA5032N spectrum analyzer in vector network analyzer (VNA)
mode to measure impedance. We connect VNA to each device’s power distribution
network (PDN) using a coaxial cable. The coaxial cable consists of an inner
conductor surrounded by a concentric conducting shell, which enables signal
transmission in the center while shielding against interference. The cable’s
design minimizes signal loss and electromagnetic interference (EMI). We
measure impedance fluctuations with better precision by directly attaching the
VNA to the PDN. The VNA-to-PDN connection enables us an accurate means to
monitor impedance changes related to processor activity in each device.

TABLE I: Program instruction set summary. Instruction type |  Description | Artix 7 FPGA | ATmega328P microcontroller
---|---|---|---
Opcode |  Operands |  Operation |  Opcode |  Operands |  Operation
Data transfer |  Load between registers |  LOAD |  R1, R2, K |  R1 $\leftarrow$ [R2 $+$ K] |  MOV |  R1, R2 |  R1 $\leftarrow$ R2
Store from register to memory |  STORE |  R1, R2, K |  R1 $\rightarrow$ [R2 $+$ K] |  — |  — |  —
Load constant into register |  SET |  R1, K |  R1 $\leftarrow$ K |  LDI |  R1, K |  R1 $\leftarrow$ K
Arithmetic and logic |  Addition |  ADD |  R1, R2, R3 |  R1 $\leftarrow$ R2 $+$ R3 |  ADD |  R1, R2 |  R1 $\leftarrow$ R1 $+$ R2
Subtraction |  SUB |  R1, R2, R3 |  R1 $\leftarrow$ R2 $-$ R3 |  SUB |  R1, R2 |  R1 $\leftarrow$ R1 $-$ R2
Bit-wise AND |  AND |  R1, R2, R3 |  R1 $\leftarrow$ R2 $\&$ R3 |  AND |  R1, R2 |  R1 $\leftarrow$ R1 $\&$ R2
Bit-wise OR |  OR |  R1, R2, R3 |  R1 $\leftarrow$ R2 $|$ R3 |  OR |  R1, R2 |  R1 $\leftarrow$ R1 $|$ R2
Bit-wise XOR |  XOR |  R1, R2, R3 |  R1 $\leftarrow$ R2 $\oplus$ R3 |  EOR |  R1, R2 |  R1 $\leftarrow$ R1 $\oplus$ R2
Rotate |  Binary left shift |  SHL |  R1, R2, R3 |  R1 $\leftarrow$ R2 $<<$ R3 |  LSL |  R1 |  R1[n+1] $\leftarrow$ R1[n]
R[0] $\leftarrow$ 0
Binary right shift |  SHR |  R1, R2, R3 |  R1 $\leftarrow$ R2 $>>$ R3 |  LSR |  R1 |  R1[n] $\leftarrow$ R1[n+1]
R[7] $\leftarrow$ 0
Branch |  Branch if equal |  BEQ |  R1, K |  if R1 $=$ K:
PC $\leftarrow$ PC $+$ 2 |  BREQ |  K |  if Z $=$ 1:
PC $\leftarrow$ PC$+$K$+$ 1
Branch if not equal |  BNEQ |  R1, K |  if R1: $\neq$ K
PC $\leftarrow$ PC $+$ 2 |  BRNE |  K |  if Z $=$ 0:
PC $\leftarrow$ PC$+$K$+$1

###  IV-B Software Setup

We program the test devices using assembly language, which is a low-level
programming language with direct correspondence to hardware machine code.
Assembly instructions consist of an opcode mnemonic followed by operands like
data, arguments, or parameters. The opcode indicates the operation to be
performed, while the operands provide the associated data. Assembly language
allows us to write code with the CPU’s basic instructions. This level of
control enables us to understand the fundamental operations occurring during
code execution.

For the Artix 7 FPGA experiments, we construct a simple 8-bit CPU with a
custom instruction set. We also develop a custom assembler to translate the
instructions into memory writes for the FPGA. In total, we define 12
instruction types: data transfer (LOAD, STORE, SET), arithmetic/logic (ADD,
SUB, AND, OR, XOR), rotate (SHL, SHR), and branch (BEQ, BNEQ). This custom
12-instruction set enables basic program execution on our FPGA CPU for testing
the impedance side channel. Table I summarizes the instruction operations,
which are briefly described below.

LOAD, STORE, SET:

LOAD and SET transfer data into registers, while STORE transfers data from a
register to memory. LOAD and STORE use the syntax: Opcode R1, R2, K. For LOAD,
R1 receives the value. For STORE, R1 provides the output value. R2 contains
the base address, and K is an offset constant. SET uses the syntax: Opcode R1,
K. R1 is the target register, and K is the 8-bit value to assign.

ADD, SUB, AND, OR, XOR:

The arithmetic and logic instructions (ADD, SUB, AND, OR, XOR) follow the
syntax: Opcode R1, R2, R3. They perform operations between registers R2 and
R3, storing the result in R1. Specifically, ADD does addition, SUB does
subtraction, AND performs a logical AND, OR does a logical OR, and XOR
executes an exclusive OR.

SHL, SHR:

These two instructions have the syntax: Opcode R1, R2, R3. The SHL and SHR
instructions shift the bits in the R2 register value left or right,
respectively, by the number of bit positions specified in the R3 register and
store the result in the R1 register. The least significant bits (LSBs) and
most significant bits (MSBs) are padded with zeros following the SHL and SHR,
respectively.

BEQ, BNEQ:

The BEQ and BNEQ instructions follow the syntax: Opcode R1, K and allow
conditional branching based on comparing a register, R1, and constant, K. BEQ
skips the next instruction by increasing programming counter, $PC$, by 2 if
they are equal. BNEQ does the opposite (skips is they are not equal).

Similarly, for the Arduino’s ATmega328P AVR microcontroller, we adhere to the
conventional assembly instructions provided by the manufacturer [24]. We
select 11 representative instructions, summarized in Table I, consisting data
transfer, arithmetic/logic, rotate (SHL, SHR), and branch operations. The
8-bit ATmega328P is a RISC microcontroller with 1 KB EEPROM, 2 KB SRAM, 23
GPIO, and 32 general registers. The chosen instruction set mirrors the
functionality of the custom FPGA instructions, leveraging the ATmega328P’s
standard feature set. The following paragraph briefly outlines the operations
of the instructions.

MOV, LDI:

MOV instruction is used to transfer data from one register to another, while
LDI instruction is used to load an immediate to the designated register.

ADD, SUB, AND, OR, EOR:

These instructions execute the arithmetic and logical operations. ADD, SUB,
AND, OR, EOR perform the addition, subtraction, logical AND, OR, and XOR
operations, respectively.

LSL, LSR:

LSL, and LSR shift one bit of the specified register value to the left or
right, respectively. The LSBs and MSBs are padded with zeros following the LSL
and LSR instructions, respectively.

BREQ, BRNE:

The BREQ (branch if equal) and BNEQ (branch if not equal) instructions control
program flow based on the zero flag, $Z$. They are often used after arithmetic
operations that set or reset $Z$. If $Z$ is 0, BREQ will branch to a different
instruction sequence instead of the next immediate instruction. BNEQ branches
if $Z$ is not 0. By manipulating the program counter ($PC$), these
instructions create conditional loops and branching logic.

(a)

(b)

Figure 3: Assembly code snippet followed in the experiment: (a) Artix 7 FPGA,
(b) ATmega328P microcontroller.

The assembly code executed for the experiment runs all instructions in Table I
on both the Artix 7 FPGA and ATmega328P microcontroller platforms. Figure 3
and Figure 3(b) illustrate simplified block diagrams representing the
instruction flow for the FPGA and microcontroller, respectively. We follow
these instruction flows to collect impedance signals with no particular
computational purpose. Figure 3(b) includes two additional instructions, CPI
and RJMP, used only for the ATmega328P to control program flow. The CPI
instruction compares an immediate value to a register value and sets the zero
flag $Z$. The RJMP instruction performs a relative jump to a specified
location in the code.

###  IV-C Signal Collection

In our study, we use the Rigol RSA5032N spectrum analyzer configured as a
vector network analyzer (VNA). The RSA5032N contains built-in circuitry to
perform VNA measurements and supports standard commands for programmable
instruments (SCPI). SCPI instructions transfer the trace data over Ethernet in
complex format. Therefore, the received complex trace values need to be
transformed into impedance values for analysis.

Let $T_{Re,m}$, and $T_{Im,m}$ represent the real and imaginary portions of
the trace at frequency $m$. First, we convert the real and imaginary
components to resistance $R_{m}$, and reactance, $X_{m}$ using Equation. 13
and Equation. 14, respectively [25]. All raw traces are collected during
software instruction execution and transformed into impedance signals.

$\displaystyle R_{m}$
$\displaystyle=Z_{ref}*\frac{(1-T_{Re,m}^{2}-T_{Im,m}^{2})}{(1-T_{Re,m})^{2}+T_{Im,m}^{2}}$
(13) $\displaystyle X_{m}$
$\displaystyle=Z_{ref}*\frac{2*T_{Im,m}}{(1-T_{Re,m})^{2}+T_{Im,m}^{2}}$ (14)

Here, $Z_{ref}$ is the reference impedance of the measurement instrument. The
overall complex impedance, $Z_{T,m}$, at the trace point $m$ is calculated as,

$\displaystyle Z_{T,m}=R_{m}+iX_{m}$ (15)

We specify 10,001 linearly spaced frequency points from 500kHz to 4GHz. At
each point, we compute the average of 100 sampled measurements. This is
repeated to collect signals for each instruction execution. Using a custom
Python script with SCPI commands, we collect 700 signals per FPGA instruction
(8,400 total) and 500 signals per microcontroller instruction (5,500 total).
These raw signals are in complex form. The complex trace signals are converted
to impedance using Equation 15, where $Z_{ref}$ is the 50 $\Omega$ reference
impedance. By transforming the complex trace values into impedance, we obtain
the necessary data for analysis. The resulting impedance signals are then
labeled for supervised learning.

(a)

(b)

Figure 4: Impedance profile of program instructions. (a) Artix 7: LOAD, ADD,
BEQ, (b) ATmega328P: MOV, ADD, BREQ.

##  V Evaluation

###  V-A Signal Analysis

The impedance profiles for each instruction execution are visibly distinct, as
seen in Figure 4(a) for three Artix 7 operations (LOAD, AND, BNEQ) and Figure
4(b) for the ATmega328P (MOV, ADD, BREQ). Though subtle, variations between
instructions become evident at certain frequencies. This motivates the removal
of redundant frequency points from the raw impedance signals. Further analysis
uses the impedance magnitude values as they present most of the information
[13, 26]. At each measured frequency, the signals follow a Gaussian
distribution, representing additive white Gaussian thermal noise. Figure 5
histograms illustrate the normal distribution of impedances at two of the
selected frequencies.

(a)

(b)

(c)

(d)

Figure 5: Impedance profile distribution: Artix 7 at (a) 1 GHz, (b) 2.3 GHz,
and ATmega328P at (c) 1 GHz, (d) 2.3 GHz.

(a) Artix 7: two major principal component distributions.

(b) ATmega328P: two major principal component distributions.

Figure 6: Distribution of the two most significant principal components for
multiple program instructions.

###  V-B Signal Processing

To determine relevant frequency points, we compute the Pearson correlation
coefficient between the impedance signal at each frequency and the program
instruction set. This allows us to select a subset of the 10,001 total
frequency points where the impedance responses are highly correlated with
changes in instruction execution. Frequency points with lower correlation to
instruction changes are rejected.

The impedance value at a particular frequency is denoted as $X$ and the
instruction set as $I$. For $n$ sample pairs
{($X_{1},I_{1}$),…,($X_{n},I_{n}$)}, the Pearson correlation coefficient
$\rho_{XI}$ is calculated as:

$\displaystyle\rho_{XI}=\frac{n\sum X_{i}I_{i}-\sum X_{i}\sum
I_{i}}{\sqrt{n\sum X_{i}^{2}-(\sum X_{i})^{2}}\sqrt{n\sum I_{i}^{2}-(\sum
I_{i})^{2}}}$ (16)

We select the largest set of frequencies where the impedance responses are
fairly orthogonal, allowing us to further reduce the number of points. Using
Equation 16, we calculate the Pearson correlation coefficients between $X_{i}$
(impedance at one frequency) and $Y_{i}$ (impedance at another frequency). We
choose the maximum number of frequencies where the intra-group impedance
responses are less than 85%. In other words, the impedance variations at
rejected frequencies can be explained by the impedance at selected
frequencies. Since impedance at the chosen frequencies can explain the
rejected points, we termed these the Dominant frequency points.

Using this two-step frequency selection, we locate approximately 3600 and 2700
frequency points for the FPGA and ATmega328P, respectively, that adequately
characterize the software instructions. Notably, these represent just 36% and
27% of the total observable frequency points. We then collect additional
impedance signals during various program executions at the specified
frequencies to construct the test dataset. By selecting dominant orthogonal
frequencies, we drastically reduce the data required while retaining the
information needed to reverse-engineer software instructions.

###  V-C Feature Extraction

We use the training data to identify features associated with each
instruction’s execution. We perform principal component analysis (PCA) [27] on
the signals to extract these features and then input them to the machine
learning (ML) classifiers.

To reduce training time and increase accuracy, we select a subset of principal
components that account for 95% of the variance in the training data. Using
these key components as features improves performance of the classifiers.
Figure 6(a) and Figure 6(b) show the distribution of the two most significant
principal components for the FPGA and microcontroller instructions,
respectively. The axes correspond to the data projected onto the top two
components.

###  V-D Performance Metrics

To evaluate classifier performance, we observe five key metrics: recall rate
(true positive rate), specificity (true negative rate), precision, accuracy,
and F1-score [28]. All classes are weighted equally when calculating the macro
average of these metrics. Let $TP_{i}$, $TN_{i}$, $FP_{i}$, and $FN_{i}$
represent the true positives, true negatives, false positives, and false
negatives predicted by a given classifier for class $i$. The metrics are
defined as:

$\displaystyle
Recall=\frac{1}{i}\sum_{i}\left(\frac{TP_{i}}{TP_{i}+FN_{i}}\right)$ (17)
$\displaystyle
Specificity=\frac{1}{i}\sum_{i}\left(\frac{TN_{i}}{TN_{i}+FP_{i}}\right)$ (18)
$\displaystyle
Precision=\frac{1}{i}\sum_{i}\left(\frac{TP_{i}}{TP_{i}+FP_{i}}\right)$ (19)
$\displaystyle
Accuracy=\frac{1}{i}\sum_{i}\left(\frac{TP_{i}+TN_{i}}{TP_{i}+TN_{i}+FP_{i}+FN_{i}}\right)$
(20) $\displaystyle F1-score=\frac{2\times Precision\times
Recall}{Precision+Recall}$ (21)

We use Equation (17)-(21) to calculate the performance metrics and compare the
performance of the classifiers.

###  V-E Detection and Classification

We use a number of ML models, including support vector machine (SVM), adaptive
boosting (AdaBoost), k-nearest neighbors (kNN), linear discriminant, gaussian
naive bayes [28]. These models are trained to detect and classify program
instructions. We utilize 10-fold cross-validation during training to improve
stability, avoid overfitting and select the top performer based on its 10-fold
cross-validation score.

TABLE II: Classification scores for detecting program instruction. Device | Classifier [28] | Validation Score | F1-Score | Recall | Specificity | Precision | Accuracy
---|---|---|---|---|---|---|---
FPGA | SVM (Kernel: Linear) | 92.8% | 92.6% | 92.7% | 99.3% | 92.7% | 92.6%
AdaBoost | 91.8% | 92.0% | 92.0% | 99.3% | 92.1% | 92.0%
Linear Discriminant | 86.6% | 87.2% | 87.3% | 98.8% | 87.3% | 87.3%
ATmega328P | SVM (Kernel: Quadratic) | 95.0% | 96.1% | 96.1% | 99.6% | 96.1% | 96.1%
Bagged trees | 92.5% | 91.6% | 91.7% | 99.2% | 91.6% | 91.6%
Linear Discriminant | 88.9% | 92.2% | 92.0% | 99.2% | 92.8% | 92.2%

(a)

(b)

Figure 7: Confusion matrix of reverse-engineered program instructions: (a)
Artix 7 FPGA, (b) ATmega328P microcontroller.

After extracting instruction-specific features from the signals as outlined in
previous sections (Section V-B, Section V-C), the models are evaluated on a
30% held-out test set. The SVM performs exceptionally well and achieves top
classification performance, with F1 score, precision, recall, specificity, and
accuracy all over 92% on the test data. This demonstrates the viability of our
proposed approach using impedance side channel for reverse engineering program
instructions. The findings of the classification of individual program
instructions are presented in Table II. The confusion matrix in Figure 7
provides further insight into the performance of the top classifier, SVM,
along with the positive predictive value (PPV), false discovery rate (FDR),
true positive rate (TPR), and false negative rate (FNR). PPV represents the
probability that a predicted result is actually correct, whereas FDR is the
complement of PPV. A high PPV indicates the reliability of the trained model,
and the false positive rate is the complement of specificity. Among the other
classifiers, SVM demonstrates the ability to accurately differentiate between
the various instructions with minimal confusion and a top 10-fold cross-
validation score.

In summary, by leveraging ML algorithms and extracted signal features, our
method of using impedance as a side channel can reliably identify and reverse-
engineer program instructions executed on a chip. The exceptional
classification results from the SVM highlight the promise of this technique.

##  VI Related Works

Side Channel Analysis in Hardware Defense: Side channels in hardware have been
leveraged both for extracting sensitive information and securing systems. For
example, the authors in [29] use timing-based information leakage and simple
power analysis to analyze vulnerabilities in embedded neural networks. In
[30], an EM side channel-based hardware Trojan detection is proposed by
spectrum modeling and analyzing. Authors in [31], detect board-level
modifications by measuring impedance at various locations. Another approach in
[32] detects Trojans by monitoring impedance changes in integrated circuit
wires. Thus, prior works have demonstrated side channels like timing, power,
EM emissions, and impedance can be exploited for analyzing hardware
vulnerabilities, detecting Trojans, and identifying malicious modifications.
Our research similarly uses impedance as a side channel, but with the novel
goal of reverse engineering software instructions.

Side Channel Analysis in Software Defense: Recent work has leveraged physical
side channels produced by embedded micro-controllers to infer internal
behavior and operations. For example, authors in [33] present an analytical
approach to assess the security of hardware performance counters (HPCs) for
malware detection. Their framework analyzes the probability of malware
detection given a program, set of HPCs, and sampling rate. In [34], the
authors present a method utilizing power side channel and ML on statistical
trace features to detect run-time malware in medical devices. Analyzing EM
emissions is another approach explored in prior art [35] detected malicious
programmable logic controller (PLC) code by training a sequential neural
network model on pre-processed frequency data to encode control flow
transitions. Other works include detecting behavioral changes in industrial
control systems [36], and identifying malicious PLC code [37]. Beyond EM and
power analysis, recent work has examined backscattering side channels
modulated by impedance variations [12]. It should be noted that the
backscattering side channel in the paper exploits variations in the signal
reflected back from the device. These variations in the reflected signal are
caused by changes in the impedance.
Side channel Analysis in Code Reverse Engineering: The authors in [38]
implement an instruction classifier for the PIC16F687 microcontroller by
performing a template attack using the power side channel. With statistical
models like hidden Markov models (HMMs), they achieve 70.1% accuracy over 35
test instructions. By modeling control flows with HMMs on an 8-bit AVR,
authors in [39] measure voltage drops on the power pin to track code execution
and detect abnormalities. Authors in [40] utilize instruction-level power side
channel leakage profiles for detecting program instructions executed on an
embedded processor. Other works include using localized EM probes for dynamic
code recognition [41].

The extensive prior art demonstrates side channels can reveal rich details
about a device’s internal operations. Our work similarly leverages impedance
as a side channel, but with the unique goal of reverse engineering software
instructions on FPGA and microcontroller platforms. By contrast, most existing
techniques focus on malware detection, behavior identification, and code
profiling rather than reverse engineering the actual opcodes. The ability to
reliably reconstruct sequences of software instructions will open up new
possibilities for observation, verification, and reverse engineering of
embedded and cyber-physical systems.

##  VII Conclusion

In this paper, we investigated the potential of using impedance side channel
to identify program instructions. We used hardware platforms including an
Artix 7 FPGA and ATmega328P microcontroller, each with a unique instruction
set. By analyzing the impedance signals, we generated fingerprints and
employed machine learning classifiers. We found specific instructions could be
identified with 92.6% accuracy on the FPGA and 96.1% on the microcontroller.
This research pioneers the use of impedance as an active side channel for
hardware security. It shows device impedance can reveal executed instructions,
opening new possibilities for code recognition, code flow analysis, code
reverse engineering and embedded systems security. Analyzing the relationship
between impedance and software represents an important advance. It promises to
revolutionize techniques for strengthening resilience against cyberthreats in
an increasingly connected world. In conclusion, transforming impedance from a
passive, overlooked property into an active, potent side channel marks a
critical step forward for the field.

## Acknowledgement

This work is supported partly by the National Science Foundation Award #
2114200 and the National Security Agency Award # H98230-22-1-0327.

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