payload: {"push_id":4499781834,"size":443,"distinct_size":7,"ref":"refs/heads/clover_support_hmm","head":"be642ee2ed74b4cd691a0152626f200d4a47a950","before":"8cc7979378c853f563afd0d5945da03d47eb3c44","commits":[{"sha":"072e95e07ad940d95c78291c6422172346b74c50","author":{"name":"Jonathan Marek","email":"3692bfa45759a67d83aedf0045f6cb635a966abf@marek.ca"},"message":"freedreno/ir3: update prefetch input_offset when packing inlocs\n\nIf the input location changes then prefetch input_offset needs to change.\n\nSigned-off-by: Jonathan Marek <jonathan@marek.ca>\nReviewed-by: Eric Anholt <eric@anholt.net>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/072e95e07ad940d95c78291c6422172346b74c50"},{"sha":"afdc0121b55e8543118c003307b20d90e14329e7","author":{"name":"Lionel Landwerlin","email":"9463032a5b99ffad10f36631678a833369a311b5@intel.com"},"message":"i965/iris/perf: factor out frequency register capture\n\nSigned-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>\nReviewed-by: Mark Janes <mark.a.janes@intel.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/afdc0121b55e8543118c003307b20d90e14329e7"},{"sha":"636175da6dabc28f1b289bca07ecb09bee820472","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"dcos: add releanse notes for 19.3.1","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/636175da6dabc28f1b289bca07ecb09bee820472"},{"sha":"d32e1257c0471cb4f1732d9777b39e77d8f8172e","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs: Add release notes, update calendar, and add news for 19.3.1","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/d32e1257c0471cb4f1732d9777b39e77d8f8172e"},{"sha":"2f724d2202804f74fe691d0be27bd9e5a506e805","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs: add relnotes for 19.2.8","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/2f724d2202804f74fe691d0be27bd9e5a506e805"},{"sha":"7017f69a64121cc9247144f8fec63b61477ac1b5","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs/relnotes/19.2.8: Add SHA256 sum","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/7017f69a64121cc9247144f8fec63b61477ac1b5"},{"sha":"69decdb28a8d6b3a7169ea6729ee111765a7d386","author":{"name":"Dylan Baker","email":"dd378c4ca75f71f527acddef5b43fc35b68d5b7a@pnwbakers.com"},"message":"docs: Add release notes, news, and update calendar for 19.2.8","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/69decdb28a8d6b3a7169ea6729ee111765a7d386"},{"sha":"a9a3108be774aea620fa4fc726c33100d9a49add","author":{"name":"Bas Nieuwenhuizen","email":"1d31d94f30d40df7951505d1034e1e923d02ec49@basnieuwenhuizen.nl"},"message":"radv: Limit workgroup size to 1024.\n\nFixes a hang with geekbench.\n\nThe existence of RX 580 and NAVI10 results shows that the generations\nbefore and after this do not have the issue. (They show up on the\nwebsite). So this is likely a GFX9 only issue.\n\nThis is not something weird like LDS size since none of the shaders\nseem to use LDS.\n\nCC: <mesa-stable@lists.freedesktop.org>\nReviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/a9a3108be774aea620fa4fc726c33100d9a49add"},{"sha":"cfa1fb895ac5a752772f4d0748c1c2bce0c2e653","author":{"name":"Connor Abbott","email":"71178acffcc112b21e5858656e5751f5e4aa9364@gmail.com"},"message":"a6xx: Add more CP packets\n\nAnd add fields uncovered by looking at the firmware. I think this covers\nall the memory, register, and scratch manipulation opcodes that exist on\nA6xx, plus one additional nice find for Vulkan and describing a\npreviously unknown opcode and documenting CP_WAIT_REG_MEM.\n\nNote that the bits for the CP_REG_TO_MEM count, as well as the formula\nfor computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG,\nare changed because the A630 SQE firmware actually does something\ndifferent. I haven't investigated older microcodes to see whether this\nextends back to A5xx and A4xx, but the only non-A6xx uses of this\nfield result in the same bit-pattern when using the A6xx bit range and\nformula, so it should be safe to change the definition universally.\n\nReviewed-by: Kristian H. Kristensen <hoegsberg@google.com>\nReviewed-by: Rob Clark <robdclark@gmail.com>\nReviewed-by: Eric Anholt <eric@anholt.net>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/cfa1fb895ac5a752772f4d0748c1c2bce0c2e653"},{"sha":"4c5ac156c36b697e3605a8143aafd332dd1a15e7","author":{"name":"Connor Abbott","email":"71178acffcc112b21e5858656e5751f5e4aa9364@gmail.com"},"message":"freedreno: Use new macros for CP_WAIT_REG_MEM and CP_WAIT_MEM_GTE\n\nSimilar to the existing usage for CP_COND_WRITE5, this makes it clear\nwhat each of the magic parameters are for.\n\nReviewed-by: Kristian H. Kristensen <hoegsberg@google.com>\nReviewed-by: Rob Clark <robdclark@gmail.com>\nReviewed-by: Eric Anholt <eric@anholt.net>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/4c5ac156c36b697e3605a8143aafd332dd1a15e7"},{"sha":"648cc22afb6855bf68c83912502454c23adad951","author":{"name":"Connor Abbott","email":"71178acffcc112b21e5858656e5751f5e4aa9364@gmail.com"},"message":"freedreno: Fix CP_MEM_TO_REG flag definitions\n\nThese actually mean something completely different, at least on A5xx\nand A6xx. The only other usage of the old flags on something older than\nA6xx was a typo, so I don't know if it was always this way, but at the\nsame time it means that we don't have to worry too much about that.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/648cc22afb6855bf68c83912502454c23adad951"},{"sha":"fc2552b6445a1295c18acf8798411da85bbc5387","author":{"name":"Lionel Landwerlin","email":"9463032a5b99ffad10f36631678a833369a311b5@intel.com"},"message":"loader: fix close on uninitialized file descriptor value\n\nUsing a drm syscall layer faking a kernel driver :\n\n  ==581460== Conditional jump or move depends on uninitialised value(s)\n  ==581460==    by 0x48A4C2B: close (drm-hooks.cpp:185)\n  ==581460==    by 0x5A815F1: dri3_alloc_render_buffer (loader_dri3_helper.c:1469)\n  ==581460==    by 0x5A82050: dri3_get_buffer (loader_dri3_helper.c:1827)\n  ==581460==    by 0x5A82662: loader_dri3_get_buffers (loader_dri3_helper.c:2028)\n  ==581460==    by 0x6C78109: intel_update_image_buffers (brw_context.c:1870)\n  ==581460==    by 0x6C77805: intel_update_renderbuffers (brw_context.c:1499)\n  ==581460==    by 0x6C7789D: intel_prepare_render (brw_context.c:1520)\n  ==581460==    by 0x6C773D4: intelMakeCurrent (brw_context.c:1341)\n\nSigned-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>\nFixes: 069fdd5f9fac (\"egl/x11: Support DRI3 v1.1\")\nReviewed-by: Eric Anholt <eric@anholt.net>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/fc2552b6445a1295c18acf8798411da85bbc5387"},{"sha":"4a59bc6df2baf3be1d8bc8dbcd04b7b02df13560","author":{"name":"Jonathan Marek","email":"3692bfa45759a67d83aedf0045f6cb635a966abf@marek.ca"},"message":"turnip: add cache invalidate to fix input attachment cases\n\nFixes artifacts in the subpasses demo.\n\nWorkaround texture cache with input attachments from GMEM by adding a cache\ninvalidate between subpasses.\n\nSigned-off-by: Jonathan Marek <jonathan@marek.ca>\nReviewed-by: Eric Anholt <eric@anholt.net>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/4a59bc6df2baf3be1d8bc8dbcd04b7b02df13560"},{"sha":"5785bcc8a0ff9c5072c647337bf73f696c63cbe6","author":{"name":"Jonathan Marek","email":"3692bfa45759a67d83aedf0045f6cb635a966abf@marek.ca"},"message":"turnip: don't set SP_FS_CTRL_REG0_VARYING if only fragcoord is used\n\nFixes artifacts in the subpasses demo, which has a shader using fragcoord\nwithout any varyings. It looks like setting this bit when there are no\nvaryings can cause weirdness in some cases (without this change, if the\nprevious shader had <= 8 varyings it would work, but with 9 varyings it\nwould have artifacts).\n\nSigned-off-by: Jonathan Marek <jonathan@marek.ca>\nReviewed-by: Eric Anholt <eric@anholt.net>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/5785bcc8a0ff9c5072c647337bf73f696c63cbe6"},{"sha":"b31d1b73bc6bcb64ff37ecb0805646d8b09c6427","author":{"name":"Erik Faye-Lund","email":"552315cf0e00b9487eaead400a0dcdd46f0528a2@collabora.com"},"message":"zink: enable PIPE_CAP_MIXED_COLORBUFFER_FORMATS\n\nThis just works in Vulkan, there's no work neeed to enable it.\n\nReviewed-by: Dave Airlie <airlied@redhat.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/b31d1b73bc6bcb64ff37ecb0805646d8b09c6427"},{"sha":"af65bfb38fa56bf6a28dd4b681ca123b9c05a827","author":{"name":"Erik Faye-Lund","email":"552315cf0e00b9487eaead400a0dcdd46f0528a2@collabora.com"},"message":"zink: implement nir_texop_txd\n\nThis lets us enable PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, which in turns\ngives us ARB_shader_texture_lod.\n\nStill fails one piglit test on ANV, namely\nspec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,\nbut with 33 new passing tests, I think this is worth it.\n\nReviewed-by: Dave Airlie <airlied@redhat.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/af65bfb38fa56bf6a28dd4b681ca123b9c05a827"},{"sha":"8172b1fa03fe74165728bfb182c98a3e62193d2b","author":{"name":"Juan A. Suarez Romero","email":"af79b5692270b306571bb1d8bbe0285ae3ac93d9@igalia.com"},"message":"nir/lower_double_ops: relax lower mod()\n\nCurrently when lowering mod() we add an extra instruction so if\nmod(a,b) == b then 0 is returned instead of b, as mathematically\nmod(a,b) is in the interval [0, b).\n\nBut Vulkan spec has relaxed this restriction, and allows the result to\nbe in the interval [0, b].\n\nThis commit takes this in account to remove the extra instruction\nrequired to return 0 instead.\n\nReviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/8172b1fa03fe74165728bfb182c98a3e62193d2b"},{"sha":"f3cccd05d9f6e9d05c18d1a3a5f9eb863e4f264b","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"radv/gfx10: fix the out-of-bounds check for vertex descriptors\n\nWhen stride is 0, it should check against the offset not the index.\n\nThis fixes black character models with Beat Saber and missing snow\nwith Dragon Quest.\n\nCloses: https://gitlab.freedesktop.org/mesa/mesa/issues/2233\nCloses: https://gitlab.freedesktop.org/mesa/mesa/issues/1975\nCc: <mesa-stable@lists.freedesktop.org>\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/f3cccd05d9f6e9d05c18d1a3a5f9eb863e4f264b"},{"sha":"13b4e9adcfd60eb704528c637a8acb9651bc280c","author":{"name":"Samuel Pitoiset","email":"506e97eed81d9e59d22f4c73fb51123bb62b4a30@gmail.com"},"message":"ac: declare an enum for the OOB select field on GFX10\n\nSigned-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/13b4e9adcfd60eb704528c637a8acb9651bc280c"},{"sha":"5710250074a066288c0ed44fd796baa0c4d0f42b","author":{"name":"Alyssa Rosenzweig","email":"f464ae820bbc3d32045ebe0b6ab93746c20733e8@collabora.com"},"message":"pan/midgard: Add uniform/work heuristic\n\nUniform/work registers are partitioned on a shader-by-shader basis as\ndetermined by the compiler. We add a simple heuristic here running\nbefore scheduling that prioritizes mitigating spilling at all costs.\n\nA more sophisticated heuristic should run *after* scheduling, doing a\ndry run of the register allocator itself to determine spilling. Fitting\nthis into our current scheduling model is difficult, so while this\nheuristic does hurt some shaders, overall the results are acceptable:\n\ntotal instructions in shared programs: 50065 -> 38747 (-22.61%)\ninstructions in affected programs: 37187 -> 25869 (-30.44%)\nhelped: 59\nHURT: 77\nhelped stats (abs) min: 1 max: 757 x̄: 198.46 x̃: 151\nhelped stats (rel) min: 0.48% max: 62.89% x̄: 32.95% x̃: 36.27%\nHURT stats (abs)   min: 1 max: 9 x̄: 5.08 x̃: 6\nHURT stats (rel)   min: 0.92% max: 14.29% x̄: 6.71% x̃: 4.60%\n95% mean confidence interval for instructions value: -111.15 -55.29\n95% mean confidence interval for instructions %-change: -14.33% -6.67%\nInstructions are helped.\n\ntotal bundles in shared programs: 30606 -> 19157 (-37.41%)\nbundles in affected programs: 23907 -> 12458 (-47.89%)\nhelped: 58\nHURT: 74\nhelped stats (abs) min: 6 max: 757 x̄: 203.09 x̃: 152\nhelped stats (rel) min: 5.19% max: 77.00% x̄: 49.38% x̃: 53.79%\nHURT stats (abs)   min: 1 max: 9 x̄: 4.46 x̃: 5\nHURT stats (rel)   min: 1.85% max: 26.32% x̄: 11.70% x̃: 9.57%\n95% mean confidence interval for bundles value: -115.46 -58.01\n95% mean confidence interval for bundles %-change: -20.87% -9.41%\nBundles are helped.\n\ntotal quadwords in shared programs: 31305 -> 32027 (2.31%)\nquadwords in affected programs: 20471 -> 21193 (3.53%)\nhelped: 0\nHURT: 133\nHURT stats (abs)   min: 1 max: 9 x̄: 5.43 x̃: 5\nHURT stats (rel)   min: 0.76% max: 15.15% x̄: 5.47% x̃: 4.65%\n95% mean confidence interval for quadwords value: 5.00 5.86\n95% mean confidence interval for quadwords %-change: 4.85% 6.08%\nQuadwords are HURT.\n\ntotal registers in shared programs: 2256 -> 2545 (12.81%)\nregisters in affected programs: 708 -> 997 (40.82%)\nhelped: 0\nHURT: 95\nHURT stats (abs)   min: 1 max: 8 x̄: 3.04 x̃: 3\nHURT stats (rel)   min: 12.50% max: 100.00% x̄: 39.41% x̃: 37.50%\n95% mean confidence interval for registers value: 2.64 3.45\n95% mean confidence interval for registers %-change: 34.62% 44.19%\nRegisters are HURT.\n\ntotal threads in shared programs: 1776 -> 1709 (-3.77%)\nthreads in affected programs: 134 -> 67 (-50.00%)\nhelped: 0\nHURT: 67\nHURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1\nHURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%\n95% mean confidence interval for threads value: -1.00 -1.00\n95% mean confidence interval for threads %-change: -50.00% -50.00%\nThreads are HURT.\n\ntotal spills in shared programs: 3868 -> 2 (-99.95%)\nspills in affected programs: 3868 -> 2 (-99.95%)\nhelped: 60\nHURT: 0\n\ntotal fills in shared programs: 6456 -> 4 (-99.94%)\nfills in affected programs: 6456 -> 4 (-99.94%)\nhelped: 60\nHURT: 0\n\nSigned-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>\nTested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>\nPart-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>","distinct":false,"url":"https://api.github.com/repos/karolherbst/mesa/commits/5710250074a066288c0ed44fd796baa0c4d0f42b"}]}
other: {"actor":{"display_login":"karolherbst"}}