payload: {"action":"created","comment":{"url":"https://api.github.com/repos/pcengines/apu2-documentation/pulls/comments/255504506","pull_request_review_id":202102043,"id":255504506,"node_id":"MDI0OlB1bGxSZXF1ZXN0UmV2aWV3Q29tbWVudDI1NTUwNDUwNg==","diff_hunk":"@@ -156,11 +156,59 @@ This can be the source of some reboot problems, but it is hard to test in a\n reliable way - reset is asynchronous event that have to take place in very short\n amount of time during transition.\n \n+## Voltage regulator\n+\n+CPU communicates with voltage regulator using SVI2 (Serial VID Interface 2.0).\n+Typically, after all frequency and voltage dependencies described above are\n+resolved, transition to higher performance follows a sequence:\n+\n+1. SVI2 command is send to the voltage regulator, `D18F5x12C[Svi2CmdBusy]`\n+   is set.\n+2. Voltage regulator sets the requested voltage, waits for it to stabilize and\n+   clears `Svi2CmdBusy`.\n+3. After `Svi2CmdBusy` is clear frequency change is performed.\n+\n+Transition towards lower performance starts with frequency change and doesn't\n+have to wait for it to finish before changing voltage. Because of these\n+restrictions it is impossible for CPU to work with high frequency and too low\n+voltage for that frequency.\n+\n+Multiple requests can be grouped:\n+\n+> * If multiple commands are issued that affect the P-state of a domain prior\n+>   to when the processor initiates the change of the P-state of that domain,\n+>   then the processor operates on the last one issued.\n+> * Once a P-state change starts, the P-state state machine (PSSM) continues\n+>   through completion unless interrupted by a PWROK deassertion. If multiple\n+>   P-state changes are requested concurrently, the PSSM may group the\n+>   associated VID changes separately from the associated COF changes.\n+\n+Setting `D18F5x12C[WaitVidCompDis]` changes behaviour of transition towards\n+higher performance - instead of waiting for voltage regulator to report end of\n+transition next request can be made after a defined time period\n+(`D18F3xD8[VSRampSlamTime]`).\n+\n+## Findings from logs obtained from community\n+\n+Registers values from community revealed that CPU had voltage of (software) P0,\n+but its frequency was stuck at a value of P2. Voltage change to P0 was requested\n+but not reported as done by voltage regulator for some reason.","path":"docs/debug/cpu_frequency.md","position":49,"original_position":49,"commit_id":"58f09e997e485b78d75a0efb49c4d8c62af3c707","original_commit_id":"58f09e997e485b78d75a0efb49c4d8c62af3c707","user":{"login":"pietrushnic","id":1071894,"node_id":"MDQ6VXNlcjEwNzE4OTQ=","avatar_url":"https://avatars3.githubusercontent.com/u/1071894?v=4","gravatar_id":"","url":"https://api.github.com/users/pietrushnic","html_url":"https://github.com/pietrushnic","followers_url":"https://api.github.com/users/pietrushnic/followers","following_url":"https://api.github.com/users/pietrushnic/following{/other_user}","gists_url":"https://api.github.com/users/pietrushnic/gists{/gist_id}","starred_url":"https://api.github.com/users/pietrushnic/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/pietrushnic/subscriptions","organizations_url":"https://api.github.com/users/pietrushnic/orgs","repos_url":"https://api.github.com/users/pietrushnic/repos","events_url":"https://api.github.com/users/pietrushnic/events{/privacy}","received_events_url":"https://api.github.com/users/pietrushnic/received_events","type":"User","site_admin":false},"body":"@krystian-hebel there are some parts compatible with SVI2:\r\n\r\n* https://docplayer.net/51160536-Rt8870a-dual-output-pwm-controller-for-amd-svi-mobile-cpu-power-supply.html\r\n* https://www.infineon.com/dgdl/Infineon-IR35201MTRPBF-DS-v01_00-EN.pdf?fileId=5546d462576f347501579c95d19772b5\r\n* https://media.digikey.com/pdf/Data%20Sheets/ON%20Semiconductor%20PDFs/NCP81022.pdf\r\n\r\nAnyway to not make this discussion longer, please fill JIRA item in content marketing and we will see if there will be time and resources to take care of that in future.","created_at":"2019-02-11T13:24:14Z","updated_at":"2019-02-11T13:24:14Z","html_url":"https://github.com/pcengines/apu2-documentation/pull/129#discussion_r255504506","pull_request_url":"https://api.github.com/repos/pcengines/apu2-documentation/pulls/129","author_association":"MEMBER","_links":{"self":{"href":"https://api.github.com/repos/pcengines/apu2-documentation/pulls/comments/255504506"},"html":{"href":"https://github.com/pcengines/apu2-documentation/pull/129#discussion_r255504506"},"pull_request":{"href":"https://api.github.com/repos/pcengines/apu2-documentation/pulls/129"}},"in_reply_to_id":244716778},"pull_request":{"url":"https://api.github.com/repos/pcengines/apu2-documentation/pulls/129","id":239812876,"node_id":"MDExOlB1bGxSZXF1ZXN0MjM5ODEyODc2","html_url":"https://github.com/pcengines/apu2-documentation/pull/129","diff_url":"https://github.com/pcengines/apu2-documentation/pull/129.diff","patch_url":"https://github.com/pcengines/apu2-documentation/pull/129.patch","issue_url":"https://api.github.com/repos/pcengines/apu2-documentation/issues/129","number":129,"state":"open","locked":false,"title":"cpu_frequency.md: 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