payload: {"push_id":3813876228,"size":798,"distinct_size":2,"ref":"refs/heads/caf/3.10/caf/linux-next/master","head":"2c51253c171447ec896072c50c037c4f984582f7","before":"1481057642d5bfe4f8a9d9144ab62ccf7c5f7517","commits":[{"sha":"b119019847fbcac36ed1384f166c91f177d070e7","author":{"name":"Jim Mattson","email":"69e6c825ffb81c81b96935a61b79166dbc1f7a9d@google.com"},"message":"kvm: nVMX: Remove unnecessary sync_roots from handle_invept\n\nWhen L0 is executing handle_invept(), the TDP MMU is active. Emulating\nan L1 INVEPT does require synchronizing the appropriate shadow EPT\nroot(s), but a call to kvm_mmu_sync_roots in this context won't do\nthat. Similarly, the hardware TLB and paging-structure-cache entries\nassociated with the appropriate shadow EPT root(s) must be flushed,\nbut requesting a TLB_FLUSH from this context won't do that either.\n\nHow did this ever work? KVM always does a sync_roots and TLB flush (in\nthe correct context) when transitioning from L1 to L2. That isn't the\nbest choice for nested VM performance, but it effectively papers over\nthe mistakes here.\n\nRemove the unnecessary operations and leave a comment to try to do\nbetter in the future.\n\nReported-by: Junaid Shahid <junaids@google.com>\nFixes: bfd0a56b90005f (\"nEPT: Nested INVEPT\")\nCc: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>\nCc: Nadav Har'El <nyh@il.ibm.com>\nCc: Jun Nakajima <jun.nakajima@intel.com>\nCc: Xinhao Xu <xinhao.xu@intel.com>\nCc: Yang Zhang <yang.z.zhang@Intel.com>\nCc: Gleb Natapov <gleb@redhat.com>\nCc: Paolo Bonzini <pbonzini@redhat.com>\nReviewed-by Peter Shier <pshier@google.com>\nReviewed-by: Junaid Shahid <junaids@google.com>\nSigned-off-by: Jim Mattson <jmattson@google.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/b119019847fbcac36ed1384f166c91f177d070e7"},{"sha":"c550505b57832936aebb5eb376375bc258f8a807","author":{"name":"Jim Mattson","email":"69e6c825ffb81c81b96935a61b79166dbc1f7a9d@google.com"},"message":"kvm: x86: Pass through AMD_STIBP_ALWAYS_ON in GET_SUPPORTED_CPUID\n\nThis bit is purely advisory. Passing it through to the guest indicates\nthat the virtual processor, like the physical processor, prefers that\nSTIBP is only set once during boot and not changed.\n\nSigned-off-by: Jim Mattson <jmattson@google.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/c550505b57832936aebb5eb376375bc258f8a807"},{"sha":"d647eb63e67156fae44d2b467b1f314fc676de7a","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: svm: add nrips module parameter\n\nAllow testing code for old processors that lack the next RIP save\nfeature, by disabling usage of the next_rip field.\n\nNested hypervisors however get the feature unconditionally.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/d647eb63e67156fae44d2b467b1f314fc676de7a"},{"sha":"7be373b6de503cd1eed6be4f2780925a5af03230","author":{"name":"Wanpeng Li","email":"ab8ac92aed17a02f2e86162bb83ed8da94a09c3f@tencent.com"},"message":"KVM: LAPIC: remove the trailing newline used in the fmt parameter of TP_printk\n\nThe trailing newlines will lead to extra newlines in the trace file\nwhich looks like the following output, so remove it.\n\nqemu-system-x86-15695 [002] ...1 15774.839240: kvm_hv_timer_state: vcpu_id 0 hv_timer 1\n\nqemu-system-x86-15695 [002] ...1 15774.839309: kvm_hv_timer_state: vcpu_id 0 hv_timer 1\n\nCc: Paolo Bonzini <pbonzini@redhat.com>\nCc: Radim Krčmář <rkrcmar@redhat.com>\nSigned-off-by: Wanpeng Li <wanpengli@tencent.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/7be373b6de503cd1eed6be4f2780925a5af03230"},{"sha":"ab8bcf64971180e1344ce2c7e70c49b0f24f6b0d","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: cpuid: do_cpuid_ent works on a whole CPUID function\n\nRename it as well as __do_cpuid_ent and __do_cpuid_ent_emulated to have\n\"func\" in its name, and drop the index parameter which is always 0.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/ab8bcf64971180e1344ce2c7e70c49b0f24f6b0d"},{"sha":"54d360d41211006437bebf97513394693bd32623","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: cpuid: extract do_cpuid_7_mask and support multiple subleafs\n\nCPUID function 7 has multiple subleafs.  Instead of having nested\nswitch statements, move the logic to filter supported features to\na separate function, and call it for each subleaf.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/54d360d41211006437bebf97513394693bd32623"},{"sha":"d9aadaf689928ba896529cb684729923b21c2de5","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: cpuid: set struct kvm_cpuid_entry2 flags in do_cpuid_1_ent\n\ndo_cpuid_1_ent is typically called in two places by __do_cpuid_func\nfor CPUID functions that have subleafs.  Both places have to set\nthe KVM_CPUID_FLAG_SIGNIFCANT_INDEX.  Set that flag, and\nKVM_CPUID_FLAG_STATEFUL_FUNC as well, directly in do_cpuid_1_ent.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/d9aadaf689928ba896529cb684729923b21c2de5"},{"sha":"50a9e1a4b1dece60fd79ecdee25db01274a7f291","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: cpuid: rename do_cpuid_1_ent\n\ndo_cpuid_1_ent does not do the entire processing for a CPUID entry, it\nonly retrieves the host's values.  Rename it to match reality.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/50a9e1a4b1dece60fd79ecdee25db01274a7f291"},{"sha":"60cec433c485564bd7caac38a9df5c1ed79ee560","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: cpuid: remove has_leaf_count from struct kvm_cpuid_param\n\nThe has_leaf_count member was originally added for KVM's paravirtualization\nCPUID leaves.  However, since then the leaf count _has_ been added to those\nleaves as well, so we can drop that special case.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/60cec433c485564bd7caac38a9df5c1ed79ee560"},{"sha":"43fdcda96e2550c6d1c46fb8a78801aa2f7276ed","author":{"name":"Junaid Shahid","email":"aaf94ebe6313df785f223e22a08d9ac3811b753e@google.com"},"message":"kvm: x86: Do not release the page inside mmu_set_spte()\n\nRelease the page at the call-site where it was originally acquired.\nThis makes the exit code cleaner for most call sites, since they\ndo not need to duplicate code between success and the failure\nlabel.\n\nSigned-off-by: Junaid Shahid <junaids@google.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/43fdcda96e2550c6d1c46fb8a78801aa2f7276ed"},{"sha":"3fcf2d1bdeb6a513523cb2c77012a6b047aa859c","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: x86: make FNAME(fetch) and __direct_map more similar\n\nThese two functions are basically doing the same thing through\nkvm_mmu_get_page, link_shadow_page and mmu_set_spte; yet, for historical\nreasons, their code looks very different.  This patch tries to take the\nbest of each and make them very similar, so that it is easy to understand\nchanges that apply to both of them.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/3fcf2d1bdeb6a513523cb2c77012a6b047aa859c"},{"sha":"d679b32611c0102ce33b9e1a4e4b94854ed1812a","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: x86: remove now unneeded hugepage gfn adjustment\n\nAfter the previous patch, the low bits of the gfn are masked in\nboth FNAME(fetch) and __direct_map, so we do not need to clear them\nin transparent_hugepage_adjust.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/d679b32611c0102ce33b9e1a4e4b94854ed1812a"},{"sha":"e9f2a760b158551bfbef6db31d2cae45ab8072e5","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: x86: change kvm_mmu_page_get_gfn BUG_ON to WARN_ON\n\nNote that in such a case it is quite likely that KVM will BUG_ON\nin __pte_list_remove when the VM is closed.  However, there is no\nimmediate risk of memory corruption in the host so a WARN_ON is\nenough and it lets you gather traces for debugging.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/e9f2a760b158551bfbef6db31d2cae45ab8072e5"},{"sha":"335e192a3fa415e1202c8b9ecdaaecd643f823cc","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: x86: add tracepoints around __direct_map and FNAME(fetch)\n\nThese are useful in debugging shadow paging.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/335e192a3fa415e1202c8b9ecdaaecd643f823cc"},{"sha":"f087a02941feacf7d6f097522bc67c602fda18e6","author":{"name":"Sean Christopherson","email":"c0cf6ffb699e0a4c98b3fa7c5dd03fa419b94ed2@intel.com"},"message":"KVM: nVMX: Stash L1's CR3 in vmcs01.GUEST_CR3 on nested entry w/o EPT\n\nKVM does not have 100% coverage of VMX consistency checks, i.e. some\nchecks that cause VM-Fail may only be detected by hardware during a\nnested VM-Entry.  In such a case, KVM must restore L1's state to the\npre-VM-Enter state as L2's state has already been loaded into KVM's\nsoftware model.\n\nL1's CR3 and PDPTRs in particular are loaded from vmcs01.GUEST_*.  But\nwhen EPT is disabled, the associated fields hold KVM's shadow values,\nnot L1's \"real\" values.  Fortunately, when EPT is disabled the PDPTRs\ncome from memory, i.e. are not cached in the VMCS.  Which leaves CR3\nas the sole anomaly.\n\nA previously applied workaround to handle CR3 was to force nested early\nchecks if EPT is disabled:\n\n  commit 2b27924bb1d48 (\"KVM: nVMX: always use early vmcs check when EPT\n                         is disabled\")\n\nForcing nested early checks is undesirable as doing so adds hundreds of\ncycles to every nested VM-Entry.  Rather than take this performance hit,\nhandle CR3 by overwriting vmcs01.GUEST_CR3 with L1's CR3 during nested\nVM-Entry when EPT is disabled *and* nested early checks are disabled.\nBy stuffing vmcs01.GUEST_CR3, nested_vmx_restore_host_state() will\nnaturally restore the correct vcpu->arch.cr3 from vmcs01.GUEST_CR3.\n\nThese shenanigans work because nested_vmx_restore_host_state() does a\nfull kvm_mmu_reset_context(), i.e. unloads the current MMU, which\nguarantees vmcs01.GUEST_CR3 will be rewritten with a new shadow CR3\nprior to re-entering L1.\n\nvcpu->arch.root_mmu.root_hpa is set to INVALID_PAGE via:\n\n    nested_vmx_restore_host_state() ->\n        kvm_mmu_reset_context() ->\n            kvm_mmu_unload() ->\n                kvm_mmu_free_roots()\n\nkvm_mmu_unload() has WARN_ON(root_hpa != INVALID_PAGE), i.e. we can bank\non 'root_hpa == INVALID_PAGE' unless the implementation of\nkvm_mmu_reset_context() is changed.\n\nOn the way into L1, VMCS.GUEST_CR3 is guaranteed to be written (on a\nsuccessful entry) via:\n\n    vcpu_enter_guest() ->\n        kvm_mmu_reload() ->\n            kvm_mmu_load() ->\n                kvm_mmu_load_cr3() ->\n                    vmx_set_cr3()\n\nStuff vmcs01.GUEST_CR3 if and only if nested early checks are disabled\nas a \"late\" VM-Fail should never happen win that case (KVM WARNs), and\nthe conditional write avoids the need to restore the correct GUEST_CR3\nwhen nested_vmx_check_vmentry_hw() fails.\n\nSigned-off-by: Sean Christopherson <sean.j.christopherson@intel.com>\nMessage-Id: <20190607185534.24368-1-sean.j.christopherson@intel.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/f087a02941feacf7d6f097522bc67c602fda18e6"},{"sha":"1ef23e1f16088f5a91b25bb17585c2d532a097f7","author":{"name":"Krish Sadhukhan","email":"5dfdd34eb2d2c95b216f4788d0d55a5c8821ebfa@oracle.com"},"message":"KVM nVMX: Check Host Segment Registers and Descriptor Tables on vmentry of nested guests\n\nAccording to section \"Checks on Host Segment and Descriptor-Table\nRegisters\" in Intel SDM vol 3C, the following checks are performed on\nvmentry of nested guests:\n\n   - In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the\n     RPL (bits 1:0) and the TI flag (bit 2) must be 0.\n   - The selector fields for CS and TR cannot be 0000H.\n   - The selector field for SS cannot be 0000H if the \"host address-space\n     size\" VM-exit control is 0.\n   - On processors that support Intel 64 architecture, the base-address\n     fields for FS, GS and TR must contain canonical addresses.\n\nSigned-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>\nReviewed-by: Karl Heubaum <karl.heubaum@oracle.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/1ef23e1f16088f5a91b25bb17585c2d532a097f7"},{"sha":"101628ded5d990f7f364bd4d371ada9b2beaae64","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"KVM: LAPIC: ARBPRI is a reserved register for x2APIC\n\nkvm-unit-tests were adjusted to match bare metal behavior, but KVM\nitself was not doing what bare metal does; fix that.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/101628ded5d990f7f364bd4d371ada9b2beaae64"},{"sha":"01402cf81051f796dac7c60ca11d6147153ca46a","author":{"name":"Paolo Bonzini","email":"69d3ebcf5ee4e7f05a50dc23cd96655b730804b4@redhat.com"},"message":"kvm: LAPIC: write down valid APIC registers\n\nReplace a magic 64-bit mask with a list of valid registers, computing\nthe same mask in the end.\n\nSuggested-by: Liran Alon <liran.alon@oracle.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/01402cf81051f796dac7c60ca11d6147153ca46a"},{"sha":"548f7fb22234c6fe13c64459059fbd42058953c4","author":{"name":"Wanpeng Li","email":"ab8ac92aed17a02f2e86162bb83ed8da94a09c3f@tencent.com"},"message":"KVM: LAPIC: Retry tune per-vCPU timer_advance_ns if adaptive tuning goes insane\n\nRetry tune per-vCPU timer_advance_ns if adaptive tuning goes insane which\ncan happen sporadically in product environment.\n\nCc: Paolo Bonzini <pbonzini@redhat.com>\nCc: Radim Krčmář <rkrcmar@redhat.com>\nSigned-off-by: Wanpeng Li <wanpengli@tencent.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/548f7fb22234c6fe13c64459059fbd42058953c4"},{"sha":"f6b6aefee70aa5261deec7feab80c249bf58397f","author":{"name":"Bjorn Helgaas","email":"f10ec01be0c6b54271af5c550cd257810bdf3268@google.com"},"message":"PCI: Fix typos and whitespace errors\n\nFix typos in drivers/pci.  Comment and whitespace changes only.\n\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>\nReviewed-by: Randy Dunlap <rdunlap@infradead.org>","distinct":false,"url":"https://api.github.com/repos/Jackeagle/kernel_msm-3.18/commits/f6b6aefee70aa5261deec7feab80c249bf58397f"}]}
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